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@@ -169,11 +169,12 @@ unit rgobj;
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{ can be overriden to add cpu specific interferences }
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{ can be overriden to add cpu specific interferences }
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procedure add_cpu_interferences(p : tai);virtual;
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procedure add_cpu_interferences(p : tai);virtual;
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procedure add_constraints(reg:Tregister);virtual;
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procedure add_constraints(reg:Tregister);virtual;
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- procedure getregisterinline(list:Taasmoutput;position:Tai;subreg:Tsubregister;var result:Tregister);
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- procedure ungetregisterinline(list:Taasmoutput;position:Tai;r:Tregister);
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- function get_spill_subreg(r : tregister) : tsubregister;virtual;
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- procedure do_spill_read(list:Taasmoutput;instr:taicpu;const spilltemp:treference;const tempreg:tregister);virtual;
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- procedure do_spill_written(list:Taasmoutput;instr:taicpu;const spilltemp:treference;const tempreg:tregister);virtual;
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+ function getregisterinline(list:Taasmoutput;subreg:Tsubregister):Tregister;
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+ procedure ungetregisterinline(list:Taasmoutput;r:Tregister);
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+ function get_spill_subreg(r : tregister) : tsubregister;virtual;
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+ function do_spill_replace(list:Taasmoutput;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;virtual;
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+ procedure do_spill_read(list:Taasmoutput;pos:tai;const spilltemp:treference;tempreg:tregister);virtual;
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+ procedure do_spill_written(list:Taasmoutput;pos:tai;const spilltemp:treference;tempreg:tregister);virtual;
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function instr_spill_register(list:Taasmoutput;
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function instr_spill_register(list:Taasmoutput;
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instr:taicpu;
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instr:taicpu;
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@@ -212,8 +213,8 @@ unit rgobj;
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procedure epilogue_colouring;
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procedure epilogue_colouring;
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{# Colour the registers; that is do the register allocation.}
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{# Colour the registers; that is do the register allocation.}
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procedure colour_registers;
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procedure colour_registers;
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- {# Spills certain registers in the specified assembler list.}
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- procedure insert_regalloc_info(list:Taasmoutput;headertai:tai);
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+ procedure insert_regalloc_info(list:Taasmoutput;u:tsuperregister);
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+ procedure insert_regalloc_info_all(list:Taasmoutput);
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procedure generate_interference_graph(list:Taasmoutput;headertai:tai);
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procedure generate_interference_graph(list:Taasmoutput;headertai:tai);
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procedure translate_registers(list:Taasmoutput);
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procedure translate_registers(list:Taasmoutput);
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function spill_registers(list:Taasmoutput;headertai:tai):boolean;virtual;
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function spill_registers(list:Taasmoutput;headertai:tai):boolean;virtual;
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@@ -478,7 +479,7 @@ unit rgobj;
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begin
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begin
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if (getsupreg(r)>=first_imaginary) then
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if (getsupreg(r)>=first_imaginary) then
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InternalError(2004020901);
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InternalError(2004020901);
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- list.concat(Tai_regalloc.dealloc(r));
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+ list.concat(Tai_regalloc.dealloc(r,nil));
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end;
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end;
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@@ -490,7 +491,7 @@ unit rgobj;
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if supreg>=first_imaginary then
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if supreg>=first_imaginary then
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internalerror(2003121503);
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internalerror(2003121503);
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include(used_in_proc,supreg);
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include(used_in_proc,supreg);
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- list.concat(Tai_regalloc.alloc(r));
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+ list.concat(Tai_regalloc.alloc(r,nil));
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end;
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end;
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@@ -523,7 +524,7 @@ unit rgobj;
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i:Tsuperregister;
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i:Tsuperregister;
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begin
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begin
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{ Insert regalloc info for imaginary registers }
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{ Insert regalloc info for imaginary registers }
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- insert_regalloc_info(list,headertai);
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+ insert_regalloc_info_all(list);
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ibitmap:=tinterferencebitmap.create;
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ibitmap:=tinterferencebitmap.create;
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generate_interference_graph(list,headertai);
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generate_interference_graph(list,headertai);
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{ Don't do the real allocation when -sr is passed }
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{ Don't do the real allocation when -sr is passed }
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@@ -539,6 +540,8 @@ unit rgobj;
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if spillednodes.length<>0 then
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if spillednodes.length<>0 then
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begin
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begin
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inc(spillingcounter);
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inc(spillingcounter);
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+ if spillingcounter>maxspillingcounter then
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+ exit;
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if spillingcounter>maxspillingcounter then
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if spillingcounter>maxspillingcounter then
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internalerror(200309041);
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internalerror(200309041);
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endspill:=not spill_registers(list,headertai);
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endspill:=not spill_registers(list,headertai);
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@@ -1370,81 +1373,80 @@ unit rgobj;
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end;
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end;
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end;
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end;
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- procedure trgobj.getregisterinline(list:Taasmoutput;
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- position:Tai;subreg:Tsubregister;var result:Tregister);
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- var p:Tsuperregister;
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- r:Tregister;
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- begin
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- p:=getnewreg(subreg);
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- live_registers.add(p);
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- r:=newreg(regtype,p,subreg);
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- if position=nil then
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- list.insert(Tai_regalloc.alloc(r))
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- else
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- list.insertafter(Tai_regalloc.alloc(r),position);
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- add_edges_used(p);
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- add_constraints(r);
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- result:=r;
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- end;
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+ function trgobj.getregisterinline(list:Taasmoutput;subreg:Tsubregister):Tregister;
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+ var
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+ p : Tsuperregister;
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+ r : Tregister;
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+ begin
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+ p:=getnewreg(subreg);
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+ live_registers.add(p);
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+ result:=newreg(regtype,p,subreg);
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+ add_edges_used(p);
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+ add_constraints(result);
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+ end;
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- procedure trgobj.ungetregisterinline(list:Taasmoutput;
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- position:Tai;r:Tregister);
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-
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- var supreg:Tsuperregister;
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- begin
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- supreg:=getsupreg(r);
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- live_registers.delete(supreg);
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- if position=nil then
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- list.insert(Tai_regalloc.dealloc(r))
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- else
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- list.insertafter(Tai_regalloc.dealloc(r),position);
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- end;
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+ procedure trgobj.ungetregisterinline(list:Taasmoutput;r:Tregister);
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+ var
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+ supreg:Tsuperregister;
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+ begin
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+ supreg:=getsupreg(r);
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+ live_registers.delete(supreg);
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+ insert_regalloc_info(list,supreg);
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+ end;
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- procedure trgobj.insert_regalloc_info(list:Taasmoutput;headertai:tai);
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+ procedure trgobj.insert_regalloc_info(list:Taasmoutput;u:tsuperregister);
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var
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var
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- supreg : tsuperregister;
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p : tai;
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p : tai;
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r : tregister;
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r : tregister;
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begin
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begin
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{ Insert regallocs for all imaginary registers }
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{ Insert regallocs for all imaginary registers }
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- for supreg:=first_imaginary to maxreg-1 do
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- with reginfo[supreg] do
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- begin
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- r:=newreg(regtype,supreg,subreg);
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- if assigned(live_start) then
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- begin
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+ with reginfo[u] do
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+ begin
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+ r:=newreg(regtype,u,subreg);
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+ if assigned(live_start) then
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+ begin
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{$ifdef EXTDEBUG}
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{$ifdef EXTDEBUG}
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- if live_start=live_end then
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- Comment(V_Warning,'Register '+std_regname(r)+' is only used once');
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+ if live_start=live_end then
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+ Comment(V_Warning,'Register '+std_regname(r)+' is only used once');
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{$endif EXTDEBUG}
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{$endif EXTDEBUG}
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- list.insertbefore(Tai_regalloc.alloc(r),live_start);
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- { Insert live end deallocation before reg allocations
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- to reduce conflicts }
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- p:=live_end;
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- while assigned(p) and
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- assigned(p.previous) and
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- (tai(p.previous).typ=ait_regalloc) and
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- (tai_regalloc(p.previous).ratype=ra_alloc) and
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- (tai_regalloc(p.previous).reg<>r) do
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- p:=tai(p.previous);
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- { , but add release after sync }
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- if assigned(p) and
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- (p.typ=ait_regalloc) and
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- (tai_regalloc(p).ratype=ra_sync) then
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- p:=tai(p.next);
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- if assigned(p) then
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- list.insertbefore(Tai_regalloc.dealloc(r),p)
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- else
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- list.concat(Tai_regalloc.dealloc(r));
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- end
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+ list.insertbefore(Tai_regalloc.alloc(r,live_start),live_start);
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+ { Insert live end deallocation before reg allocations
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+ to reduce conflicts }
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+ p:=live_end;
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+ while assigned(p) and
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+ assigned(p.previous) and
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+ (tai(p.previous).typ=ait_regalloc) and
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+ (tai_regalloc(p.previous).ratype=ra_alloc) and
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+ (tai_regalloc(p.previous).reg<>r) do
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+ p:=tai(p.previous);
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+ { , but add release after sync }
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+ if assigned(p) and
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+ (p.typ=ait_regalloc) and
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+ (tai_regalloc(p).ratype=ra_sync) then
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+ p:=tai(p.next);
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+ if assigned(p) then
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+ list.insertbefore(Tai_regalloc.dealloc(r,live_end),p)
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+ else
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+ list.concat(Tai_regalloc.dealloc(r,live_end));
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+ end
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{$ifdef EXTDEBUG}
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{$ifdef EXTDEBUG}
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- else
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- Comment(V_Warning,'Register '+std_regname(r)+' not used');
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+ else
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+ Comment(V_Warning,'Register '+std_regname(r)+' not used');
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{$endif EXTDEBUG}
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{$endif EXTDEBUG}
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- end;
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+ end;
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+ end;
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+
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+
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+ procedure trgobj.insert_regalloc_info_all(list:Taasmoutput);
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+ var
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+ supreg : tsuperregister;
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+ begin
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+ { Insert regallocs for all imaginary registers }
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+ for supreg:=first_imaginary to maxreg-1 do
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+ insert_regalloc_info(list,supreg);
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end;
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end;
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@@ -1569,6 +1571,7 @@ unit rgobj;
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ait_instruction:
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ait_instruction:
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with Taicpu(p) do
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with Taicpu(p) do
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begin
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begin
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+ aktfilepos:=fileinfo;
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for i:=0 to ops-1 do
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for i:=0 to ops-1 do
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with oper[i]^ do
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with oper[i]^ do
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case typ of
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case typ of
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@@ -1610,6 +1613,7 @@ unit rgobj;
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end;
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end;
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p:=Tai(p.next);
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p:=Tai(p.next);
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end;
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end;
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+ aktfilepos:=current_procinfo.exitpos;
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end;
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end;
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@@ -1702,21 +1706,21 @@ unit rgobj;
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end;
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end;
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- procedure Trgobj.do_spill_read(list:Taasmoutput;instr:taicpu;const spilltemp:treference;const tempreg:tregister);
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- var
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- helpins : Tai;
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+ function trgobj.do_spill_replace(list:Taasmoutput;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;
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begin
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begin
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- helpins:=spilling_create_load(spilltemp,tempreg);
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- list.insertbefore(helpins,instr);
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+ result:=false;
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end;
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end;
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- procedure Trgobj.do_spill_written(list:Taasmoutput;instr:taicpu;const spilltemp:treference;const tempreg:tregister);
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- var
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- helpins : Tai;
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+ procedure Trgobj.do_spill_read(list:Taasmoutput;pos:tai;const spilltemp:treference;tempreg:tregister);
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+ begin
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+ list.insertafter(spilling_create_load(spilltemp,tempreg),pos);
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+ end;
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+
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+
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+ procedure Trgobj.do_spill_written(list:Taasmoutput;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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begin
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- helpins:=spilling_create_store(tempreg,spilltemp);
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- list.insertafter(helpins,instr);
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+ list.insertafter(spilling_create_store(tempreg,spilltemp),pos);
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end;
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end;
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@@ -1791,7 +1795,8 @@ unit rgobj;
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end;
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end;
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var
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var
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- counter2 : longint;
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+ loadpos,
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+ storepos : tai;
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oldlive_registers : tsuperregisterworklist;
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oldlive_registers : tsuperregisterworklist;
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begin
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begin
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result := false;
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result := false;
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@@ -1837,42 +1842,124 @@ unit rgobj;
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if not spilled then
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if not spilled then
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exit;
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exit;
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- { Add conflicts with all non-spilled registers }
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+{$ifdef x86}
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+ { Try replacing the register with the spilltemp. This is usefull only
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+ for the i386,x86_64 that support memory locations for several instructions }
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+ for counter := 0 to pred(regindex) do
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+ with regs[counter] do
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+ begin
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+ if mustbespilled then
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+ begin
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+ if do_spill_replace(list,instr,orgreg,spilltemplist[orgreg]) then
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+ mustbespilled:=false;
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+ end;
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+ end;
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+{$endif x86}
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+
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+ {
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+ There are registers that need are spilled. We generate the
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+ following code for it. The used positions where code need
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+ to be inserted are marked using #. Note that code is always inserted
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+ before the positions using pos.previous. This way the position is always
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+ the same since pos doesn't change, but pos.previous is modified everytime
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+ new code is inserted.
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+
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+ [
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+ - reg_allocs load spills
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+ - load spills
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+ ]
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+ [#loadpos
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+ - reg_deallocs
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+ - reg_allocs
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+ ]
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+ [
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+ - reg_deallocs for load-only spills
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+ - reg_allocs for store-only spills
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+ ]
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+ [#instr
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+ - original instruction
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+ ]
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+ [
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+ - store spills
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+ - reg_deallocs store spills
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+ ]
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+ [#storepos
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+ ]
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+ }
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+
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+ result := true;
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oldlive_registers.copyfrom(live_registers);
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oldlive_registers.copyfrom(live_registers);
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- for counter2 := 0 to pred(regindex) do
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+
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+ { Process all tai_regallocs belonging to this instruction. All
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+ released registers are also added to the live_registers because
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+ they can't be used during the spilling }
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+ loadpos:=tai(instr.previous);
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+ while assigned(loadpos) and
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+ (loadpos.typ=ait_regalloc) and
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+ (tai_regalloc(loadpos).instr=instr) do
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begin
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begin
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- if (not regs[counter2].mustbespilled) then
|
|
|
|
- live_registers.add(get_alias(regs[counter2].orgreg));
|
|
|
|
|
|
+ if tai_regalloc(loadpos).ratype=ra_dealloc then
|
|
|
|
+ live_registers.add(getsupreg(tai_regalloc(loadpos).reg));
|
|
|
|
+ loadpos:=tai(loadpos.previous);
|
|
end;
|
|
end;
|
|
|
|
+ loadpos:=tai(loadpos.next);
|
|
|
|
|
|
- { generate the spilling code }
|
|
|
|
- result := true;
|
|
|
|
|
|
+ { Load the spilled registers }
|
|
for counter := 0 to pred(regindex) do
|
|
for counter := 0 to pred(regindex) do
|
|
with regs[counter] do
|
|
with regs[counter] do
|
|
begin
|
|
begin
|
|
- if mustbespilled then
|
|
|
|
|
|
+ if mustbespilled and regread then
|
|
begin
|
|
begin
|
|
- getregisterinline(list,tai(instr.previous),get_spill_subreg(regs[counter].spillreg),tempreg);
|
|
|
|
|
|
+ tempreg:=getregisterinline(list,get_spill_subreg(regs[counter].spillreg));
|
|
|
|
+ do_spill_read(list,tai(loadpos.previous),spilltemplist[orgreg],tempreg);
|
|
|
|
+ end;
|
|
|
|
+ end;
|
|
|
|
|
|
- if regread then
|
|
|
|
- do_spill_read(list,instr,spilltemplist[orgreg],tempreg);
|
|
|
|
- if regwritten then
|
|
|
|
- do_spill_written(list,instr,spilltemplist[orgreg],tempreg);
|
|
|
|
|
|
+ { Release temp registers of read-only registers, and add reference of the instruction
|
|
|
|
+ to the reginfo }
|
|
|
|
+ for counter := 0 to pred(regindex) do
|
|
|
|
+ with regs[counter] do
|
|
|
|
+ begin
|
|
|
|
+ if mustbespilled and regread and (not regwritten) then
|
|
|
|
+ begin
|
|
|
|
+ { The original instruction will be the next that uses this register }
|
|
|
|
+ add_reg_instruction(instr,tempreg);
|
|
|
|
+ ungetregisterinline(list,tempreg);
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
- { Release temp registers after all registers for the instruction are spilled }
|
|
|
|
|
|
+ { Allocate temp registers of write-only registers, and add reference of the instruction
|
|
|
|
+ to the reginfo }
|
|
for counter := 0 to pred(regindex) do
|
|
for counter := 0 to pred(regindex) do
|
|
with regs[counter] do
|
|
with regs[counter] do
|
|
begin
|
|
begin
|
|
- if mustbespilled then
|
|
|
|
- ungetregisterinline(list,instr,tempreg);
|
|
|
|
|
|
+ if mustbespilled and regwritten then
|
|
|
|
+ begin
|
|
|
|
+ { When the register is also loaded there is already a register assigned }
|
|
|
|
+ if (not regread) then
|
|
|
|
+ tempreg:=getregisterinline(list,get_spill_subreg(regs[counter].spillreg));
|
|
|
|
+ { The original instruction will be the next that uses this register, this
|
|
|
|
+ also needs to be done for read-write registers }
|
|
|
|
+ add_reg_instruction(instr,tempreg);
|
|
|
|
+ end;
|
|
end;
|
|
end;
|
|
|
|
|
|
- { restore live registers }
|
|
|
|
|
|
+ { we are now at the original instruction, restore live registers }
|
|
live_registers.done;
|
|
live_registers.done;
|
|
live_registers:=oldlive_registers;
|
|
live_registers:=oldlive_registers;
|
|
|
|
|
|
|
|
+ { store the spilled registers }
|
|
|
|
+ storepos:=tai(instr.next);
|
|
|
|
+ for counter := 0 to pred(regindex) do
|
|
|
|
+ with regs[counter] do
|
|
|
|
+ begin
|
|
|
|
+ if mustbespilled and regwritten then
|
|
|
|
+ begin
|
|
|
|
+ do_spill_written(list,tai(storepos.previous),spilltemplist[orgreg],tempreg);
|
|
|
|
+ ungetregisterinline(list,tempreg);
|
|
|
|
+ end;
|
|
|
|
+ end;
|
|
|
|
+
|
|
{ substitute registers }
|
|
{ substitute registers }
|
|
for counter:=0 to instr.ops-1 do
|
|
for counter:=0 to instr.ops-1 do
|
|
with instr.oper[counter]^ do
|
|
with instr.oper[counter]^ do
|
|
@@ -1880,12 +1967,16 @@ unit rgobj;
|
|
case typ of
|
|
case typ of
|
|
top_reg:
|
|
top_reg:
|
|
begin
|
|
begin
|
|
- tryreplacereg(reg);
|
|
|
|
|
|
+ if (getregtype(reg) = regtype) then
|
|
|
|
+ tryreplacereg(reg);
|
|
end;
|
|
end;
|
|
top_ref:
|
|
top_ref:
|
|
begin
|
|
begin
|
|
- tryreplacereg(ref^.base);
|
|
|
|
- tryreplacereg(ref^.index);
|
|
|
|
|
|
+ if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then
|
|
|
|
+ begin
|
|
|
|
+ tryreplacereg(ref^.base);
|
|
|
|
+ tryreplacereg(ref^.index);
|
|
|
|
+ end;
|
|
end;
|
|
end;
|
|
{$ifdef ARM}
|
|
{$ifdef ARM}
|
|
top_shifterop:
|
|
top_shifterop:
|
|
@@ -1903,7 +1994,10 @@ unit rgobj;
|
|
end.
|
|
end.
|
|
{
|
|
{
|
|
$Log$
|
|
$Log$
|
|
- Revision 1.138 2004-10-04 20:46:22 peter
|
|
|
|
|
|
+ Revision 1.139 2004-10-05 20:41:01 peter
|
|
|
|
+ * more spilling rewrites
|
|
|
|
+
|
|
|
|
+ Revision 1.138 2004/10/04 20:46:22 peter
|
|
* spilling code rewritten for x86. It now used the generic
|
|
* spilling code rewritten for x86. It now used the generic
|
|
spilling routines. Special x86 optimization still needs
|
|
spilling routines. Special x86 optimization still needs
|
|
to be added.
|
|
to be added.
|