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@@ -4,10 +4,6 @@
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Contains the base types for the i386
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- * This code was inspired by the NASM sources
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- The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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- Julian Hall. All rights reserved.
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-
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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@@ -37,555 +33,365 @@ interface
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uses
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globals,cutils,cclasses,aasm,cpuinfo,cginfo;
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-const
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-{ Size of the instruction table converted by nasmconv.pas }
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- instabentries = {$i i386nop.inc}
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- maxinfolen = 8;
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-
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-{ By default we want everything }
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-{$define ATTOP}
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-{$define INTELOP}
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-{$define ITTABLE}
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-
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-{ We Don't need the intel style opcodes if we don't have a intel
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- reader or generator }
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-{$ifdef NORA386INT}
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- {$ifdef NOAG386NSM}
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- {$ifdef NOAG386INT}
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- {$undef INTELOP}
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- {$endif}
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- {$endif}
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-{$endif}
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-
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-{ We Don't need the AT&T style opcodes if we don't have a AT&T
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- reader or generator }
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-{$ifdef NORA386ATT}
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- {$ifdef NOAG386ATT}
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- {$undef ATTOP}
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- {$ifdef NOAG386DIR}
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- {$undef ATTREG}
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- {$endif}
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- {$endif}
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-{$endif}
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-
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-{ We need the AT&T suffix table for both asm readers and AT&T writer }
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-{$define ATTSUF}
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-{$ifdef NORA386INT}
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- {$ifdef NORA386ATT}
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- {$ifdef NOAG386ATT}
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- {$undef ATTSUF}
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- {$endif}
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- {$endif}
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-{$endif}
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-
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-const
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-{ Operand types }
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- OT_NONE = $00000000;
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-
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- OT_BITS8 = $00000001; { size, and other attributes, of the operand }
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- OT_BITS16 = $00000002;
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- OT_BITS32 = $00000004;
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- OT_BITS64 = $00000008; { FPU only }
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- OT_BITS80 = $00000010;
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- OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
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- OT_NEAR = $00000040;
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- OT_SHORT = $00000080;
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-
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- OT_SIZE_MASK = $000000FF; { all the size attributes }
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- OT_NON_SIZE = longint(not OT_SIZE_MASK);
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-
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- OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
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-
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- OT_TO = $00000200; { operand is followed by a colon }
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- { reverse effect in FADD, FSUB &c }
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- OT_COLON = $00000400;
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-
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- OT_REGISTER = $00001000;
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- OT_IMMEDIATE = $00002000;
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- OT_IMM8 = $00002001;
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- OT_IMM16 = $00002002;
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- OT_IMM32 = $00002004;
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- OT_IMM64 = $00002008;
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- OT_IMM80 = $00002010;
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- OT_REGMEM = $00200000; { for r/m, ie EA, operands }
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- OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
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- OT_REG8 = $00201001;
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- OT_REG16 = $00201002;
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- OT_REG32 = $00201004;
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- OT_MMXREG = $00201008; { MMX registers }
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- OT_XMMREG = $00201010; { Katmai registers }
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- OT_MEMORY = $00204000; { register number in 'basereg' }
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- OT_MEM8 = $00204001;
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- OT_MEM16 = $00204002;
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- OT_MEM32 = $00204004;
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- OT_MEM64 = $00204008;
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- OT_MEM80 = $00204010;
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- OT_FPUREG = $01000000; { floating point stack registers }
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- OT_FPU0 = $01000800; { FPU stack register zero }
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- OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
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- { a mask for the following }
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- OT_REG_ACCUM = $00211000; { accumulator: AL, AX or EAX }
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- OT_REG_AL = $00211001; { REG_ACCUM | BITSxx }
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- OT_REG_AX = $00211002; { ditto }
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- OT_REG_EAX = $00211004; { and again }
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- OT_REG_COUNT = $00221000; { counter: CL, CX or ECX }
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- OT_REG_CL = $00221001; { REG_COUNT | BITSxx }
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- OT_REG_CX = $00221002; { ditto }
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- OT_REG_ECX = $00221004; { another one }
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- OT_REG_DX = $00241002;
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-
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- OT_REG_SREG = $00081002; { any segment register }
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- OT_REG_CS = $01081002; { CS }
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- OT_REG_DESS = $02081002; { DS, ES, SS (non-CS 86 registers) }
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- OT_REG_FSGS = $04081002; { FS, GS (386 extended registers) }
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-
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- OT_REG_CDT = $00101004; { CRn, DRn and TRn }
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- OT_REG_CREG = $08101004; { CRn }
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- OT_REG_CR4 = $08101404; { CR4 (Pentium only) }
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- OT_REG_DREG = $10101004; { DRn }
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- OT_REG_TREG = $20101004; { TRn }
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-
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- OT_MEM_OFFS = $00604000; { special type of EA }
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- { simple [address] offset }
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- OT_ONENESS = $00800000; { special type of immediate operand }
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- { so UNITY == IMMEDIATE | ONENESS }
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- OT_UNITY = $00802000; { for shift/rotate instructions }
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-
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-{Instruction flags }
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- IF_NONE = $00000000;
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- IF_SM = $00000001; { size match first two operands }
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- IF_SM2 = $00000002;
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- IF_SB = $00000004; { unsized operands can't be non-byte }
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- IF_SW = $00000008; { unsized operands can't be non-word }
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- IF_SD = $00000010; { unsized operands can't be nondword }
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- IF_AR0 = $00000020; { SB, SW, SD applies to argument 0 }
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- IF_AR1 = $00000040; { SB, SW, SD applies to argument 1 }
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- IF_AR2 = $00000060; { SB, SW, SD applies to argument 2 }
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- IF_ARMASK = $00000060; { mask for unsized argument spec }
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- IF_PRIV = $00000100; { it's a privileged instruction }
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- IF_SMM = $00000200; { it's only valid in SMM }
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- IF_PROT = $00000400; { it's protected mode only }
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- IF_UNDOC = $00001000; { it's an undocumented instruction }
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- IF_FPU = $00002000; { it's an FPU instruction }
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- IF_MMX = $00004000; { it's an MMX instruction }
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- IF_3DNOW = $00008000; { it's a 3DNow! instruction }
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- IF_SSE = $00010000; { it's a SSE (KNI, MMX2) instruction }
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- IF_PMASK =
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- longint($FF000000); { the mask for processor types }
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- IF_PFMASK =
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- longint($F001FF00); { the mask for disassembly "prefer" }
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- IF_8086 = $00000000; { 8086 instruction }
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- IF_186 = $01000000; { 186+ instruction }
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- IF_286 = $02000000; { 286+ instruction }
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- IF_386 = $03000000; { 386+ instruction }
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- IF_486 = $04000000; { 486+ instruction }
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- IF_PENT = $05000000; { Pentium instruction }
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- IF_P6 = $06000000; { P6 instruction }
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- IF_KATMAI = $07000000; { Katmai instructions }
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- IF_CYRIX = $10000000; { Cyrix-specific instruction }
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- IF_AMD = $20000000; { AMD-specific instruction }
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- { added flags }
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- IF_PRE = $40000000; { it's a prefix instruction }
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- IF_PASS2 =
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- longint($80000000); { if the instruction can change in a second pass }
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-
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-type
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-
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- TAsmOp={$i i386op.inc}
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-
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- {# This should define the array of instructions as string }
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- op2strtable=array[tasmop] of string[11];
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-
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-Const
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-
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- {# First value of opcode enumeration }
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- firstop = low(tasmop);
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- {# Last value of opcode enumeration }
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- lastop = high(tasmop);
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-
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{*****************************************************************************
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- Operand Sizes
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+ Assembler Opcodes
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*****************************************************************************}
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-type
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- topsize = (S_NO,
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- S_B,S_W,S_L,S_BW,S_BL,S_WL,
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- S_IS,S_IL,S_IQ,
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- S_FS,S_FL,S_FX,S_D,S_Q,S_FV,
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- S_NEAR,S_FAR,S_SHORT
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- );
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-
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-const
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- { Intel style operands ! }
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- opsize_2_type:array[0..2,topsize] of longint=(
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- (OT_NONE,
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- OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS16,OT_BITS32,OT_BITS32,
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- OT_BITS16,OT_BITS32,OT_BITS64,
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- OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_BITS64,OT_BITS64,
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- OT_NEAR,OT_FAR,OT_SHORT
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- ),
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- (OT_NONE,
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- OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS8,OT_BITS8,OT_BITS16,
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- OT_BITS16,OT_BITS32,OT_BITS64,
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- OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_BITS64,OT_BITS64,
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- OT_NEAR,OT_FAR,OT_SHORT
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- ),
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- (OT_NONE,
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- OT_BITS8,OT_BITS16,OT_BITS32,OT_NONE,OT_NONE,OT_NONE,
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- OT_BITS16,OT_BITS32,OT_BITS64,
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- OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_BITS64,OT_BITS64,
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- OT_NEAR,OT_FAR,OT_SHORT
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- )
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- );
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+ type
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+ TAsmOp={$i i386op.inc}
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+ {# This should define the array of instructions as string }
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+ op2strtable=array[tasmop] of string[11];
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+ Const
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+ {# First value of opcode enumeration }
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+ firstop = low(tasmop);
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+ {# Last value of opcode enumeration }
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+ lastop = high(tasmop);
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{*****************************************************************************
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- Conditions
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+ Operand Sizes
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*****************************************************************************}
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-type
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- TAsmCond=(C_None,
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- C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
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- C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,
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- C_NS,C_NZ,C_O,C_P,C_PE,C_PO,C_S,C_Z
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- );
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-
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-const
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- cond2str:array[TAsmCond] of string[3]=('',
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- 'a','ae','b','be','c','e','g','ge','l','le','na','nae',
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- 'nb','nbe','nc','ne','ng','nge','nl','nle','no','np',
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- 'ns','nz','o','p','pe','po','s','z'
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- );
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- inverse_cond:array[TAsmCond] of TAsmCond=(C_None,
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- C_NA,C_NAE,C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_A,C_AE,
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- C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_O,C_P,
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- C_S,C_Z,C_NO,C_NP,C_NP,C_P,C_NS,C_NZ
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- );
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-
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+ type
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+ topsize = (S_NO,
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+ S_B,S_W,S_L,S_BW,S_BL,S_WL,
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+ S_IS,S_IL,S_IQ,
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+ S_FS,S_FL,S_FX,S_D,S_Q,S_FV,
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+ S_NEAR,S_FAR,S_SHORT
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+ );
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{*****************************************************************************
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Registers
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*****************************************************************************}
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-type
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- {# Enumeration for all possible registers for cpu. It
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- is to note that all registers of the same type
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- (for example all FPU registers), should be grouped
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- together.
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- }
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- { don't change the order }
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- { it's used by the register size conversions }
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- tregister = (R_NO,
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- R_EAX,R_ECX,R_EDX,R_EBX,R_ESP,R_EBP,R_ESI,R_EDI,
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- R_AX,R_CX,R_DX,R_BX,R_SP,R_BP,R_SI,R_DI,
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- R_AL,R_CL,R_DL,R_BL,R_AH,R_CH,R_BH,R_DH,
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- R_CS,R_DS,R_ES,R_SS,R_FS,R_GS,
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- R_ST,R_ST0,R_ST1,R_ST2,R_ST3,R_ST4,R_ST5,R_ST6,R_ST7,
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- R_DR0,R_DR1,R_DR2,R_DR3,R_DR6,R_DR7,
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- R_CR0,R_CR2,R_CR3,R_CR4,
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- R_TR3,R_TR4,R_TR5,R_TR6,R_TR7,
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- R_MM0,R_MM1,R_MM2,R_MM3,R_MM4,R_MM5,R_MM6,R_MM7,
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- R_XMM0,R_XMM1,R_XMM2,R_XMM3,R_XMM4,R_XMM5,R_XMM6,R_XMM7
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- );
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-
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- {# Set type definition for registers }
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- tregisterset = set of tregister;
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-
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- {# Type definition for the array of string of register nnames }
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- reg2strtable = array[tregister] of string[6];
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-
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-const
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- {# First register in the tregister enumeration }
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- firstreg = low(tregister);
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- {# Last register in the tregister enumeration }
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- lastreg = high(tregister);
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-
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- firstsreg = R_CS;
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- lastsreg = R_GS;
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-
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- regset8bit : tregisterset = [R_AL..R_DH];
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- regset16bit : tregisterset = [R_AX..R_DI,R_CS..R_SS];
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- regset32bit : tregisterset = [R_EAX..R_EDI];
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-
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- { Convert reg to opsize }
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- reg2opsize : array[firstreg..lastreg] of topsize = (S_NO,
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- S_L,S_L,S_L,S_L,S_L,S_L,S_L,S_L,
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- S_W,S_W,S_W,S_W,S_W,S_W,S_W,S_W,
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- S_B,S_B,S_B,S_B,S_B,S_B,S_B,S_B,
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- S_W,S_W,S_W,S_W,S_W,S_W,
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- S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,
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- S_L,S_L,S_L,S_L,S_L,S_L,
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- S_L,S_L,S_L,S_L,
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- S_L,S_L,S_L,S_L,S_L,
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- S_D,S_D,S_D,S_D,S_D,S_D,S_D,S_D,
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- S_D,S_D,S_D,S_D,S_D,S_D,S_D,S_D
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- );
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-
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- { Convert reg to operand type }
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- reg2type : array[firstreg..lastreg] of longint = (OT_NONE,
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- OT_REG_EAX,OT_REG_ECX,OT_REG32,OT_REG32,OT_REG32,OT_REG32,OT_REG32,OT_REG32,
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- OT_REG_AX,OT_REG_CX,OT_REG_DX,OT_REG16,OT_REG16,OT_REG16,OT_REG16,OT_REG16,
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- OT_REG_AL,OT_REG_CL,OT_REG8,OT_REG8,OT_REG8,OT_REG8,OT_REG8,OT_REG8,
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- OT_REG_CS,OT_REG_DESS,OT_REG_DESS,OT_REG_DESS,OT_REG_FSGS,OT_REG_FSGS,
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- OT_FPU0,OT_FPU0,OT_FPUREG,OT_FPUREG,OT_FPUREG,OT_FPUREG,OT_FPUREG,OT_FPUREG,OT_FPUREG,
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- OT_REG_DREG,OT_REG_DREG,OT_REG_DREG,OT_REG_DREG,OT_REG_DREG,OT_REG_DREG,
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- OT_REG_CREG,OT_REG_CREG,OT_REG_CREG,OT_REG_CR4,
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- OT_REG_TREG,OT_REG_TREG,OT_REG_TREG,OT_REG_TREG,OT_REG_TREG,
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- OT_MMXREG,OT_MMXREG,OT_MMXREG,OT_MMXREG,OT_MMXREG,OT_MMXREG,OT_MMXREG,OT_MMXREG,
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- OT_XMMREG,OT_XMMREG,OT_XMMREG,OT_XMMREG,OT_XMMREG,OT_XMMREG,OT_XMMREG,OT_XMMREG
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- );
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-
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- {# Standard opcode string table (for each tasmop enumeration). The
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- opcode strings should conform to the names as defined by the
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- processor manufacturer.
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- }
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- std_op2str:op2strtable={$i i386int.inc}
|
|
|
-
|
|
|
- {# Standard register table (for each tregister enumeration). The
|
|
|
- register strings should conform to the the names as defined
|
|
|
- by the processor manufacturer
|
|
|
- }
|
|
|
- std_reg2str : reg2strtable = ('',
|
|
|
- 'eax','ecx','edx','ebx','esp','ebp','esi','edi',
|
|
|
- 'ax','cx','dx','bx','sp','bp','si','di',
|
|
|
- 'al','cl','dl','bl','ah','ch','bh','dh',
|
|
|
- 'cs','ds','es','ss','fs','gs',
|
|
|
- 'st','st(0)','st(1)','st(2)','st(3)','st(4)','st(5)','st(6)','st(7)',
|
|
|
- 'dr0','dr1','dr2','dr3','dr6','dr7',
|
|
|
- 'cr0','cr2','cr3','cr4',
|
|
|
- 'tr3','tr4','tr5','tr6','tr7',
|
|
|
- 'mm0','mm1','mm2','mm3','mm4','mm5','mm6','mm7',
|
|
|
- 'xmm0','xmm1','xmm2','xmm3','xmm4','xmm5','xmm6','xmm7'
|
|
|
- );
|
|
|
+ type
|
|
|
+ {# Enumeration for all possible registers for cpu. It
|
|
|
+ is to note that all registers of the same type
|
|
|
+ (for example all FPU registers), should be grouped
|
|
|
+ together.
|
|
|
+ }
|
|
|
+ { don't change the order }
|
|
|
+ { it's used by the register size conversions }
|
|
|
+ tregister = (R_NO,
|
|
|
+ R_EAX,R_ECX,R_EDX,R_EBX,R_ESP,R_EBP,R_ESI,R_EDI,
|
|
|
+ R_AX,R_CX,R_DX,R_BX,R_SP,R_BP,R_SI,R_DI,
|
|
|
+ R_AL,R_CL,R_DL,R_BL,R_AH,R_CH,R_BH,R_DH,
|
|
|
+ R_CS,R_DS,R_ES,R_SS,R_FS,R_GS,
|
|
|
+ R_ST,R_ST0,R_ST1,R_ST2,R_ST3,R_ST4,R_ST5,R_ST6,R_ST7,
|
|
|
+ R_DR0,R_DR1,R_DR2,R_DR3,R_DR6,R_DR7,
|
|
|
+ R_CR0,R_CR2,R_CR3,R_CR4,
|
|
|
+ R_TR3,R_TR4,R_TR5,R_TR6,R_TR7,
|
|
|
+ R_MM0,R_MM1,R_MM2,R_MM3,R_MM4,R_MM5,R_MM6,R_MM7,
|
|
|
+ R_XMM0,R_XMM1,R_XMM2,R_XMM3,R_XMM4,R_XMM5,R_XMM6,R_XMM7
|
|
|
+ );
|
|
|
+
|
|
|
+ {# Set type definition for registers }
|
|
|
+ tregisterset = set of tregister;
|
|
|
+
|
|
|
+ {# Type definition for the array of string of register nnames }
|
|
|
+ reg2strtable = array[tregister] of string[6];
|
|
|
|
|
|
+ const
|
|
|
+ {# First register in the tregister enumeration }
|
|
|
+ firstreg = low(tregister);
|
|
|
+ {# Last register in the tregister enumeration }
|
|
|
+ lastreg = high(tregister);
|
|
|
+
|
|
|
+ firstsreg = R_CS;
|
|
|
+ lastsreg = R_GS;
|
|
|
+
|
|
|
+ regset8bit : tregisterset = [R_AL..R_DH];
|
|
|
+ regset16bit : tregisterset = [R_AX..R_DI,R_CS..R_SS];
|
|
|
+ regset32bit : tregisterset = [R_EAX..R_EDI];
|
|
|
+
|
|
|
+ { Convert reg to opsize }
|
|
|
+ reg2opsize : array[firstreg..lastreg] of topsize = (S_NO,
|
|
|
+ S_L,S_L,S_L,S_L,S_L,S_L,S_L,S_L,
|
|
|
+ S_W,S_W,S_W,S_W,S_W,S_W,S_W,S_W,
|
|
|
+ S_B,S_B,S_B,S_B,S_B,S_B,S_B,S_B,
|
|
|
+ S_W,S_W,S_W,S_W,S_W,S_W,
|
|
|
+ S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,S_FL,
|
|
|
+ S_L,S_L,S_L,S_L,S_L,S_L,
|
|
|
+ S_L,S_L,S_L,S_L,
|
|
|
+ S_L,S_L,S_L,S_L,S_L,
|
|
|
+ S_D,S_D,S_D,S_D,S_D,S_D,S_D,S_D,
|
|
|
+ S_D,S_D,S_D,S_D,S_D,S_D,S_D,S_D
|
|
|
+ );
|
|
|
+
|
|
|
+ {# Standard opcode string table (for each tasmop enumeration). The
|
|
|
+ opcode strings should conform to the names as defined by the
|
|
|
+ processor manufacturer.
|
|
|
+ }
|
|
|
+ std_op2str:op2strtable={$i i386int.inc}
|
|
|
+
|
|
|
+ {# Standard register table (for each tregister enumeration). The
|
|
|
+ register strings should conform to the the names as defined
|
|
|
+ by the processor manufacturer
|
|
|
+ }
|
|
|
+ std_reg2str : reg2strtable = ('',
|
|
|
+ 'eax','ecx','edx','ebx','esp','ebp','esi','edi',
|
|
|
+ 'ax','cx','dx','bx','sp','bp','si','di',
|
|
|
+ 'al','cl','dl','bl','ah','ch','bh','dh',
|
|
|
+ 'cs','ds','es','ss','fs','gs',
|
|
|
+ 'st','st(0)','st(1)','st(2)','st(3)','st(4)','st(5)','st(6)','st(7)',
|
|
|
+ 'dr0','dr1','dr2','dr3','dr6','dr7',
|
|
|
+ 'cr0','cr2','cr3','cr4',
|
|
|
+ 'tr3','tr4','tr5','tr6','tr7',
|
|
|
+ 'mm0','mm1','mm2','mm3','mm4','mm5','mm6','mm7',
|
|
|
+ 'xmm0','xmm1','xmm2','xmm3','xmm4','xmm5','xmm6','xmm7'
|
|
|
+ );
|
|
|
|
|
|
{*****************************************************************************
|
|
|
- Flags
|
|
|
+ Conditions
|
|
|
*****************************************************************************}
|
|
|
|
|
|
-type
|
|
|
- TResFlags = (F_E,F_NE,F_G,F_L,F_GE,F_LE,F_C,F_NC,F_A,F_AE,F_B,F_BE);
|
|
|
+ type
|
|
|
+ TAsmCond=(C_None,
|
|
|
+ C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
|
|
|
+ C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,
|
|
|
+ C_NS,C_NZ,C_O,C_P,C_PE,C_PO,C_S,C_Z
|
|
|
+ );
|
|
|
+
|
|
|
+ const
|
|
|
+ cond2str:array[TAsmCond] of string[3]=('',
|
|
|
+ 'a','ae','b','be','c','e','g','ge','l','le','na','nae',
|
|
|
+ 'nb','nbe','nc','ne','ng','nge','nl','nle','no','np',
|
|
|
+ 'ns','nz','o','p','pe','po','s','z'
|
|
|
+ );
|
|
|
+
|
|
|
+ inverse_cond:array[TAsmCond] of TAsmCond=(C_None,
|
|
|
+ C_NA,C_NAE,C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_A,C_AE,
|
|
|
+ C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_O,C_P,
|
|
|
+ C_S,C_Z,C_NO,C_NP,C_NP,C_P,C_NS,C_NZ
|
|
|
+ );
|
|
|
|
|
|
{*****************************************************************************
|
|
|
- Reference
|
|
|
+ Flags
|
|
|
*****************************************************************************}
|
|
|
|
|
|
-type
|
|
|
- trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
|
|
|
-
|
|
|
-type
|
|
|
- { immediate/reference record }
|
|
|
- poperreference = ^treference;
|
|
|
- treference = packed record
|
|
|
- segment,
|
|
|
- base,
|
|
|
- index : tregister;
|
|
|
- scalefactor : byte;
|
|
|
- offset : longint;
|
|
|
- symbol : tasmsymbol;
|
|
|
- offsetfixup : longint;
|
|
|
- options : trefoptions;
|
|
|
- end;
|
|
|
+ type
|
|
|
+ TResFlags = (F_E,F_NE,F_G,F_L,F_GE,F_LE,F_C,F_NC,F_A,F_AE,F_B,F_BE);
|
|
|
|
|
|
{*****************************************************************************
|
|
|
- Operands
|
|
|
+ Reference
|
|
|
*****************************************************************************}
|
|
|
|
|
|
- { Types of operand }
|
|
|
- toptype=(top_none,top_reg,top_ref,top_const,top_symbol);
|
|
|
-
|
|
|
- toper=record
|
|
|
- ot : longint;
|
|
|
- case typ : toptype of
|
|
|
- top_none : ();
|
|
|
- top_reg : (reg:tregister);
|
|
|
- top_ref : (ref:poperreference);
|
|
|
- top_const : (val:aword);
|
|
|
- top_symbol : (sym:tasmsymbol;symofs:longint);
|
|
|
- end;
|
|
|
-
|
|
|
-
|
|
|
+ type
|
|
|
+ trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
|
|
|
+
|
|
|
+ { reference record }
|
|
|
+ preference = ^treference;
|
|
|
+ treference = packed record
|
|
|
+ segment,
|
|
|
+ base,
|
|
|
+ index : tregister;
|
|
|
+ scalefactor : byte;
|
|
|
+ offset : longint;
|
|
|
+ symbol : tasmsymbol;
|
|
|
+ offsetfixup : longint;
|
|
|
+ options : trefoptions;
|
|
|
+ end;
|
|
|
|
|
|
{*****************************************************************************
|
|
|
- Argument Classification
|
|
|
+ Operands
|
|
|
*****************************************************************************}
|
|
|
|
|
|
+ { Types of operand }
|
|
|
+ toptype=(top_none,top_reg,top_ref,top_const,top_symbol);
|
|
|
+
|
|
|
+ toper=record
|
|
|
+ ot : longint;
|
|
|
+ case typ : toptype of
|
|
|
+ top_none : ();
|
|
|
+ top_reg : (reg:tregister);
|
|
|
+ top_ref : (ref:preference);
|
|
|
+ top_const : (val:aword);
|
|
|
+ top_symbol : (sym:tasmsymbol;symofs:longint);
|
|
|
+ end;
|
|
|
|
|
|
{*****************************************************************************
|
|
|
Generic Location
|
|
|
*****************************************************************************}
|
|
|
|
|
|
-type
|
|
|
- TLoc=(
|
|
|
- LOC_INVALID, { added for tracking problems}
|
|
|
- LOC_CONSTANT, { constant value }
|
|
|
- LOC_JUMP, { boolean results only, jump to false or true label }
|
|
|
- LOC_FLAGS, { boolean results only, flags are set }
|
|
|
- LOC_CREFERENCE, { in memory constant value reference (cannot change) }
|
|
|
- LOC_REFERENCE, { in memory value }
|
|
|
- LOC_REGISTER, { in a processor register }
|
|
|
- LOC_CREGISTER, { Constant register which shouldn't be modified }
|
|
|
- LOC_FPUREGISTER, { FPU stack }
|
|
|
- LOC_CFPUREGISTER, { if it is a FPU register variable on the fpu stack }
|
|
|
- LOC_MMXREGISTER, { MMX register }
|
|
|
- LOC_CMMXREGISTER, { MMX register variable }
|
|
|
- LOC_SSEREGISTER,
|
|
|
- LOC_CSSEREGISTER
|
|
|
- );
|
|
|
-
|
|
|
- plocation = ^tlocation;
|
|
|
- tlocation = packed record
|
|
|
- loc : TLoc;
|
|
|
- size : TCGSize;
|
|
|
- case TLoc of
|
|
|
- LOC_FLAGS : (resflags : tresflags);
|
|
|
- LOC_CONSTANT : (
|
|
|
- case longint of
|
|
|
- 1 : (value : AWord);
|
|
|
- 2 : (valuelow, valuehigh:AWord);
|
|
|
- );
|
|
|
- LOC_CREFERENCE,
|
|
|
- LOC_REFERENCE : (reference : treference);
|
|
|
- { segment in reference at the same place as in loc_register }
|
|
|
- LOC_REGISTER,LOC_CREGISTER : (
|
|
|
- case longint of
|
|
|
- 1 : (register,segment,registerhigh : tregister);
|
|
|
- { overlay a registerlow }
|
|
|
- 2 : (registerlow : tregister);
|
|
|
- );
|
|
|
- { it's only for better handling }
|
|
|
- LOC_MMXREGISTER,LOC_CMMXREGISTER : (mmxreg : tregister);
|
|
|
- end;
|
|
|
+ type
|
|
|
+ TLoc=(
|
|
|
+ LOC_INVALID, { added for tracking problems}
|
|
|
+ LOC_CONSTANT, { constant value }
|
|
|
+ LOC_JUMP, { boolean results only, jump to false or true label }
|
|
|
+ LOC_FLAGS, { boolean results only, flags are set }
|
|
|
+ LOC_CREFERENCE, { in memory constant value reference (cannot change) }
|
|
|
+ LOC_REFERENCE, { in memory value }
|
|
|
+ LOC_REGISTER, { in a processor register }
|
|
|
+ LOC_CREGISTER, { Constant register which shouldn't be modified }
|
|
|
+ LOC_FPUREGISTER, { FPU stack }
|
|
|
+ LOC_CFPUREGISTER, { if it is a FPU register variable on the fpu stack }
|
|
|
+ LOC_MMXREGISTER, { MMX register }
|
|
|
+ LOC_CMMXREGISTER, { MMX register variable }
|
|
|
+ LOC_SSEREGISTER,
|
|
|
+ LOC_CSSEREGISTER
|
|
|
+ );
|
|
|
+
|
|
|
+ tlocation = packed record
|
|
|
+ loc : TLoc;
|
|
|
+ size : TCGSize;
|
|
|
+ case TLoc of
|
|
|
+ LOC_FLAGS : (resflags : tresflags);
|
|
|
+ LOC_CONSTANT : (
|
|
|
+ case longint of
|
|
|
+ 1 : (value : AWord);
|
|
|
+ 2 : (valuelow, valuehigh:AWord);
|
|
|
+ );
|
|
|
+ LOC_CREFERENCE,
|
|
|
+ LOC_REFERENCE : (reference : treference);
|
|
|
+ { segment in reference at the same place as in loc_register }
|
|
|
+ LOC_REGISTER,LOC_CREGISTER : (
|
|
|
+ case longint of
|
|
|
+ 1 : (register,segment,registerhigh : tregister);
|
|
|
+ { overlay a registerlow }
|
|
|
+ 2 : (registerlow : tregister);
|
|
|
+ );
|
|
|
+ { it's only for better handling }
|
|
|
+ LOC_MMXREGISTER,LOC_CMMXREGISTER : (mmxreg : tregister);
|
|
|
+ end;
|
|
|
|
|
|
{*****************************************************************************
|
|
|
Constants
|
|
|
*****************************************************************************}
|
|
|
|
|
|
-const
|
|
|
- general_registers = [R_EAX,R_EBX,R_ECX,R_EDX];
|
|
|
-
|
|
|
- {# Table of registers which can be allocated by the code generator
|
|
|
- internally, when generating the code.
|
|
|
- }
|
|
|
- { legend: }
|
|
|
- { xxxregs = set of all possibly used registers of that type in the code }
|
|
|
- { generator }
|
|
|
- { usableregsxxx = set of all 32bit components of registers that can be }
|
|
|
- { possible allocated to a regvar or using getregisterxxx (this }
|
|
|
- { excludes registers which can be only used for parameter }
|
|
|
- { passing on ABI's that define this) }
|
|
|
- { c_countusableregsxxx = amount of registers in the usableregsxxx set }
|
|
|
-
|
|
|
- intregs = [R_EAX..R_BL];
|
|
|
- usableregsint = general_registers;
|
|
|
- c_countusableregsint = 4;
|
|
|
-
|
|
|
- fpuregs = [R_ST0..R_ST7];
|
|
|
- usableregsfpu = [];
|
|
|
- c_countusableregsfpu = 0;
|
|
|
-
|
|
|
- mmregs = [R_MM0..R_MM7];
|
|
|
- usableregsmm = [R_MM0..R_MM7];
|
|
|
- c_countusableregsmm = 8;
|
|
|
-
|
|
|
- firstsaveintreg = R_EAX;
|
|
|
- lastsaveintreg = R_EBX;
|
|
|
- firstsavefpureg = R_NO;
|
|
|
- lastsavefpureg = R_NO;
|
|
|
- firstsavemmreg = R_MM0;
|
|
|
- lastsavemmreg = R_MM7;
|
|
|
-
|
|
|
- {# Constant defining possibly all registers which might require saving }
|
|
|
- ALL_REGISTERS = [firstreg..lastreg];
|
|
|
-
|
|
|
- lvaluelocations = [LOC_REFERENCE,LOC_CFPUREGISTER,
|
|
|
- LOC_CREGISTER,LOC_MMXREGISTER,LOC_CMMXREGISTER];
|
|
|
+ const
|
|
|
+ max_operands = 3;
|
|
|
+
|
|
|
+ lvaluelocations = [LOC_REFERENCE,LOC_CFPUREGISTER,
|
|
|
+ LOC_CREGISTER,LOC_MMXREGISTER,LOC_CMMXREGISTER];
|
|
|
+
|
|
|
+ {# Constant defining possibly all registers which might require saving }
|
|
|
+ ALL_REGISTERS = [firstreg..lastreg];
|
|
|
+
|
|
|
+ general_registers = [R_EAX,R_EBX,R_ECX,R_EDX];
|
|
|
+
|
|
|
+ {# low and high of the available maximum width integer general purpose }
|
|
|
+ { registers }
|
|
|
+ LoGPReg = R_EAX;
|
|
|
+ HiGPReg = R_EDX;
|
|
|
+
|
|
|
+ {# low and high of every possible width general purpose register (same as }
|
|
|
+ { above on most architctures apart from the 80x86) }
|
|
|
+ LoReg = R_EAX;
|
|
|
+ HiReg = R_DH;
|
|
|
+
|
|
|
+ {# Table of registers which can be allocated by the code generator
|
|
|
+ internally, when generating the code.
|
|
|
+ }
|
|
|
+ { legend: }
|
|
|
+ { xxxregs = set of all possibly used registers of that type in the code }
|
|
|
+ { generator }
|
|
|
+ { usableregsxxx = set of all 32bit components of registers that can be }
|
|
|
+ { possible allocated to a regvar or using getregisterxxx (this }
|
|
|
+ { excludes registers which can be only used for parameter }
|
|
|
+ { passing on ABI's that define this) }
|
|
|
+ { c_countusableregsxxx = amount of registers in the usableregsxxx set }
|
|
|
+
|
|
|
+ maxintregs = 4;
|
|
|
+ intregs = [R_EAX..R_BL];
|
|
|
+ usableregsint = [R_EAX,R_EBX,R_ECX,R_EDX];
|
|
|
+ c_countusableregsint = 4;
|
|
|
+
|
|
|
+ maxfpuregs = 8;
|
|
|
+ fpuregs = [R_ST0..R_ST7];
|
|
|
+ usableregsfpu = [];
|
|
|
+ c_countusableregsfpu = 0;
|
|
|
+
|
|
|
+ mmregs = [R_MM0..R_MM7];
|
|
|
+ usableregsmm = [R_MM0..R_MM7];
|
|
|
+ c_countusableregsmm = 8;
|
|
|
+
|
|
|
+ firstsaveintreg = R_EAX;
|
|
|
+ lastsaveintreg = R_EBX;
|
|
|
+ firstsavefpureg = R_NO;
|
|
|
+ lastsavefpureg = R_NO;
|
|
|
+ firstsavemmreg = R_MM0;
|
|
|
+ lastsavemmreg = R_MM7;
|
|
|
+
|
|
|
+ maxvarregs = 4;
|
|
|
+ varregs : array[1..maxvarregs] of tregister =
|
|
|
+ (R_EBX,R_EDX,R_ECX,R_EAX);
|
|
|
+
|
|
|
+ maxfpuvarregs = 8;
|
|
|
+
|
|
|
+ {# Registers which are defined as scratch and no need to save across
|
|
|
+ routine calls or in assembler blocks.
|
|
|
+ }
|
|
|
+ max_scratch_regs = 1;
|
|
|
+ scratch_regs : array[1..max_scratch_regs] of tregister = (R_EDI);
|
|
|
|
|
|
{*****************************************************************************
|
|
|
Default generic sizes
|
|
|
*****************************************************************************}
|
|
|
- {# Defines the default address size for a processor, }
|
|
|
- OS_ADDR = OS_32;
|
|
|
- {# the natural int size for a processor, }
|
|
|
- OS_INT = OS_32;
|
|
|
- {# the maximum float size for a processor, }
|
|
|
- OS_FLOAT = OS_F80;
|
|
|
- {# the size of a vector register for a processor }
|
|
|
- OS_VECTOR = OS_M64;
|
|
|
+
|
|
|
+ {# Defines the default address size for a processor, }
|
|
|
+ OS_ADDR = OS_32;
|
|
|
+ {# the natural int size for a processor, }
|
|
|
+ OS_INT = OS_32;
|
|
|
+ {# the maximum float size for a processor, }
|
|
|
+ OS_FLOAT = OS_F80;
|
|
|
+ {# the size of a vector register for a processor }
|
|
|
+ OS_VECTOR = OS_M64;
|
|
|
|
|
|
{*****************************************************************************
|
|
|
Generic Register names
|
|
|
*****************************************************************************}
|
|
|
|
|
|
- {# Stack pointer register }
|
|
|
- stack_pointer_reg = R_ESP;
|
|
|
- {# Frame pointer register }
|
|
|
- frame_pointer_reg = R_EBP;
|
|
|
- {# Self pointer register : contains the instance address of an
|
|
|
- object or class. }
|
|
|
- self_pointer_reg = R_ESI;
|
|
|
- {# Register for addressing absolute data in a position independant way,
|
|
|
- such as in PIC code. The exact meaning is ABI specific }
|
|
|
- pic_offset_reg = R_EBX;
|
|
|
- {# Results are returned in this register (32-bit values) }
|
|
|
- accumulator = R_EAX;
|
|
|
- {# Hi-Results are returned in this register (64-bit value high register) }
|
|
|
- accumulatorhigh = R_EDX;
|
|
|
- { WARNING: don't change to R_ST0!! See comments above implementation of }
|
|
|
- { a_loadfpu* methods in rgcpu (JM) }
|
|
|
- fpuresultreg = R_ST;
|
|
|
- mmresultreg = R_MM0;
|
|
|
-
|
|
|
- {# Registers which are defined as scratch and no need to save across
|
|
|
- routine calls or in assembler blocks.
|
|
|
- }
|
|
|
- scratch_regs : array[1..1] of tregister = (R_EDI);
|
|
|
-
|
|
|
-
|
|
|
+ {# Stack pointer register }
|
|
|
+ stack_pointer_reg = R_ESP;
|
|
|
+ {# Frame pointer register }
|
|
|
+ frame_pointer_reg = R_EBP;
|
|
|
+ {# Self pointer register : contains the instance address of an
|
|
|
+ object or class. }
|
|
|
+ self_pointer_reg = R_ESI;
|
|
|
+ {# Register for addressing absolute data in a position independant way,
|
|
|
+ such as in PIC code. The exact meaning is ABI specific }
|
|
|
+ pic_offset_reg = R_EBX;
|
|
|
+ {# Results are returned in this register (32-bit values) }
|
|
|
+ accumulator = R_EAX;
|
|
|
+ {# Hi-Results are returned in this register (64-bit value high register) }
|
|
|
+ accumulatorhigh = R_EDX;
|
|
|
+ { WARNING: don't change to R_ST0!! See comments above implementation of }
|
|
|
+ { a_loadfpu* methods in rgcpu (JM) }
|
|
|
+ fpuresultreg = R_ST;
|
|
|
+ mmresultreg = R_MM0;
|
|
|
|
|
|
{*****************************************************************************
|
|
|
GCC /ABI linking information
|
|
|
*****************************************************************************}
|
|
|
|
|
|
- {# Registers which must be saved when calling a routine declared as
|
|
|
- cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
|
|
|
- saved should be the ones as defined in the target ABI and / or GCC.
|
|
|
-
|
|
|
- This value can be deduced from the CALLED_USED_REGISTERS array in the
|
|
|
- GCC source.
|
|
|
- }
|
|
|
- std_saved_registers = [R_ESI,R_EDI,R_EBX];
|
|
|
- {# Required parameter alignment when calling a routine declared as
|
|
|
- stdcall and cdecl. The alignment value should be the one defined
|
|
|
- by GCC or the target ABI.
|
|
|
-
|
|
|
- The value of this constant is equal to the constant
|
|
|
- PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
|
|
|
- }
|
|
|
- std_param_align = 4;
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
+ const
|
|
|
+ {# Registers which must be saved when calling a routine declared as
|
|
|
+ cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
|
|
|
+ saved should be the ones as defined in the target ABI and / or GCC.
|
|
|
+
|
|
|
+ This value can be deduced from the CALLED_USED_REGISTERS array in the
|
|
|
+ GCC source.
|
|
|
+ }
|
|
|
+ std_saved_registers = [R_ESI,R_EDI,R_EBX];
|
|
|
+ {# Required parameter alignment when calling a routine declared as
|
|
|
+ stdcall and cdecl. The alignment value should be the one defined
|
|
|
+ by GCC or the target ABI.
|
|
|
+
|
|
|
+ The value of this constant is equal to the constant
|
|
|
+ PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
|
|
|
+ }
|
|
|
+ std_param_align = 4;
|
|
|
|
|
|
+{*****************************************************************************
|
|
|
+ CPU Dependent Constants
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
{*****************************************************************************
|
|
|
Helpers
|
|
|
*****************************************************************************}
|
|
|
|
|
|
- const
|
|
|
- maxvarregs = 4;
|
|
|
- varregs : array[1..maxvarregs] of tregister =
|
|
|
- (R_EBX,R_EDX,R_ECX,R_EAX);
|
|
|
-
|
|
|
- maxfpuvarregs = 8;
|
|
|
- max_operands = 3;
|
|
|
-
|
|
|
- maxintregs = maxvarregs;
|
|
|
- maxfpuregs = maxfpuvarregs;
|
|
|
-
|
|
|
-
|
|
|
function is_calljmp(o:tasmop):boolean;
|
|
|
|
|
|
function flags_to_cond(const f: TResFlags) : TAsmCond;
|
|
|
@@ -593,17 +399,10 @@ const
|
|
|
|
|
|
implementation
|
|
|
|
|
|
-{$ifdef heaptrc}
|
|
|
- uses
|
|
|
- ppheap;
|
|
|
-{$endif heaptrc}
|
|
|
-
|
|
|
-
|
|
|
{*****************************************************************************
|
|
|
Helpers
|
|
|
*****************************************************************************}
|
|
|
|
|
|
-
|
|
|
function is_calljmp(o:tasmop):boolean;
|
|
|
begin
|
|
|
case o of
|
|
|
@@ -624,9 +423,6 @@ implementation
|
|
|
end;
|
|
|
|
|
|
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
function flags_to_cond(const f: TResFlags) : TAsmCond;
|
|
|
const
|
|
|
flags_2_cond : array[TResFlags] of TAsmCond =
|
|
|
@@ -635,11 +431,16 @@ implementation
|
|
|
result := flags_2_cond[f];
|
|
|
end;
|
|
|
|
|
|
-
|
|
|
end.
|
|
|
{
|
|
|
$Log$
|
|
|
- Revision 1.19 2002-05-12 16:53:16 peter
|
|
|
+ Revision 1.20 2002-05-14 17:28:09 peter
|
|
|
+ * synchronized cpubase between powerpc and i386
|
|
|
+ * moved more tables from cpubase to cpuasm
|
|
|
+ * tai_align_abstract moved to tainst, cpuasm must define
|
|
|
+ the tai_align class now, which may be empty
|
|
|
+
|
|
|
+ Revision 1.19 2002/05/12 16:53:16 peter
|
|
|
* moved entry and exitcode to ncgutil and cgobj
|
|
|
* foreach gets extra argument for passing local data to the
|
|
|
iterator function
|
peter