Add some support for shifterop parameters in intrinsics.

git-svn-id: branches/laksen/intrinsics@32154 -

compiler/arm/armfirst.inc

@@ -121,13 +121,13 @@ in_arm_umaal
     result:=nil;
   end;
 in_arm_pkhbt_shift
-: //out rd:r32;rn:r32;rm:r32;ls:i32;
+: //out rd:r32;rn:r32;rm:r32;ls:lsl5;
   begin
     expectloc:=LOC_REGISTER;
     result:=nil;
   end;
 in_arm_pkhtb_shift
-: //out rd:r32;rn:r32;rm:r32;rs:i32;
+: //out rd:r32;rn:r32;rm:r32;rs:asr5;
   begin
     expectloc:=LOC_REGISTER;
     result:=nil;
@@ -190,7 +190,7 @@ in_arm_sxtab_ror
 ,in_arm_uxtab_ror
 ,in_arm_uxtab16_ror
 ,in_arm_uxtah_ror
-: //out rd:r32;rm:r32;rn:r32;ror:i32;
+: //out rd:r32;rm:r32;rn:r32;ror:ror3;
   begin
     expectloc:=LOC_REGISTER;
     result:=nil;
@@ -217,7 +217,7 @@ in_arm_sxtb_ror
 ,in_arm_uxtb_ror
 ,in_arm_uxtb16_ror
 ,in_arm_uxth_ror
-: //out rd:r32;rm:r32;ror:i32;
+: //out rd:r32;rm:r32;ror:ror3;
   begin
     expectloc:=LOC_REGISTER;
     result:=nil;

compiler/arm/armintr.dat

@@ -65,8 +65,8 @@ umaal(out [rl,rh]: r64; rl, rh, rn,rm: r32)
 
 pkhbt(out rd: r32; rn,rm: r32)
 pkhtb(out rd: r32; rn,rm: r32)
-pkhbt[shift](out rd: r32; rn,rm: r32; ls: i32)                     (ls in [0..31])
-pkhtb[shift](out rd: r32; rn,rm: r32; rs: i32)                     (ls in [0..31])
+pkhbt[shift](out rd: r32; rn,rm: r32; ls: lsl5)                    (ls in [0..31])
+pkhtb[shift](out rd: r32; rn,rm: r32; rs: asr5)                    (ls in [0..31])
 
 qadd(out rd: r32; rm,rn: r32)
 qadd16(out rd: r32; rm,rn: r32)
@@ -117,12 +117,12 @@ uxtab(out rd: r32; rm,rn: r32)
 uxtab16(out rd: r32; rm,rn: r32)
 uxtah(out rd: r32; rm,rn: r32)
 
-sxtab[ror](out rd: r32; rm,rn: r32; ror: i32)                    (ls in [0,8,16,24])
-sxtab16[ror](out rd: r32; rm,rn: r32; ror: i32)                  (ls in [0,8,16,24])
-sxtah[ror](out rd: r32; rm,rn: r32; ror: i32)                    (ls in [0,8,16,24])
-uxtab[ror](out rd: r32; rm,rn: r32; ror: i32)                    (ls in [0,8,16,24])
-uxtab16[ror](out rd: r32; rm,rn: r32; ror: i32)                  (ls in [0,8,16,24])
-uxtah[ror](out rd: r32; rm,rn: r32; ror: i32)                    (ls in [0,8,16,24])
+sxtab[ror](out rd: r32; rm,rn: r32; ror: ror3)                   (ls in [0,8,16,24])
+sxtab16[ror](out rd: r32; rm,rn: r32; ror: ror3)                 (ls in [0,8,16,24])
+sxtah[ror](out rd: r32; rm,rn: r32; ror: ror3)                   (ls in [0,8,16,24])
+uxtab[ror](out rd: r32; rm,rn: r32; ror: ror3)                   (ls in [0,8,16,24])
+uxtab16[ror](out rd: r32; rm,rn: r32; ror: ror3)                 (ls in [0,8,16,24])
+uxtah[ror](out rd: r32; rm,rn: r32; ror: ror3)                   (ls in [0,8,16,24])
 
 sxtb(out rd: r32; rm: r32)
 sxtb16(out rd: r32; rm: r32)
@@ -131,12 +131,12 @@ uxtb(out rd: r32; rm: r32)
 uxtb16(out rd: r32; rm: r32)
 uxth(out rd: r32; rm: r32)
 
-sxtb[ror](out rd: r32; rm: r32; ror: i32)                        (ls in [0,8,16,24])
-sxtb16[ror](out rd: r32; rm: r32; ror: i32)                      (ls in [0,8,16,24])
-sxth[ror](out rd: r32; rm: r32; ror: i32)                        (ls in [0,8,16,24])
-uxtb[ror](out rd: r32; rm: r32; ror: i32)                        (ls in [0,8,16,24])
-uxtb16[ror](out rd: r32; rm: r32; ror: i32)                      (ls in [0,8,16,24])
-uxth[ror](out rd: r32; rm: r32; ror: i32)                        (ls in [0,8,16,24])
+sxtb[ror](out rd: r32; rm: r32; ror: ror3)                       (ls in [0,8,16,24])
+sxtb16[ror](out rd: r32; rm: r32; ror: ror3)                     (ls in [0,8,16,24])
+sxth[ror](out rd: r32; rm: r32; ror: ror3)                       (ls in [0,8,16,24])
+uxtb[ror](out rd: r32; rm: r32; ror: ror3)                       (ls in [0,8,16,24])
+uxtb16[ror](out rd: r32; rm: r32; ror: ror3)                     (ls in [0,8,16,24])
+uxth[ror](out rd: r32; rm: r32; ror: ror3)                       (ls in [0,8,16,24])
 
 clz(out rd: r32; rm: r32)
 rbit(out rd: r32; rm: r32)
@@ -151,4 +151,4 @@ ssat(out rd: r32; sat: i32; rn: r32)                        (sat in [1..32])
 usat(out rd: r32; sat: i32; rn: r32)                        (sat in [1..32])
 
 ssat16(out rd: r32; sat: i32; rn: r32)                      (sat in [1..32])
-usat16(out rd: r32; sat: i32; rn: r32)                      (sat in [1..32])          
+usat16(out rd: r32; sat: i32; rn: r32)                      (sat in [1..32])

compiler/arm/armsecond.inc

@@ -290,7 +290,7 @@ in_arm_umaal
     current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_reg(op,paraarray[1].location.register,paraarray[2].location.register,paraarray[3].location.register,paraarray[4].location.register),pf));
   end;
 in_arm_pkhbt_shift
-: //out rd:r32;rn:r32;rm:r32;ls:i32;
+: //out rd:r32;rn:r32;rm:r32;ls:lsl5;
   begin
     case inlinenumber of
       in_arm_pkhbt_shift: begin op:=A_pkhbt; pf:=PF_None; end;
@@ -304,10 +304,10 @@ in_arm_pkhbt_shift
     hlcg.location_force_reg(current_asmdata.CurrAsmList, paraarray[2].location, paraarray[2].resultdef,u32inttype,true);
     location_reset(location,LOC_REGISTER,OS_32);
     location.register:=cg.getintregister(current_asmdata.CurrAsmList, OS_32);
-    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_const(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetConstInt(paraarray[3])),pf));
+    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_shifterop(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetShifterOp(sm_lsl,paraarray[3])),pf));
   end;
 in_arm_pkhtb_shift
-: //out rd:r32;rn:r32;rm:r32;rs:i32;
+: //out rd:r32;rn:r32;rm:r32;rs:asr5;
   begin
     case inlinenumber of
       in_arm_pkhtb_shift: begin op:=A_pkhtb; pf:=PF_None; end;
@@ -321,7 +321,7 @@ in_arm_pkhtb_shift
     hlcg.location_force_reg(current_asmdata.CurrAsmList, paraarray[2].location, paraarray[2].resultdef,u32inttype,true);
     location_reset(location,LOC_REGISTER,OS_32);
     location.register:=cg.getintregister(current_asmdata.CurrAsmList, OS_32);
-    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_const(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetConstInt(paraarray[3])),pf));
+    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_shifterop(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetShifterOp(sm_asr,paraarray[3])),pf));
   end;
 in_arm_qadd
 ,in_arm_qadd16
@@ -438,7 +438,7 @@ in_arm_sxtab_ror
 ,in_arm_uxtab_ror
 ,in_arm_uxtab16_ror
 ,in_arm_uxtah_ror
-: //out rd:r32;rm:r32;rn:r32;ror:i32;
+: //out rd:r32;rm:r32;rn:r32;ror:ror3;
   begin
     case inlinenumber of
       in_arm_uxtah_ror: begin op:=A_uxtah; pf:=PF_None; end;
@@ -457,7 +457,7 @@ in_arm_sxtab_ror
     hlcg.location_force_reg(current_asmdata.CurrAsmList, paraarray[2].location, paraarray[2].resultdef,u32inttype,true);
     location_reset(location,LOC_REGISTER,OS_32);
     location.register:=cg.getintregister(current_asmdata.CurrAsmList, OS_32);
-    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_const(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetConstInt(paraarray[3])),pf));
+    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg_shifterop(op,location.register,paraarray[1].location.register,paraarray[2].location.register,GetShifterOp(sm_ror,paraarray[3])),pf));
   end;
 in_arm_sxtb
 ,in_arm_sxtb16
@@ -501,7 +501,7 @@ in_arm_sxtb_ror
 ,in_arm_uxtb_ror
 ,in_arm_uxtb16_ror
 ,in_arm_uxth_ror
-: //out rd:r32;rm:r32;ror:i32;
+: //out rd:r32;rm:r32;ror:ror3;
   begin
     case inlinenumber of
       in_arm_uxth_ror: begin op:=A_uxth; pf:=PF_None; end;
@@ -519,7 +519,7 @@ in_arm_sxtb_ror
     hlcg.location_force_reg(current_asmdata.CurrAsmList, paraarray[1].location, paraarray[1].resultdef,u32inttype,true);
     location_reset(location,LOC_REGISTER,OS_32);
     location.register:=cg.getintregister(current_asmdata.CurrAsmList, OS_32);
-    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_const(op,location.register,paraarray[1].location.register,GetConstInt(paraarray[2])),pf));
+    current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_shifterop(op,location.register,paraarray[1].location.register,GetShifterOp(sm_ror,paraarray[2])),pf));
   end;
 in_arm_sbfx
 ,in_arm_ubfx

compiler/arm/armtype.inc

@@ -121,13 +121,13 @@ in_arm_umaal
     resultdef:=u64inttype;
   end;
 in_arm_pkhbt_shift
-: //out rd:r32;rn:r32;rm:r32;ls:i32;
+: //out rd:r32;rn:r32;rm:r32;ls:lsl5;
   begin
     CheckParameters(3);
     resultdef:=u32inttype;
   end;
 in_arm_pkhtb_shift
-: //out rd:r32;rn:r32;rm:r32;rs:i32;
+: //out rd:r32;rn:r32;rm:r32;rs:asr5;
   begin
     CheckParameters(3);
     resultdef:=u32inttype;
@@ -190,7 +190,7 @@ in_arm_sxtab_ror
 ,in_arm_uxtab_ror
 ,in_arm_uxtab16_ror
 ,in_arm_uxtah_ror
-: //out rd:r32;rm:r32;rn:r32;ror:i32;
+: //out rd:r32;rm:r32;rn:r32;ror:ror3;
   begin
     CheckParameters(3);
     resultdef:=u32inttype;
@@ -217,7 +217,7 @@ in_arm_sxtb_ror
 ,in_arm_uxtb_ror
 ,in_arm_uxtb16_ror
 ,in_arm_uxth_ror
-: //out rd:r32;rm:r32;ror:i32;
+: //out rd:r32;rm:r32;ror:ror3;
   begin
     CheckParameters(2);
     resultdef:=u32inttype;

compiler/arm/narminl.pas

@@ -432,6 +432,13 @@ implementation
             Message(type_e_constant_expr_expected);
         end;
 
+      function GetShifterOp(AShiftMode: tshiftmode; AAmount: tnode): tshifterop;
+        begin
+          result.shiftmode:=AShiftMode;
+          result.rs:=NR_NO;
+          Result.shiftimm:=GetConstInt(AAmount);
+        end;
+
       procedure GetParameters(count: longint);
         var
           i: longint;

compiler/utils/mkarminl.pp

@@ -28,6 +28,9 @@ function GetPascalType(const ATyp: string): string;
       'r64':   exit('qword');
       'rs64':  exit('int64');
       'i32':   exit('longint');
+      'ror3':  exit('longint');
+      'lsl5':  exit('longint');
+      'asr5':  exit('longint');
       'ptr32': exit('pointer');
     else
       exit(ATyp);
@@ -56,6 +59,9 @@ function GetOper(const ATyp: string): string;
       'r64':   exit('_reg_reg');
       'rs64':  exit('_reg_reg');
       'i32':   exit('_const');
+      'ror3':  exit('_shifterop');
+      'asr5':  exit('_shifterop');
+      'lsl5':  exit('_shifterop');
       'ptr32': exit('_ref');
     else
       exit('');
@@ -71,6 +77,9 @@ function GetOperand(const ATyp: string; AIndex: longint): string;
       'rs64':  exit(format(',paraarray[%d].location.register64.reglo,paraarray[%d].location.register64.reghi', [AIndex,AIndex]));
       'i32':   exit(format(',GetConstInt(paraarray[%d])',[AIndex]));
       'ptr32': exit(format(',paraarray[%d].location.reference', [AIndex]));
+      'ror3':  exit(format(',GetShifterOp(sm_ror,paraarray[%d])',[AIndex]));
+      'lsl5':  exit(format(',GetShifterOp(sm_lsl,paraarray[%d])',[AIndex]));
+      'asr5':  exit(format(',GetShifterOp(sm_asr,paraarray[%d])',[AIndex]));
     else
       exit(ATyp);
     end;