pascal/freepascal.compiler

mirror of https://gitlab.com/freepascal.org/fpc/source.git

Author	SHA1 Message	Date
florian	f71871e60d * generating a linear sub list makes no sense for RiscV	1 month ago
florian	ccae78f97a + RiscV64: apply OptPass1OP also to addiw	11 months ago
Jonas Maebe	07bd4ba517 * let all the case code generation work with tconstexprint instead of aint,	6 years ago
Jeppe Johansen	054bf32f1f Add RV64GC cpu type.	7 years ago
Jeppe Johansen	ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.	7 years ago