 florian
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2cfb790eb7
* apply OptPass1FOP to FCVT.*.*
|
10 months ago |
|
florian
|
c83a047dda
* extend use of OptPass1FOP
|
10 months ago |
|
florian
|
28e1daa8e1
* apply OptPass1FOP to more opcodes
|
10 months ago |
|
florian
|
fe4f121721
* generalize FOpFsgnj02FOp optimization
|
10 months ago |
|
florian
|
477b9ad556
+ RiscV: FOp.sFsgnj.s02FOp.s optimization
|
10 months ago |
|
florian
|
683b566cb7
* improve RiscV assembler optimizer
|
10 months ago |
|
florian
|
42f15792ec
+ first batch of instructions added for Addi0Op2Op
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10 months ago |
|
florian
|
584e49c6a2
* Addi0Op2Op has to consider both operands
|
10 months ago |
|
florian
|
e9fa0510d0
* RiscV: extend Addi0Op2Op
|
10 months ago |
|
florian
|
b667be825e
+ RiscV: Addi0Op2Op optimization
|
10 months ago |
|
florian
|
f356d8cc51
* fix RiscV32 compilation
|
11 months ago |
|
florian
|
2123c59941
+ RiscV: AndiAddwi02Andi optimization
|
11 months ago |
|
florian
|
7c023d33d0
* RiscV: fix AndiAndi2Andi optimization
|
11 months ago |
|
florian
|
6ef37d999a
+ Risc-V: instructions of B extension
|
1 year ago |
|
florian
|
f1a173bdf6
* improve Risv-V optimizer
|
1 year ago |
|
florian
|
23dec631f5
+ Risc-V: apply OptPass1OP to more operations
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1 year ago |
|
florian
|
cc2406ad74
* factor out TRVCpuAsmOptimizer.OptPass1Add
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1 year ago |
|
florian
|
8708144c50
+ RiscV: AndiAndi2Andi
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1 year ago |
|
florian
|
80febbd8cf
* Risc-V: use OptPass1OP more
|
1 year ago |
|
florian
|
a4242e60b2
+ Risc-V 32: apply OptPass1OP also on ADD
|
1 year ago |
|
florian
|
657e4bf838
* more use of OptPass1OP
|
1 year ago |
|
florian
|
9c81c4a5fa
* apply OptPass1OP to more instructions
|
1 year ago |
|
florian
|
1c96bf5d30
+ S*LI x,x,0 to nop optimization
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1 year ago |
|
florian
|
c81f10bfbd
+ apply OptPass1OP also to SRL/SLL
|
1 year ago |
|
florian
|
39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
|
1 year ago |
 pierre
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c2c7982a22
Fix check that third parameter of ADDI hp1 instruction is a constant
|
4 years ago |
|
florian
|
9e2bcd940a
+ RiscV: initial OpAddi02Op implementation
|
4 years ago |
 Jeppe Johansen
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02c3f328a2
- RISC-V: Share optimizations between 32 and 64-bit.
|
5 years ago |
