 florian
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6ef37d999a
+ Risc-V: instructions of B extension
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1 year ago |
|
florian
|
f1a173bdf6
* improve Risv-V optimizer
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1 year ago |
|
florian
|
23dec631f5
+ Risc-V: apply OptPass1OP to more operations
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1 year ago |
|
florian
|
cc2406ad74
* factor out TRVCpuAsmOptimizer.OptPass1Add
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1 year ago |
|
florian
|
8708144c50
+ RiscV: AndiAndi2Andi
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1 year ago |
|
florian
|
80febbd8cf
* Risc-V: use OptPass1OP more
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1 year ago |
|
florian
|
a4242e60b2
+ Risc-V 32: apply OptPass1OP also on ADD
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1 year ago |
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florian
|
657e4bf838
* more use of OptPass1OP
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1 year ago |
|
florian
|
9c81c4a5fa
* apply OptPass1OP to more instructions
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1 year ago |
|
florian
|
1c96bf5d30
+ S*LI x,x,0 to nop optimization
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1 year ago |
|
florian
|
c81f10bfbd
+ apply OptPass1OP also to SRL/SLL
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1 year ago |
|
florian
|
39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
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1 year ago |
 pierre
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c2c7982a22
Fix check that third parameter of ADDI hp1 instruction is a constant
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4 years ago |
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florian
|
9e2bcd940a
+ RiscV: initial OpAddi02Op implementation
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4 years ago |
 Jeppe Johansen
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02c3f328a2
- RISC-V: Share optimizations between 32 and 64-bit.
|
5 years ago |
