 florian
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6d157b5bf0
+ Risc-V 32: optimize QWord(1) shl ...
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1 year ago |
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florian
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1737035501
+ riscv32: trv32shlshrnode.second_64bit
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1 year ago |
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florian
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7f8f733963
* RiscV32 correctly set operands of div/mod operations, resolves #37743
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4 years ago |
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florian
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28f25b2df0
* reworked usage of tcgnotnode.handle_locjump
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5 years ago |
 pierre
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7405ae2758
Fix trv32notnode, by using same code as for riscv64 CPU
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5 years ago |
 Jeppe Johansen
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a1a17447ff
- Fix bug in 64bit softfloat double negation.
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6 years ago |
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Jeppe Johansen
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
