Tree:
8a8aba47c5
39999-documentation-for-sizeint-is-incomplete
GetRidOfSysutilsInMath
asm-const-allow-comments
basemath
cherry-pick-27ab140d-2
cherry-pick-a8cd770b
ci_from_joost_testconversion2
extended_process
extended_rtti_cleaned
fixes_3_2
floatx80funcs
fpmask
httpserver_keepalive
joost/classattributes
joost/dwarfproperties
laksen/armiw
laksen/avr32new
laksen/gcra
laksen/intrinsics
laksen/spc32
libc_csu_weakexternal
maciej/generics_collections
maciej/smart_pointers
main
merged/avr_2
merged/cleanroom
merged/fpc_2_3
merged/pasboolxx
merged/usersections
monitor_support
mos6502
olivier/uefi
parameter_check_po_global
pas2js/fixes_2_2
pas2js/fixes_3_0
pas2js/fixes_3_2
paul/extended_records
paul/features
paul/generics
paul/namespaces
pierre-error-on-class-to-classrefdef-typecast
pierre/class-vs-classref-typecasts
pierre/fix-composite-parasyms
release_3_2_4-branch
rtti-thunk-no-global-label
svenbarth/arc
svenbarth/classhelpers
svenbarth/collector
svenbarth/generics
svenbarth/misc
svenbarth/nativent
svenbarth/packages
svenbarth/symobi
svn/blocks
svn/cpstrrtl
svn/debug_eh
svn/fixes_2_0
svn/fixes_2_2
svn/fixes_2_2_0_dos
svn/fixes_2_4
svn/fixes_2_6
svn/fixes_2_6_0
svn/fixes_3_0
svn/fixes_3_0_ios
svn/fixes_3_2
svn/hlcgllvm
svn/interfacertti
svn/js
svn/jvmbackend
svn/llvm
svn/mips_embedded
svn/nestedprocvars
svn/objc
svn/rc_2_2_2
svn/release_2_1_2x
svn/release_2_2_4_rc1
svn/resources
svn/sergei
svn/target-subdir
svn/targetandroid
svn/tue
svn/unicode
svn/unicodekvm
svn/unicodertl
svn/unicodestring
svn/unitrw
svn/wpo
svn/xpcom
target-subdir
tg74/avx1
tg74/avx2
tg74/avx512
tg74/avx512-0037785
tg74/avx512merge
tg74/fixes_3_2
try_less_recompilations
unicodekvm
unicodertl
val_range_check
val_sint
wasm_reference_types
x32
release_3_2_4_rc1
pas2js/release_2_2_0
3.2.3
3.3.1
git_start
release_3_2_2
release_3_2_2_rc1
release_3_2_0
release_3_2_0_rc1
release_3_0_4a_macos_10_14
release_3_0_4
release_3_0_4_rc1
release_3_0_2
release_3_0_2_rc1
release_3_0_0
release_3_0_0_rc2
release_3_0_0_rc1
release_2_6_4
release_2_6_4_rc1
release_2_6_2
release_2_6_2_rc1
release_2_6_0
release_2_6_0_rc1
release_2_4_4
release_2_4_4_rc1
release_2_4_2_rc1
release_2_4_2
release_2_4_0_rc1
release_2_4_0
release_2_2_4
release_2_2_2
release_2_2_2_rc2
release_2_2_2_rc1
release_2_0_2
release_2_2_0
release_2_1_4
release_2_1_2
release_2_0_4_macos
release_2_0_4
release_2_0_4_rc3
release_2_0_4_rc2
release_2_0_4_rc1
release_2_0_0
RELEASE.2.0.0
RELEASE.1.9.8
RELEASE.1.9.6
Makefile
RELEASE.1.9.4
FIXES.1.0.0
DWARFSTART
RELEASE.1.9.2
RELEASE.1.9.0
RELEASE.1.0.10
RELEASE.1.0.8
RELEASE.1.0.8.PRE3
NEWRA.MERGED
RELEASE.1.0.6.PRE1
CVS
FIXES1.0.0
RELEASE.1.0.4
fcl
help
MERGE.109
RELEASE.1.0.0
RELEASE.100
INITIAL
latest.sent.to.gabor
release-0.99.14
merged-0.99.12
release-0.99.12
release-0.99.10
merged-0.99.8
release-0.99.8
VER0.99.8
release-0-99-5
RESTORED.VERSION
Commit History
| Author | SHA1 Message | Date |
|---|---|---|
 Interferon
|
b293825a1a There is code in the register allocator to restrict register allocation to the | 2 years ago |
|
Interferon
|
b0adc3cf0c Added generic WCH32Vx RISC-V processor types using memory size suffixes | 2 years ago |
 Jeppe Johansen
|
2678522db5 - RISC-V: Add controller types for common RV32 MCUs. | 5 years ago |