 florian
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963fe73d19
+ support all XSAVE instructions, resolves #37864
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4 anni fa |
 tg74
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1454e8b29d
new avx512-opcodes VBMI2,VNNI,BITALG ...
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5 anni fa |
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florian
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746bfced25
Synchronized with trunk, part 1 (only make cycle tested, make all is broken, avx-512 support not yet tested
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6 anni fa |
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florian
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4f0da5fcc3
+ patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799
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6 anni fa |
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florian
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8943c0584e
+ patch by J. Gareth Moreton to support BMI2 instructions
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6 anni fa |
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tg74
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dd967ecfee
remove any gather/scatter opcodes for nights mill
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7 anni fa |
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tg74
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c611e4814a
new avx512 opcodes
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7 anni fa |
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tg74
|
1d9cbb4dcb
new AVX512 opcodes
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7 anni fa |
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tg74
|
914e31dbd1
new AVX512 instructions vextracti..,vextractf..
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7 anni fa |
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tg74
|
2b1da37d66
new avx512 instructions and bugfixes avx512
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7 anni fa |
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tg74
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867d145e50
support vector operand bcst,{sae},{er} + k-register
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7 anni fa |
 marco
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f0042a4719
* vcmppd hardcoded primitives like vcmpeqpd.
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7 anni fa |
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marco
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f21a141144
* mantis #32001, add 32 vcmpps variants.
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7 anni fa |
 nickysn
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ae92973196
+ added support for the retw, retnw, retfw, retd, retnd, retfd, retq, retnq and
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7 anni fa |
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nickysn
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0fb79946a5
+ added support for the parameterized versions of the x86 string instructions
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7 anni fa |
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florian
|
48fbd569fd
* support for the CDQE instruction, by Emelyanov Roman, resolves #30978
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8 anni fa |
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florian
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56252d59f0
+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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8 anni fa |
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florian
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406e3c4ac1
+ support xgetbv instruction, resolves issue #29958
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9 anni fa |
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florian
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8d5cc3dfa4
* (extended and modified) patch by Emelyanov Roman to add suport of RDRAND, RDSEED and TSX instructions set, resolves issue #29893.
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9 anni fa |
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florian
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a3964d9ee0
+ support for RDTSCP, resolves issue #28916
|
9 anni fa |
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florian
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d6e4af8279
+ applied remaining patches of Torsten Grundke: adds gather instructions of avx2
|
10 anni fa |
 sergei
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 anni fa |
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florian
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842e027a9f
+ prove of concept how FMA4 could be supported in inline assembler
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11 anni fa |
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florian
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a79be2b05c
+ support for FMA instructions in inline assembler
|
11 anni fa |
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florian
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aa107b914c
* merged avx2 branch, developed by Torsten Grundke
|
11 anni fa |
|
florian
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7028210817
+ tzcnt assembler instruction
|
11 anni fa |
|
nickysn
|
f6e846c574
+ added the NEC V20/V30 instructions
|
12 anni fa |
|
florian
|
9b6094a58c
+ added a few BMI instructions to see if they can be encoded
|
12 anni fa |
|
florian
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283ff05127
* merged avx support in inline assembler developed by Torsten Grundke
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13 anni fa |
|
florian
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c011949765
+ iretq for x86_64
|
14 anni fa |
