 Sven/Sarah Barth
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30a1cde7a5
* fix #40421: implement assembly variants of the SwapEndian functions for Aarch64
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2 years ago |
 Jonas Maebe
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0758aa1143
FPU exception mask: generlised system unit interface
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3 years ago |
 Benito van der Zander
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7704fe9319
fix stack trace crash, see #39492
|
3 years ago |
 florian
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38706a1713
* fix declocked(longint) for aarch64 without LSE, resolves #39569
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3 years ago |
|
florian
|
4de8ca8393
* fpcr and fpsr are 64 bit on aarch64
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4 years ago |
|
florian
|
d53b17cadc
+ Aarch64: completed LSE support for all interlocked operations
|
4 years ago |
|
florian
|
e6f01065ec
+ Aarch64: use LSE if available for atomic intrinsics
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4 years ago |
|
Jonas Maebe
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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5 years ago |
|
Jonas Maebe
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d9f4c85d2e
* llvm sometimes uses the AArch64 framepointer register as a regvar in the
|
5 years ago |
|
florian
|
688c7d439f
o AArch64:
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6 years ago |
|
florian
|
078595be4c
+ support for software floating point exception handling on AArch64 (-CE)
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6 years ago |
|
Jonas Maebe
|
41fba0c4f7
* switched to using the stack pointer as base register for the temp allocator
|
10 years ago |
|
Jonas Maebe
|
dad442c7e3
+ aarch64 fpu init, atomic routines and memory barriers
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10 years ago |
