Author | SHA1 Message | Date |
---|---|---|
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f1fb880f18 * fixed debug register values for vector registers | 10 years ago |
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9c55fa6f6c + FPCR, FPSR and TPIDR registers | 10 years ago |
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f1b619a942 * made (X|W)ZR and (W)SP separate registers, because a number of | 10 years ago |
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ca75588989 + first cpubase implementation for aarch64 | 12 years ago |
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5af1d48158 + register definitions for AArch64 aka ARM64 | 12 years ago |