Autor | SHA1 Mensagem | Data |
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6f3582954c Use same features for riscv32 as for arm and xtensa CPUs | há 2 anos atrás |
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546a679f4e Add -SfPROCESSES for arm cpu, to be able to compile fcl-base package as for xtensa | há 5 anos atrás |
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702e63e59f * build more units for FreeRTOS | há 5 anos atrás |
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391512546e + initial FreeRTOS RTL support, largely based on the Embedded target, limited to Xtensa so far | há 5 anos atrás |