 florian
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90afbc8114
* RiscV: unified cpu initialization and FPU exception handling, resolves #38893
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4 years ago |
 Jeppe Johansen
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e53cb61b11
Add support for softfloat in RISCV RTL.
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6 years ago |
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florian
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4f052e4f90
o fix several issues with floating point exceptions
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7 years ago |
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florian
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203409ab48
* fixed floating point exception masking support for RiscV64
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7 years ago |
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Jeppe Johansen
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f781c8942e
Write real atomic operations, and add memory barrier operations.
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7 years ago |
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Jeppe Johansen
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b98eb3daa9
Changed order in stack unravelling RTL code, to match the most common cases.
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7 years ago |
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Jeppe Johansen
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
