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nx86inl.pas 37 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. Generate x86 inline nodes
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit nx86inl;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. node,ninl,ncginl;
  22. type
  23. tx86inlinenode = class(tcginlinenode)
  24. { first pass override
  25. so that the code generator will actually generate
  26. these nodes.
  27. }
  28. function first_pi: tnode ; override;
  29. function first_arctan_real: tnode; override;
  30. function first_abs_real: tnode; override;
  31. function first_sqr_real: tnode; override;
  32. function first_sqrt_real: tnode; override;
  33. function first_ln_real: tnode; override;
  34. function first_cos_real: tnode; override;
  35. function first_sin_real: tnode; override;
  36. function first_round_real: tnode; override;
  37. function first_trunc_real: tnode; override;
  38. function first_popcnt: tnode; override;
  39. function first_fma: tnode; override;
  40. function first_sse: tnode; override;
  41. { second pass override to generate these nodes }
  42. procedure second_IncludeExclude;override;
  43. procedure second_pi; override;
  44. procedure second_arctan_real; override;
  45. procedure second_abs_real; override;
  46. procedure second_round_real; override;
  47. procedure second_sqr_real; override;
  48. procedure second_sqrt_real; override;
  49. procedure second_ln_real; override;
  50. procedure second_cos_real; override;
  51. procedure second_sin_real; override;
  52. procedure second_trunc_real; override;
  53. procedure second_prefetch;override;
  54. {$ifndef i8086}
  55. procedure second_abs_long;override;
  56. {$endif not i8086}
  57. procedure second_popcnt;override;
  58. procedure second_fma;override;
  59. procedure second_sse;override;
  60. private
  61. procedure load_fpu_location(lnode: tnode);
  62. end;
  63. implementation
  64. uses
  65. systems,
  66. globtype,globals,
  67. cutils,verbose,
  68. symconst,
  69. defutil,
  70. aasmbase,aasmtai,aasmdata,aasmcpu,
  71. symtype,symdef,symcpu,
  72. cgbase,pass_2,
  73. cpuinfo,cpubase,paramgr,
  74. nbas,ncon,ncal,ncnv,nld,ncgutil,
  75. tgobj,
  76. cga,cgutils,cgx86,cgobj,hlcgobj;
  77. {*****************************************************************************
  78. TX86INLINENODE
  79. *****************************************************************************}
  80. function tx86inlinenode.first_pi : tnode;
  81. begin
  82. if (tfloatdef(pbestrealtype^).floattype=s80real) then
  83. begin
  84. expectloc:=LOC_FPUREGISTER;
  85. first_pi := nil;
  86. end
  87. else
  88. result:=inherited;
  89. end;
  90. function tx86inlinenode.first_arctan_real : tnode;
  91. begin
  92. {$ifdef i8086}
  93. { FPATAN's range is limited to (0 <= value < 1) on the 8087 and 80287,
  94. so we need to use the RTL helper on these FPUs }
  95. if current_settings.cputype < cpu_386 then
  96. begin
  97. result := inherited;
  98. exit;
  99. end;
  100. {$endif i8086}
  101. if (tfloatdef(pbestrealtype^).floattype=s80real) then
  102. begin
  103. expectloc:=LOC_FPUREGISTER;
  104. first_arctan_real := nil;
  105. end
  106. else
  107. result:=inherited;
  108. end;
  109. function tx86inlinenode.first_abs_real : tnode;
  110. begin
  111. if use_vectorfpu(resultdef) then
  112. expectloc:=LOC_MMREGISTER
  113. else
  114. expectloc:=LOC_FPUREGISTER;
  115. first_abs_real := nil;
  116. end;
  117. function tx86inlinenode.first_sqr_real : tnode;
  118. begin
  119. if use_vectorfpu(resultdef) then
  120. expectloc:=LOC_MMREGISTER
  121. else
  122. expectloc:=LOC_FPUREGISTER;
  123. first_sqr_real := nil;
  124. end;
  125. function tx86inlinenode.first_sqrt_real : tnode;
  126. begin
  127. if use_vectorfpu(resultdef) then
  128. expectloc:=LOC_MMREGISTER
  129. else
  130. expectloc:=LOC_FPUREGISTER;
  131. first_sqrt_real := nil;
  132. end;
  133. function tx86inlinenode.first_ln_real : tnode;
  134. begin
  135. if (tfloatdef(pbestrealtype^).floattype=s80real) then
  136. begin
  137. expectloc:=LOC_FPUREGISTER;
  138. first_ln_real := nil;
  139. end
  140. else
  141. result:=inherited;
  142. end;
  143. function tx86inlinenode.first_cos_real : tnode;
  144. begin
  145. {$ifdef i8086}
  146. { FCOS is 387+ }
  147. if current_settings.cputype < cpu_386 then
  148. begin
  149. result := inherited;
  150. exit;
  151. end;
  152. {$endif i8086}
  153. if (tfloatdef(pbestrealtype^).floattype=s80real) then
  154. begin
  155. expectloc:=LOC_FPUREGISTER;
  156. result:=nil;
  157. end
  158. else
  159. result:=inherited;
  160. end;
  161. function tx86inlinenode.first_sin_real : tnode;
  162. begin
  163. {$ifdef i8086}
  164. { FSIN is 387+ }
  165. if current_settings.cputype < cpu_386 then
  166. begin
  167. result := inherited;
  168. exit;
  169. end;
  170. {$endif i8086}
  171. if (tfloatdef(pbestrealtype^).floattype=s80real) then
  172. begin
  173. expectloc:=LOC_FPUREGISTER;
  174. result:=nil;
  175. end
  176. else
  177. result:=inherited;
  178. end;
  179. function tx86inlinenode.first_round_real : tnode;
  180. begin
  181. {$ifdef x86_64}
  182. if use_vectorfpu(left.resultdef) then
  183. expectloc:=LOC_REGISTER
  184. else
  185. {$endif x86_64}
  186. expectloc:=LOC_REFERENCE;
  187. result:=nil;
  188. end;
  189. function tx86inlinenode.first_trunc_real: tnode;
  190. begin
  191. if (cs_opt_size in current_settings.optimizerswitches)
  192. {$ifdef x86_64}
  193. and not(use_vectorfpu(left.resultdef))
  194. {$endif x86_64}
  195. then
  196. result:=inherited
  197. else
  198. begin
  199. {$ifdef x86_64}
  200. if use_vectorfpu(left.resultdef) then
  201. expectloc:=LOC_REGISTER
  202. else
  203. {$endif x86_64}
  204. expectloc:=LOC_REFERENCE;
  205. result:=nil;
  206. end;
  207. end;
  208. function tx86inlinenode.first_popcnt: tnode;
  209. begin
  210. Result:=nil;
  211. {$ifndef i8086}
  212. if (CPUX86_HAS_POPCNT in cpu_capabilities[current_settings.cputype])
  213. {$ifdef i386}
  214. and not is_64bit(left.resultdef)
  215. {$endif i386}
  216. then
  217. expectloc:=LOC_REGISTER
  218. else
  219. {$endif not i8086}
  220. Result:=inherited first_popcnt
  221. end;
  222. function tx86inlinenode.first_fma : tnode;
  223. begin
  224. {$ifndef i8086}
  225. if ((cpu_capabilities[current_settings.cputype]*[CPUX86_HAS_FMA,CPUX86_HAS_FMA4])<>[]) and
  226. ((is_double(resultdef)) or (is_single(resultdef))) then
  227. begin
  228. expectloc:=LOC_MMREGISTER;
  229. Result:=nil;
  230. end
  231. else
  232. {$endif i8086}
  233. Result:=inherited first_fma;
  234. end;
  235. function tx86inlinenode.first_sse : tnode;
  236. begin
  237. {$ifndef i8086}
  238. if ((cpu_capabilities[current_settings.cputype]*[CPUX86_HAS_SSEUNIT])<>[]) then
  239. case inlinenumber of
  240. {$i x86first.inc}
  241. end
  242. else
  243. {$endif i8086}
  244. Result:=inherited first_fma;
  245. end;
  246. procedure tx86inlinenode.second_pi;
  247. begin
  248. location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
  249. emit_none(A_FLDPI,S_NO);
  250. tcgx86(cg).inc_fpu_stack;
  251. location.register:=NR_FPU_RESULT_REG;
  252. end;
  253. { load the FPU into the an fpu register }
  254. procedure tx86inlinenode.load_fpu_location(lnode: tnode);
  255. begin
  256. location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
  257. location.register:=NR_FPU_RESULT_REG;
  258. secondpass(lnode);
  259. case lnode.location.loc of
  260. LOC_FPUREGISTER:
  261. ;
  262. LOC_CFPUREGISTER:
  263. begin
  264. cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,lnode.location.size,
  265. lnode.location.size,lnode.location.register,location.register);
  266. end;
  267. LOC_REFERENCE,LOC_CREFERENCE:
  268. begin
  269. cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
  270. lnode.location.size,lnode.location.size,
  271. lnode.location.reference,location.register);
  272. end;
  273. LOC_MMREGISTER,LOC_CMMREGISTER:
  274. begin
  275. location:=lnode.location;
  276. hlcg.location_force_fpureg(current_asmdata.CurrAsmList,location,resultdef,false);
  277. end;
  278. else
  279. internalerror(309991);
  280. end;
  281. end;
  282. procedure tx86inlinenode.second_arctan_real;
  283. begin
  284. load_fpu_location(left);
  285. emit_none(A_FLD1,S_NO);
  286. emit_none(A_FPATAN,S_NO);
  287. end;
  288. procedure tx86inlinenode.second_abs_real;
  289. var
  290. href : treference;
  291. begin
  292. if use_vectorfpu(resultdef) then
  293. begin
  294. secondpass(left);
  295. if left.location.loc<>LOC_MMREGISTER then
  296. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
  297. if UseAVX then
  298. begin
  299. location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
  300. location.register:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
  301. end
  302. else
  303. location:=left.location;
  304. case tfloatdef(resultdef).floattype of
  305. s32real:
  306. begin
  307. reference_reset_symbol(href,current_asmdata.RefAsmSymbol(target_info.cprefix+'FPC_ABSMASK_SINGLE'),0,4);
  308. tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList, href);
  309. if UseAVX then
  310. current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg_reg(
  311. A_VANDPS,S_XMM,href,left.location.register,location.register))
  312. else
  313. current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_ANDPS,S_XMM,href,location.register));
  314. end;
  315. s64real:
  316. begin
  317. reference_reset_symbol(href,current_asmdata.RefAsmSymbol(target_info.cprefix+'FPC_ABSMASK_DOUBLE'),0,4);
  318. tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList, href);
  319. if UseAVX then
  320. current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg_reg(
  321. A_VANDPD,S_XMM,href,left.location.register,location.register))
  322. else
  323. current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_ANDPD,S_XMM,href,location.register))
  324. end;
  325. else
  326. internalerror(200506081);
  327. end;
  328. end
  329. else
  330. begin
  331. load_fpu_location(left);
  332. emit_none(A_FABS,S_NO);
  333. end;
  334. end;
  335. procedure tx86inlinenode.second_round_real;
  336. begin
  337. {$ifdef x86_64}
  338. if use_vectorfpu(left.resultdef) then
  339. begin
  340. secondpass(left);
  341. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
  342. location_reset(location,LOC_REGISTER,OS_S64);
  343. location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_S64);
  344. if UseAVX then
  345. case left.location.size of
  346. OS_F32:
  347. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VCVTSS2SI,S_Q,left.location.register,location.register));
  348. OS_F64:
  349. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VCVTSD2SI,S_Q,left.location.register,location.register));
  350. else
  351. internalerror(2007031402);
  352. end
  353. else
  354. case left.location.size of
  355. OS_F32:
  356. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CVTSS2SI,S_Q,left.location.register,location.register));
  357. OS_F64:
  358. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CVTSD2SI,S_Q,left.location.register,location.register));
  359. else
  360. internalerror(2007031402);
  361. end;
  362. end
  363. else
  364. {$endif x86_64}
  365. begin
  366. load_fpu_location(left);
  367. location_reset_ref(location,LOC_REFERENCE,OS_S64,0);
  368. tg.GetTemp(current_asmdata.CurrAsmList,resultdef.size,resultdef.alignment,tt_normal,location.reference);
  369. emit_ref(A_FISTP,S_IQ,location.reference);
  370. tcgx86(cg).dec_fpu_stack;
  371. emit_none(A_FWAIT,S_NO);
  372. end;
  373. end;
  374. procedure tx86inlinenode.second_trunc_real;
  375. var
  376. oldcw,newcw : treference;
  377. begin
  378. {$ifdef x86_64}
  379. if use_vectorfpu(left.resultdef) and
  380. not((left.location.loc=LOC_FPUREGISTER) and (current_settings.fputype>=fpu_sse3)) then
  381. begin
  382. secondpass(left);
  383. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
  384. location_reset(location,LOC_REGISTER,OS_S64);
  385. location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_S64);
  386. if UseAVX then
  387. case left.location.size of
  388. OS_F32:
  389. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VCVTTSS2SI,S_Q,left.location.register,location.register));
  390. OS_F64:
  391. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VCVTTSD2SI,S_Q,left.location.register,location.register));
  392. else
  393. internalerror(2007031401);
  394. end
  395. else
  396. case left.location.size of
  397. OS_F32:
  398. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CVTTSS2SI,S_Q,left.location.register,location.register));
  399. OS_F64:
  400. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CVTTSD2SI,S_Q,left.location.register,location.register));
  401. else
  402. internalerror(2007031401);
  403. end;
  404. end
  405. else
  406. {$endif x86_64}
  407. begin
  408. if (current_settings.fputype>=fpu_sse3) then
  409. begin
  410. load_fpu_location(left);
  411. location_reset_ref(location,LOC_REFERENCE,OS_S64,0);
  412. tg.GetTemp(current_asmdata.CurrAsmList,resultdef.size,resultdef.alignment,tt_normal,location.reference);
  413. emit_ref(A_FISTTP,S_IQ,location.reference);
  414. tcgx86(cg).dec_fpu_stack;
  415. end
  416. else
  417. begin
  418. tg.GetTemp(current_asmdata.CurrAsmList,2,2,tt_normal,oldcw);
  419. tg.GetTemp(current_asmdata.CurrAsmList,2,2,tt_normal,newcw);
  420. {$ifdef i8086}
  421. if current_settings.cputype<=cpu_286 then
  422. begin
  423. emit_ref(A_FSTCW,S_NO,newcw);
  424. emit_ref(A_FSTCW,S_NO,oldcw);
  425. emit_none(A_FWAIT,S_NO);
  426. end
  427. else
  428. {$endif i8086}
  429. begin
  430. emit_ref(A_FNSTCW,S_NO,newcw);
  431. emit_ref(A_FNSTCW,S_NO,oldcw);
  432. end;
  433. emit_const_ref(A_OR,S_W,$0f00,newcw);
  434. load_fpu_location(left);
  435. emit_ref(A_FLDCW,S_NO,newcw);
  436. location_reset_ref(location,LOC_REFERENCE,OS_S64,0);
  437. tg.GetTemp(current_asmdata.CurrAsmList,resultdef.size,resultdef.alignment,tt_normal,location.reference);
  438. emit_ref(A_FISTP,S_IQ,location.reference);
  439. tcgx86(cg).dec_fpu_stack;
  440. emit_ref(A_FLDCW,S_NO,oldcw);
  441. emit_none(A_FWAIT,S_NO);
  442. tg.UnGetTemp(current_asmdata.CurrAsmList,oldcw);
  443. tg.UnGetTemp(current_asmdata.CurrAsmList,newcw);
  444. end;
  445. end;
  446. end;
  447. procedure tx86inlinenode.second_sqr_real;
  448. begin
  449. if use_vectorfpu(resultdef) then
  450. begin
  451. secondpass(left);
  452. location_reset(location,LOC_MMREGISTER,left.location.size);
  453. location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
  454. if UseAVX then
  455. begin
  456. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
  457. cg.a_opmm_reg_reg_reg(current_asmdata.CurrAsmList,OP_MUL,left.location.size,left.location.register,left.location.register,location.register,mms_movescalar);
  458. end
  459. else
  460. begin
  461. if left.location.loc in [LOC_CFPUREGISTER,LOC_FPUREGISTER] then
  462. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
  463. cg.a_loadmm_loc_reg(current_asmdata.CurrAsmList,location.size,left.location,location.register,mms_movescalar);
  464. cg.a_opmm_reg_reg(current_asmdata.CurrAsmList,OP_MUL,left.location.size,location.register,location.register,mms_movescalar);
  465. end;
  466. end
  467. else
  468. begin
  469. load_fpu_location(left);
  470. emit_reg_reg(A_FMUL,S_NO,NR_ST0,NR_ST0);
  471. end;
  472. end;
  473. procedure tx86inlinenode.second_sqrt_real;
  474. begin
  475. if use_vectorfpu(resultdef) then
  476. begin
  477. secondpass(left);
  478. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
  479. location_reset(location,LOC_MMREGISTER,left.location.size);
  480. location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
  481. if UseAVX then
  482. case tfloatdef(resultdef).floattype of
  483. s32real:
  484. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSQRTSS,S_XMM,left.location.register,location.register,location.register));
  485. s64real:
  486. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_VSQRTSD,S_XMM,left.location.register,location.register,location.register));
  487. else
  488. internalerror(200510031);
  489. end
  490. else
  491. case tfloatdef(resultdef).floattype of
  492. s32real:
  493. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_SQRTSS,S_XMM,left.location.register,location.register));
  494. s64real:
  495. current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_SQRTSD,S_XMM,left.location.register,location.register));
  496. else
  497. internalerror(200510031);
  498. end;
  499. end
  500. else
  501. begin
  502. load_fpu_location(left);
  503. emit_none(A_FSQRT,S_NO);
  504. end;
  505. end;
  506. procedure tx86inlinenode.second_ln_real;
  507. begin
  508. load_fpu_location(left);
  509. emit_none(A_FLDLN2,S_NO);
  510. emit_none(A_FXCH,S_NO);
  511. emit_none(A_FYL2X,S_NO);
  512. end;
  513. procedure tx86inlinenode.second_cos_real;
  514. begin
  515. {$ifdef i8086}
  516. { FCOS is 387+ }
  517. if current_settings.cputype < cpu_386 then
  518. begin
  519. inherited;
  520. exit;
  521. end;
  522. {$endif i8086}
  523. load_fpu_location(left);
  524. emit_none(A_FCOS,S_NO);
  525. end;
  526. procedure tx86inlinenode.second_sin_real;
  527. begin
  528. {$ifdef i8086}
  529. { FSIN is 387+ }
  530. if current_settings.cputype < cpu_386 then
  531. begin
  532. inherited;
  533. exit;
  534. end;
  535. {$endif i8086}
  536. load_fpu_location(left);
  537. emit_none(A_FSIN,S_NO)
  538. end;
  539. procedure tx86inlinenode.second_prefetch;
  540. var
  541. ref : treference;
  542. r : tregister;
  543. begin
  544. {$if defined(i386) or defined(i8086)}
  545. if current_settings.cputype>=cpu_Pentium3 then
  546. {$endif i386 or i8086}
  547. begin
  548. secondpass(left);
  549. case left.location.loc of
  550. LOC_CREFERENCE,
  551. LOC_REFERENCE:
  552. begin
  553. r:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
  554. cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.location.reference,r);
  555. reference_reset_base(ref,r,0,left.location.reference.alignment);
  556. current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_PREFETCHNTA,S_NO,ref));
  557. end;
  558. else
  559. { nothing to prefetch };
  560. end;
  561. end;
  562. end;
  563. {$ifndef i8086}
  564. procedure tx86inlinenode.second_abs_long;
  565. var
  566. hregister : tregister;
  567. opsize : tcgsize;
  568. hp : taicpu;
  569. begin
  570. {$ifdef i386}
  571. if not(CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype]) then
  572. begin
  573. opsize:=def_cgsize(left.resultdef);
  574. secondpass(left);
  575. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
  576. location:=left.location;
  577. location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
  578. emit_reg_reg(A_MOV,S_L,left.location.register,location.register);
  579. emit_const_reg(A_SAR,tcgsize2opsize[opsize],31,left.location.register);
  580. emit_reg_reg(A_XOR,S_L,left.location.register,location.register);
  581. emit_reg_reg(A_SUB,S_L,left.location.register,location.register);
  582. end
  583. else
  584. {$endif i386}
  585. begin
  586. opsize:=def_cgsize(left.resultdef);
  587. secondpass(left);
  588. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
  589. hregister:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
  590. location:=left.location;
  591. location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
  592. cg.a_load_reg_reg(current_asmdata.CurrAsmList,opsize,opsize,left.location.register,hregister);
  593. cg.a_load_reg_reg(current_asmdata.CurrAsmList,opsize,opsize,left.location.register,location.register);
  594. emit_reg(A_NEG,tcgsize2opsize[opsize],hregister);
  595. hp:=taicpu.op_reg_reg(A_CMOVcc,tcgsize2opsize[opsize],hregister,location.register);
  596. hp.condition:=C_NS;
  597. current_asmdata.CurrAsmList.concat(hp);
  598. end;
  599. end;
  600. {$endif not i8086}
  601. {*****************************************************************************
  602. INCLUDE/EXCLUDE GENERIC HANDLING
  603. *****************************************************************************}
  604. procedure tx86inlinenode.second_IncludeExclude;
  605. var
  606. hregister,
  607. hregister2: tregister;
  608. setbase : aint;
  609. bitsperop,l : longint;
  610. cgop : topcg;
  611. asmop : tasmop;
  612. opdef : tdef;
  613. opsize,
  614. orgsize: tcgsize;
  615. begin
  616. {$ifdef i8086}
  617. { BTS and BTR are 386+ }
  618. if current_settings.cputype < cpu_386 then
  619. begin
  620. inherited;
  621. exit;
  622. end;
  623. {$endif i8086}
  624. if is_smallset(tcallparanode(left).resultdef) then
  625. begin
  626. opdef:=tcallparanode(left).resultdef;
  627. opsize:=int_cgsize(opdef.size)
  628. end
  629. else
  630. begin
  631. opdef:=u32inttype;
  632. opsize:=OS_32;
  633. end;
  634. bitsperop:=(8*tcgsize2size[opsize]);
  635. secondpass(tcallparanode(left).left);
  636. secondpass(tcallparanode(tcallparanode(left).right).left);
  637. setbase:=tsetdef(tcallparanode(left).left.resultdef).setbase;
  638. if tcallparanode(tcallparanode(left).right).left.location.loc=LOC_CONSTANT then
  639. begin
  640. { calculate bit position }
  641. l:=1 shl ((tcallparanode(tcallparanode(left).right).left.location.value-setbase) mod bitsperop);
  642. { determine operator }
  643. if inlinenumber=in_include_x_y then
  644. cgop:=OP_OR
  645. else
  646. begin
  647. cgop:=OP_AND;
  648. l:=not(l);
  649. end;
  650. case tcallparanode(left).left.location.loc of
  651. LOC_REFERENCE :
  652. begin
  653. inc(tcallparanode(left).left.location.reference.offset,
  654. ((tcallparanode(tcallparanode(left).right).left.location.value-setbase) div bitsperop)*tcgsize2size[opsize]);
  655. cg.a_op_const_ref(current_asmdata.CurrAsmList,cgop,opsize,l,tcallparanode(left).left.location.reference);
  656. end;
  657. LOC_CREGISTER :
  658. cg.a_op_const_reg(current_asmdata.CurrAsmList,cgop,tcallparanode(left).left.location.size,l,tcallparanode(left).left.location.register);
  659. else
  660. internalerror(200405022);
  661. end;
  662. end
  663. else
  664. begin
  665. orgsize:=opsize;
  666. if opsize in [OS_8,OS_S8] then
  667. begin
  668. opdef:=u32inttype;
  669. opsize:=OS_32;
  670. end;
  671. { determine asm operator }
  672. if inlinenumber=in_include_x_y then
  673. asmop:=A_BTS
  674. else
  675. asmop:=A_BTR;
  676. hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,tcallparanode(tcallparanode(left).right).left.resultdef,opdef,true);
  677. register_maybe_adjust_setbase(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,setbase);
  678. hregister:=tcallparanode(tcallparanode(left).right).left.location.register;
  679. if (tcallparanode(left).left.location.loc=LOC_REFERENCE) then
  680. emit_reg_ref(asmop,tcgsize2opsize[opsize],hregister,tcallparanode(left).left.location.reference)
  681. else
  682. begin
  683. { second argument can't be an 8 bit register either }
  684. hregister2:=tcallparanode(left).left.location.register;
  685. if (orgsize in [OS_8,OS_S8]) then
  686. hregister2:=cg.makeregsize(current_asmdata.CurrAsmList,hregister2,opsize);
  687. emit_reg_reg(asmop,tcgsize2opsize[opsize],hregister,hregister2);
  688. end;
  689. end;
  690. end;
  691. procedure tx86inlinenode.second_popcnt;
  692. var
  693. opsize: tcgsize;
  694. begin
  695. secondpass(left);
  696. opsize:=tcgsize2unsigned[left.location.size];
  697. { no 8 Bit popcont }
  698. if opsize=OS_8 then
  699. opsize:=OS_16;
  700. if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE]) or
  701. (left.location.size<>opsize) then
  702. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
  703. location_reset(location,LOC_REGISTER,opsize);
  704. location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
  705. if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
  706. emit_reg_reg(A_POPCNT,TCGSize2OpSize[opsize],left.location.register,location.register)
  707. else
  708. emit_ref_reg(A_POPCNT,TCGSize2OpSize[opsize],left.location.reference,location.register);
  709. end;
  710. procedure tx86inlinenode.second_fma;
  711. const
  712. op : array[false..true,false..true,s32real..s64real,0..3] of TAsmOp =
  713. (
  714. { positive product }
  715. (
  716. { positive third operand }
  717. ((A_VFMADD231SS,A_VFMADD231SS,A_VFMADD231SS,A_VFMADD213SS),
  718. (A_VFMADD231SD,A_VFMADD231SD,A_VFMADD231SD,A_VFMADD213SD)
  719. ),
  720. { negative third operand }
  721. ((A_VFMSUB231SS,A_VFMSUB231SS,A_VFMSUB231SS,A_VFMSUB213SS),
  722. (A_VFMSUB231SD,A_VFMSUB231SD,A_VFMSUB231SD,A_VFMSUB213SD)
  723. )
  724. ),
  725. { negative product }
  726. (
  727. { positive third operand }
  728. ((A_VFNMADD231SS,A_VFNMADD231SS,A_VFNMADD231SS,A_VFNMADD213SS),
  729. (A_VFNMADD231SD,A_VFNMADD231SD,A_VFNMADD231SD,A_VFNMADD213SD)
  730. ),
  731. { negative third operand }
  732. ((A_VFNMSUB231SS,A_VFNMSUB231SS,A_VFNMSUB231SS,A_VFNMSUB213SS),
  733. (A_VFNMSUB231SD,A_VFNMSUB231SD,A_VFNMSUB231SD,A_VFNMSUB213SD)
  734. )
  735. )
  736. );
  737. var
  738. paraarray : array[1..3] of tnode;
  739. memop,
  740. i : integer;
  741. negop3,
  742. negproduct,
  743. gotmem : boolean;
  744. hp : tnode;
  745. begin
  746. {$ifndef i8086}
  747. if (cpu_capabilities[current_settings.cputype]*[CPUX86_HAS_FMA,CPUX86_HAS_FMA4])<>[] then
  748. begin
  749. negop3:=false;
  750. negproduct:=false;
  751. paraarray[1]:=tcallparanode(tcallparanode(tcallparanode(parameters).nextpara).nextpara).paravalue;
  752. paraarray[2]:=tcallparanode(tcallparanode(parameters).nextpara).paravalue;
  753. paraarray[3]:=tcallparanode(parameters).paravalue;
  754. { check if a neg. node can be removed
  755. this is possible because changing the sign of
  756. a floating point number does not affect its absolute
  757. value in any way
  758. }
  759. if paraarray[1].nodetype=unaryminusn then
  760. begin
  761. paraarray[1]:=tunarynode(paraarray[1]).left;
  762. { do not release the unused unary minus node, it is kept and release together with the other nodes,
  763. only no code is generated for it }
  764. negproduct:=not(negproduct);
  765. end;
  766. if paraarray[2].nodetype=unaryminusn then
  767. begin
  768. paraarray[2]:=tunarynode(paraarray[2]).left;
  769. { do not release the unused unary minus node, it is kept and release together with the other nodes,
  770. only no code is generated for it }
  771. negproduct:=not(negproduct);
  772. end;
  773. if paraarray[3].nodetype=unaryminusn then
  774. begin
  775. paraarray[3]:=tunarynode(paraarray[3]).left;
  776. { do not release the unused unary minus node, it is kept and release together with the other nodes,
  777. only no code is generated for it }
  778. negop3:=true;
  779. end;
  780. for i:=1 to 3 do
  781. secondpass(paraarray[i]);
  782. { only one memory operand is allowed }
  783. gotmem:=false;
  784. memop:=0;
  785. for i:=1 to 3 do
  786. begin
  787. if not(paraarray[i].location.loc in [LOC_MMREGISTER,LOC_CMMREGISTER]) then
  788. begin
  789. if (paraarray[i].location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) and not(gotmem) then
  790. begin
  791. memop:=i;
  792. gotmem:=true;
  793. end
  794. else
  795. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,paraarray[i].location,paraarray[i].resultdef,true);
  796. end;
  797. end;
  798. location_reset(location,LOC_MMREGISTER,paraarray[1].location.size);
  799. location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
  800. if gotmem then
  801. begin
  802. case memop of
  803. 1:
  804. begin
  805. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[3].resultdef,resultdef,
  806. paraarray[3].location.register,location.register,mms_movescalar);
  807. emit_ref_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,memop],S_NO,
  808. paraarray[1].location.reference,paraarray[2].location.register,location.register);
  809. end;
  810. 2:
  811. begin
  812. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[3].resultdef,resultdef,
  813. paraarray[3].location.register,location.register,mms_movescalar);
  814. emit_ref_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,memop],S_NO,
  815. paraarray[2].location.reference,paraarray[1].location.register,location.register);
  816. end;
  817. 3:
  818. begin
  819. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[1].resultdef,resultdef,
  820. paraarray[1].location.register,location.register,mms_movescalar);
  821. emit_ref_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,memop],S_NO,
  822. paraarray[3].location.reference,paraarray[2].location.register,location.register);
  823. end
  824. else
  825. internalerror(2014041301);
  826. end;
  827. end
  828. else
  829. begin
  830. { try to use the location which is already in a temp. mm register as destination,
  831. so the compiler might be able to re-use the register }
  832. if paraarray[1].location.loc=LOC_MMREGISTER then
  833. begin
  834. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[1].resultdef,resultdef,
  835. paraarray[1].location.register,location.register,mms_movescalar);
  836. emit_reg_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,3],S_NO,
  837. paraarray[3].location.register,paraarray[2].location.register,location.register);
  838. end
  839. else if paraarray[2].location.loc=LOC_MMREGISTER then
  840. begin
  841. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[2].resultdef,resultdef,
  842. paraarray[2].location.register,location.register,mms_movescalar);
  843. emit_reg_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,3],S_NO,
  844. paraarray[3].location.register,paraarray[1].location.register,location.register);
  845. end
  846. else
  847. begin
  848. hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,paraarray[3].resultdef,resultdef,
  849. paraarray[3].location.register,location.register,mms_movescalar);
  850. emit_reg_reg_reg(op[negproduct,negop3,tfloatdef(resultdef).floattype,0],S_NO,
  851. paraarray[1].location.register,paraarray[2].location.register,location.register);
  852. end;
  853. end;
  854. end
  855. else
  856. {$endif i8086}
  857. internalerror(2014032301);
  858. end;
  859. procedure tx86inlinenode.second_sse;
  860. var
  861. paraarray : array[1..4] of tnode;
  862. i : integer;
  863. op: TAsmOp;
  864. function GetConstInt(n: tnode): longint;
  865. begin
  866. if is_constintnode(n) then
  867. result:=tordconstnode(n).value.svalue
  868. else
  869. Message(type_e_constant_expr_expected);
  870. end;
  871. procedure GetParameters(count: longint);
  872. var
  873. i: longint;
  874. p: tnode;
  875. begin
  876. if (count=1) and
  877. (not (left is tcallparanode)) then
  878. paraarray[1]:=left
  879. else
  880. begin
  881. p:=left;
  882. for i := count downto 1 do
  883. begin
  884. paraarray[i]:=tcallparanode(p).paravalue;
  885. p:=tcallparanode(p).nextpara;
  886. end;
  887. end;
  888. end;
  889. procedure location_force_mmxreg(list:TAsmList;var l: tlocation;maybeconst:boolean);
  890. var
  891. reg : tregister;
  892. begin
  893. if (l.loc<>LOC_MMXREGISTER) and
  894. ((l.loc<>LOC_CMMXREGISTER) or (not maybeconst)) then
  895. begin
  896. reg:=tcgx86(cg).getmmxregister(list);
  897. cg.a_loadmm_loc_reg(list,OS_M64,l,reg,nil);
  898. location_freetemp(list,l);
  899. location_reset(l,LOC_MMXREGISTER,OS_M64);
  900. l.register:=reg;
  901. end;
  902. end;
  903. procedure location_make_ref(var loc: tlocation);
  904. var
  905. hloc: tlocation;
  906. begin
  907. case loc.loc of
  908. LOC_CREGISTER,
  909. LOC_REGISTER:
  910. begin
  911. location_reset_ref(hloc, LOC_REFERENCE, OS_32, 1);
  912. hloc.reference.base:=loc.register;
  913. loc:=hloc;
  914. end;
  915. LOC_CREFERENCE,
  916. LOC_REFERENCE:
  917. begin
  918. end;
  919. else
  920. begin
  921. hlcg.location_force_reg(current_asmdata.CurrAsmList,loc,u32inttype,u32inttype,false);
  922. location_reset_ref(hloc, LOC_REFERENCE, OS_32, 1);
  923. hloc.reference.base:=loc.register;
  924. loc:=hloc;
  925. end;
  926. end;
  927. end;
  928. begin
  929. case inlinenumber of
  930. {$i x86second.inc}
  931. end;
  932. end;
  933. end.