cgcpu.pas 83 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the ARM
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. tcgarm = class(tcg)
  29. { true, if the next arithmetic operation should modify the flags }
  30. cgsetflags : boolean;
  31. procedure init_register_allocators;override;
  32. procedure done_register_allocators;override;
  33. procedure a_param_const(list : TAsmList;size : tcgsize;a : aint;const paraloc : TCGPara);override;
  34. procedure a_param_ref(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  35. procedure a_paramaddr_ref(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  36. procedure a_call_name(list : TAsmList;const s : string);override;
  37. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  38. procedure a_call_ref(list : TAsmList;ref: treference);override;
  39. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister); override;
  40. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  41. procedure a_op_const_reg_reg(list: TAsmList; op: TOpCg;
  42. size: tcgsize; a: aint; src, dst: tregister); override;
  43. procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
  44. size: tcgsize; src1, src2, dst: tregister); override;
  45. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  46. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  47. { move instructions }
  48. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : aint;reg : tregister);override;
  49. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  50. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  51. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  52. function a_internal_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference):treference;
  53. function a_internal_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister):treference;
  54. { fpu move instructions }
  55. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  56. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  57. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  58. procedure a_paramfpu_ref(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
  59. { comparison operations }
  60. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  61. l : tasmlabel);override;
  62. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  63. procedure a_jmp_name(list : TAsmList;const s : string); override;
  64. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  65. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  66. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  67. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  68. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  69. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  70. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : aint);override;
  71. procedure g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : aint);override;
  72. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  73. procedure g_concatcopy_internal(list : TAsmList;const source,dest : treference;len : aint;aligned : boolean);
  74. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  75. procedure g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);override;
  76. procedure g_save_registers(list : TAsmList);override;
  77. procedure g_restore_registers(list : TAsmList);override;
  78. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  79. procedure fixref(list : TAsmList;var ref : treference);
  80. function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
  81. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  82. private
  83. { clear out potential overflow bits from 8 or 16 bit operations }
  84. { the upper 24/16 bits of a register after an operation }
  85. procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
  86. end;
  87. tcg64farm = class(tcg64f32)
  88. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  89. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  90. procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
  91. procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  92. procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  93. procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  94. end;
  95. const
  96. OpCmp2AsmCond : Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_GT,
  97. C_LT,C_GE,C_LE,C_NE,C_LS,C_CC,C_CS,C_HI);
  98. winstackpagesize = 4096;
  99. function get_fpu_postfix(def : tdef) : toppostfix;
  100. implementation
  101. uses
  102. globals,verbose,systems,cutils,
  103. fmodule,
  104. symconst,symsym,
  105. tgobj,
  106. procinfo,cpupi,
  107. paramgr;
  108. function get_fpu_postfix(def : tdef) : toppostfix;
  109. begin
  110. if def.typ=floatdef then
  111. begin
  112. case tfloatdef(def).floattype of
  113. s32real:
  114. result:=PF_S;
  115. s64real:
  116. result:=PF_D;
  117. s80real:
  118. result:=PF_E;
  119. else
  120. internalerror(200401272);
  121. end;
  122. end
  123. else
  124. internalerror(200401271);
  125. end;
  126. procedure tcgarm.init_register_allocators;
  127. begin
  128. inherited init_register_allocators;
  129. { currently, we save R14 always, so we can use it }
  130. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  131. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  132. RS_R9,RS_R10,RS_R12,RS_R14],first_int_imreg,[]);
  133. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  134. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
  135. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
  136. [RS_S0,RS_S1,RS_R2,RS_R3,RS_R4,RS_S31],first_mm_imreg,[]);
  137. end;
  138. procedure tcgarm.done_register_allocators;
  139. begin
  140. rg[R_INTREGISTER].free;
  141. rg[R_FPUREGISTER].free;
  142. rg[R_MMREGISTER].free;
  143. inherited done_register_allocators;
  144. end;
  145. procedure tcgarm.a_param_const(list : TAsmList;size : tcgsize;a : aint;const paraloc : TCGPara);
  146. var
  147. ref: treference;
  148. begin
  149. paraloc.check_simple_location;
  150. case paraloc.location^.loc of
  151. LOC_REGISTER,LOC_CREGISTER:
  152. a_load_const_reg(list,size,a,paraloc.location^.register);
  153. LOC_REFERENCE:
  154. begin
  155. reference_reset(ref);
  156. ref.base:=paraloc.location^.reference.index;
  157. ref.offset:=paraloc.location^.reference.offset;
  158. a_load_const_ref(list,size,a,ref);
  159. end;
  160. else
  161. internalerror(2002081101);
  162. end;
  163. end;
  164. procedure tcgarm.a_param_ref(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  165. var
  166. tmpref, ref: treference;
  167. location: pcgparalocation;
  168. sizeleft: aint;
  169. begin
  170. location := paraloc.location;
  171. tmpref := r;
  172. sizeleft := paraloc.intsize;
  173. while assigned(location) do
  174. begin
  175. case location^.loc of
  176. LOC_REGISTER,LOC_CREGISTER:
  177. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  178. LOC_REFERENCE:
  179. begin
  180. reference_reset_base(ref,location^.reference.index,location^.reference.offset);
  181. { doubles in softemu mode have a strange order of registers and references }
  182. if location^.size=OS_32 then
  183. g_concatcopy(list,tmpref,ref,4)
  184. else
  185. begin
  186. g_concatcopy(list,tmpref,ref,sizeleft);
  187. if assigned(location^.next) then
  188. internalerror(2005010710);
  189. end;
  190. end;
  191. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  192. case location^.size of
  193. OS_F32, OS_F64:
  194. a_loadfpu_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  195. else
  196. internalerror(2002072801);
  197. end;
  198. LOC_VOID:
  199. begin
  200. // nothing to do
  201. end;
  202. else
  203. internalerror(2002081103);
  204. end;
  205. inc(tmpref.offset,tcgsize2size[location^.size]);
  206. dec(sizeleft,tcgsize2size[location^.size]);
  207. location := location^.next;
  208. end;
  209. end;
  210. procedure tcgarm.a_paramaddr_ref(list : TAsmList;const r : treference;const paraloc : TCGPara);
  211. var
  212. ref: treference;
  213. tmpreg: tregister;
  214. begin
  215. paraloc.check_simple_location;
  216. case paraloc.location^.loc of
  217. LOC_REGISTER,LOC_CREGISTER:
  218. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  219. LOC_REFERENCE:
  220. begin
  221. reference_reset(ref);
  222. ref.base := paraloc.location^.reference.index;
  223. ref.offset := paraloc.location^.reference.offset;
  224. tmpreg := getintregister(list,OS_ADDR);
  225. a_loadaddr_ref_reg(list,r,tmpreg);
  226. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  227. end;
  228. else
  229. internalerror(2002080701);
  230. end;
  231. end;
  232. procedure tcgarm.a_call_name(list : TAsmList;const s : string);
  233. begin
  234. list.concat(taicpu.op_sym(A_BL,current_asmdata.RefAsmSymbol(s)));
  235. {
  236. the compiler does not properly set this flag anymore in pass 1, and
  237. for now we only need it after pass 2 (I hope) (JM)
  238. if not(pi_do_call in current_procinfo.flags) then
  239. internalerror(2003060703);
  240. }
  241. include(current_procinfo.flags,pi_do_call);
  242. end;
  243. procedure tcgarm.a_call_reg(list : TAsmList;reg: tregister);
  244. begin
  245. list.concat(taicpu.op_reg_reg(A_MOV,NR_R14,NR_PC));
  246. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,reg));
  247. {
  248. the compiler does not properly set this flag anymore in pass 1, and
  249. for now we only need it after pass 2 (I hope) (JM)
  250. if not(pi_do_call in current_procinfo.flags) then
  251. internalerror(2003060703);
  252. }
  253. include(current_procinfo.flags,pi_do_call);
  254. end;
  255. procedure tcgarm.a_call_ref(list : TAsmList;ref: treference);
  256. begin
  257. a_reg_alloc(list,NR_R12);
  258. a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_R12);
  259. list.concat(taicpu.op_reg_reg(A_MOV,NR_R14,NR_PC));
  260. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R12));
  261. a_reg_dealloc(list,NR_R12);
  262. include(current_procinfo.flags,pi_do_call);
  263. end;
  264. procedure tcgarm.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister);
  265. begin
  266. a_op_const_reg_reg(list,op,size,a,reg,reg);
  267. end;
  268. procedure tcgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  269. begin
  270. case op of
  271. OP_NEG:
  272. list.concat(taicpu.op_reg_reg_const(A_RSB,dst,src,0));
  273. OP_NOT:
  274. begin
  275. list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
  276. case size of
  277. OS_8 :
  278. a_op_const_reg_reg(list,OP_AND,OS_INT,$ff,dst,dst);
  279. OS_16 :
  280. a_op_const_reg_reg(list,OP_AND,OS_INT,$ffff,dst,dst);
  281. end;
  282. end
  283. else
  284. a_op_reg_reg_reg(list,op,OS_32,src,dst,dst);
  285. end;
  286. end;
  287. const
  288. op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
  289. (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,A_NONE,A_MUL,A_MUL,A_NONE,A_NONE,A_ORR,
  290. A_NONE,A_NONE,A_NONE,A_SUB,A_EOR);
  291. procedure tcgarm.a_op_const_reg_reg(list: TAsmList; op: TOpCg;
  292. size: tcgsize; a: aint; src, dst: tregister);
  293. var
  294. ovloc : tlocation;
  295. begin
  296. a_op_const_reg_reg_checkoverflow(list,op,size,a,src,dst,false,ovloc);
  297. end;
  298. procedure tcgarm.a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
  299. size: tcgsize; src1, src2, dst: tregister);
  300. var
  301. ovloc : tlocation;
  302. begin
  303. a_op_reg_reg_reg_checkoverflow(list,op,size,src1,src2,dst,false,ovloc);
  304. end;
  305. procedure tcgarm.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);
  306. var
  307. shift : byte;
  308. tmpreg : tregister;
  309. so : tshifterop;
  310. l1 : longint;
  311. begin
  312. ovloc.loc:=LOC_VOID;
  313. if is_shifter_const(-a,shift) then
  314. case op of
  315. OP_ADD:
  316. begin
  317. op:=OP_SUB;
  318. a:=aint(dword(-a));
  319. end;
  320. OP_SUB:
  321. begin
  322. op:=OP_ADD;
  323. a:=aint(dword(-a));
  324. end
  325. end;
  326. if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
  327. case op of
  328. OP_NEG,OP_NOT,
  329. OP_DIV,OP_IDIV:
  330. internalerror(200308281);
  331. OP_SHL:
  332. begin
  333. if a>32 then
  334. internalerror(200308294);
  335. if a<>0 then
  336. begin
  337. shifterop_reset(so);
  338. so.shiftmode:=SM_LSL;
  339. so.shiftimm:=a;
  340. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  341. end
  342. else
  343. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  344. end;
  345. OP_SHR:
  346. begin
  347. if a>32 then
  348. internalerror(200308292);
  349. shifterop_reset(so);
  350. if a<>0 then
  351. begin
  352. so.shiftmode:=SM_LSR;
  353. so.shiftimm:=a;
  354. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  355. end
  356. else
  357. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  358. end;
  359. OP_SAR:
  360. begin
  361. if a>32 then
  362. internalerror(200308295);
  363. if a<>0 then
  364. begin
  365. shifterop_reset(so);
  366. so.shiftmode:=SM_ASR;
  367. so.shiftimm:=a;
  368. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  369. end
  370. else
  371. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  372. end;
  373. else
  374. list.concat(setoppostfix(
  375. taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
  376. ));
  377. if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then
  378. begin
  379. ovloc.loc:=LOC_FLAGS;
  380. case op of
  381. OP_ADD:
  382. ovloc.resflags:=F_CS;
  383. OP_SUB:
  384. ovloc.resflags:=F_CC;
  385. end;
  386. end;
  387. end
  388. else
  389. begin
  390. { there could be added some more sophisticated optimizations }
  391. if (op in [OP_MUL,OP_IMUL]) and (a=1) then
  392. a_load_reg_reg(list,size,size,src,dst)
  393. else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
  394. a_load_const_reg(list,size,0,dst)
  395. else if (op in [OP_IMUL]) and (a=-1) then
  396. a_op_reg_reg(list,OP_NEG,size,src,dst)
  397. { we do this here instead in the peephole optimizer because
  398. it saves us a register }
  399. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) and not(cgsetflags or setflags) then
  400. a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
  401. { for example : b=a*5 -> b=a*4+a with add instruction and shl }
  402. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
  403. begin
  404. if l1>32 then{roozbeh does this ever happen?}
  405. internalerror(200308296);
  406. shifterop_reset(so);
  407. so.shiftmode:=SM_LSL;
  408. so.shiftimm:=l1;
  409. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,so));
  410. end
  411. else
  412. begin
  413. tmpreg:=getintregister(list,size);
  414. a_load_const_reg(list,size,a,tmpreg);
  415. a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
  416. end;
  417. end;
  418. maybeadjustresult(list,op,size,dst);
  419. end;
  420. procedure tcgarm.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);
  421. var
  422. so : tshifterop;
  423. tmpreg,overflowreg : tregister;
  424. asmop : tasmop;
  425. begin
  426. ovloc.loc:=LOC_VOID;
  427. case op of
  428. OP_NEG,OP_NOT,
  429. OP_DIV,OP_IDIV:
  430. internalerror(200308281);
  431. OP_SHL:
  432. begin
  433. shifterop_reset(so);
  434. so.rs:=src1;
  435. so.shiftmode:=SM_LSL;
  436. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
  437. end;
  438. OP_SHR:
  439. begin
  440. shifterop_reset(so);
  441. so.rs:=src1;
  442. so.shiftmode:=SM_LSR;
  443. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
  444. end;
  445. OP_SAR:
  446. begin
  447. shifterop_reset(so);
  448. so.rs:=src1;
  449. so.shiftmode:=SM_ASR;
  450. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
  451. end;
  452. OP_IMUL,
  453. OP_MUL:
  454. begin
  455. if cgsetflags or setflags then
  456. begin
  457. overflowreg:=getintregister(list,size);
  458. if op=OP_IMUL then
  459. asmop:=A_SMULL
  460. else
  461. asmop:=A_UMULL;
  462. { the arm doesn't allow that rd and rm are the same }
  463. if dst=src2 then
  464. begin
  465. if dst<>src1 then
  466. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src1,src2))
  467. else
  468. begin
  469. tmpreg:=getintregister(list,size);
  470. a_load_reg_reg(list,size,size,src2,dst);
  471. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,tmpreg,src1));
  472. end;
  473. end
  474. else
  475. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src2,src1));
  476. if op=OP_IMUL then
  477. begin
  478. shifterop_reset(so);
  479. so.shiftmode:=SM_ASR;
  480. so.shiftimm:=31;
  481. list.concat(taicpu.op_reg_reg_shifterop(A_CMP,overflowreg,dst,so));
  482. end
  483. else
  484. list.concat(taicpu.op_reg_const(A_CMP,overflowreg,0));
  485. ovloc.loc:=LOC_FLAGS;
  486. ovloc.resflags:=F_NE;
  487. end
  488. else
  489. begin
  490. { the arm doesn't allow that rd and rm are the same }
  491. if dst=src2 then
  492. begin
  493. if dst<>src1 then
  494. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2))
  495. else
  496. begin
  497. tmpreg:=getintregister(list,size);
  498. a_load_reg_reg(list,size,size,src2,dst);
  499. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,tmpreg,src1));
  500. end;
  501. end
  502. else
  503. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src2,src1));
  504. end;
  505. end;
  506. else
  507. list.concat(setoppostfix(
  508. taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
  509. ));
  510. end;
  511. maybeadjustresult(list,op,size,dst);
  512. end;
  513. procedure tcgarm.a_load_const_reg(list : TAsmList; size: tcgsize; a : aint;reg : tregister);
  514. var
  515. imm_shift : byte;
  516. l : tasmlabel;
  517. hr : treference;
  518. begin
  519. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  520. internalerror(2002090902);
  521. if is_shifter_const(a,imm_shift) then
  522. list.concat(taicpu.op_reg_const(A_MOV,reg,a))
  523. else if is_shifter_const(not(a),imm_shift) then
  524. list.concat(taicpu.op_reg_const(A_MVN,reg,not(a)))
  525. { loading of constants with mov and orr }
  526. else if (is_shifter_const(a-byte(a),imm_shift)) then
  527. begin
  528. list.concat(taicpu.op_reg_const(A_MOV,reg,a-byte(a)));
  529. list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,byte(a)));
  530. end
  531. else if (is_shifter_const(a-word(a),imm_shift)) and (is_shifter_const(word(a),imm_shift)) then
  532. begin
  533. list.concat(taicpu.op_reg_const(A_MOV,reg,a-word(a)));
  534. list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,word(a)));
  535. end
  536. else if (is_shifter_const(a-(dword(a) shl 8) shr 8,imm_shift)) and (is_shifter_const((dword(a) shl 8) shr 8,imm_shift)) then
  537. begin
  538. list.concat(taicpu.op_reg_const(A_MOV,reg,a-(dword(a) shl 8) shr 8));
  539. list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg,(dword(a) shl 8) shr 8));
  540. end
  541. else
  542. begin
  543. reference_reset(hr);
  544. current_asmdata.getjumplabel(l);
  545. cg.a_label(current_procinfo.aktlocaldata,l);
  546. hr.symboldata:=current_procinfo.aktlocaldata.last;
  547. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
  548. hr.symbol:=l;
  549. list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
  550. end;
  551. end;
  552. function tcgarm.handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
  553. var
  554. tmpreg : tregister;
  555. tmpref : treference;
  556. l : tasmlabel;
  557. begin
  558. tmpreg:=NR_NO;
  559. { Be sure to have a base register }
  560. if (ref.base=NR_NO) then
  561. begin
  562. if ref.shiftmode<>SM_None then
  563. internalerror(200308294);
  564. ref.base:=ref.index;
  565. ref.index:=NR_NO;
  566. end;
  567. { absolute symbols can't be handled directly, we've to store the symbol reference
  568. in the text segment and access it pc relative
  569. For now, we assume that references where base or index equals to PC are already
  570. relative, all other references are assumed to be absolute and thus they need
  571. to be handled extra.
  572. A proper solution would be to change refoptions to a set and store the information
  573. if the symbol is absolute or relative there.
  574. }
  575. if (assigned(ref.symbol) and
  576. not(is_pc(ref.base)) and
  577. not(is_pc(ref.index))
  578. ) or
  579. { [#xxx] isn't a valid address operand }
  580. ((ref.base=NR_NO) and (ref.index=NR_NO)) or
  581. (ref.offset<-4095) or
  582. (ref.offset>4095) or
  583. ((oppostfix in [PF_SB,PF_H,PF_SH]) and
  584. ((ref.offset<-255) or
  585. (ref.offset>255)
  586. )
  587. ) or
  588. ((op in [A_LDF,A_STF]) and
  589. ((ref.offset<-1020) or
  590. (ref.offset>1020) or
  591. { the usual pc relative symbol handling assumes possible offsets of +/- 4095 }
  592. assigned(ref.symbol)
  593. )
  594. ) then
  595. begin
  596. reference_reset(tmpref);
  597. { load symbol }
  598. tmpreg:=getintregister(list,OS_INT);
  599. if assigned(ref.symbol) then
  600. begin
  601. current_asmdata.getjumplabel(l);
  602. cg.a_label(current_procinfo.aktlocaldata,l);
  603. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  604. current_procinfo.aktlocaldata.concat(tai_const.create_sym_offset(ref.symbol,ref.offset));
  605. { load consts entry }
  606. tmpref.symbol:=l;
  607. tmpref.base:=NR_R15;
  608. list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
  609. { in case of LDF/STF, we got rid of the NR_R15 }
  610. if is_pc(ref.base) then
  611. ref.base:=NR_NO;
  612. if is_pc(ref.index) then
  613. ref.index:=NR_NO;
  614. end
  615. else
  616. a_load_const_reg(list,OS_ADDR,ref.offset,tmpreg);
  617. if (ref.base<>NR_NO) then
  618. begin
  619. if ref.index<>NR_NO then
  620. begin
  621. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  622. ref.base:=tmpreg;
  623. end
  624. else
  625. begin
  626. ref.index:=tmpreg;
  627. ref.shiftimm:=0;
  628. ref.signindex:=1;
  629. ref.shiftmode:=SM_None;
  630. end;
  631. end
  632. else
  633. ref.base:=tmpreg;
  634. ref.offset:=0;
  635. ref.symbol:=nil;
  636. end;
  637. if (ref.base<>NR_NO) and (ref.index<>NR_NO) and (ref.offset<>0) then
  638. begin
  639. if tmpreg<>NR_NO then
  640. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,tmpreg,tmpreg)
  641. else
  642. begin
  643. tmpreg:=getintregister(list,OS_ADDR);
  644. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,ref.base,tmpreg);
  645. ref.base:=tmpreg;
  646. end;
  647. ref.offset:=0;
  648. end;
  649. { floating point operations have only limited references
  650. we expect here, that a base is already set }
  651. if (op in [A_LDF,A_STF]) and (ref.index<>NR_NO) then
  652. begin
  653. if ref.shiftmode<>SM_none then
  654. internalerror(200309121);
  655. if tmpreg<>NR_NO then
  656. begin
  657. if ref.base=tmpreg then
  658. begin
  659. if ref.signindex<0 then
  660. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,tmpreg,ref.index))
  661. else
  662. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,tmpreg,ref.index));
  663. ref.index:=NR_NO;
  664. end
  665. else
  666. begin
  667. if ref.index<>tmpreg then
  668. internalerror(200403161);
  669. if ref.signindex<0 then
  670. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,ref.base,tmpreg))
  671. else
  672. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  673. ref.base:=tmpreg;
  674. ref.index:=NR_NO;
  675. end;
  676. end
  677. else
  678. begin
  679. tmpreg:=getintregister(list,OS_ADDR);
  680. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,ref.index));
  681. ref.base:=tmpreg;
  682. ref.index:=NR_NO;
  683. end;
  684. end;
  685. list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix));
  686. Result := ref;
  687. end;
  688. procedure tcgarm.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  689. var
  690. oppostfix:toppostfix;
  691. usedtmpref: treference;
  692. tmpreg : tregister;
  693. so : tshifterop;
  694. dir : integer;
  695. begin
  696. case ToSize of
  697. { signed integer registers }
  698. OS_8,
  699. OS_S8:
  700. oppostfix:=PF_B;
  701. OS_16,
  702. OS_S16:
  703. oppostfix:=PF_H;
  704. OS_32,
  705. OS_S32:
  706. oppostfix:=PF_None;
  707. else
  708. InternalError(200308295);
  709. end;
  710. if ref.alignment<>0 then
  711. begin
  712. if target_info.endian=endian_big then
  713. dir:=-1
  714. else
  715. dir:=1;
  716. case FromSize of
  717. OS_16,OS_S16:
  718. begin
  719. shifterop_reset(so);so.shiftmode:=SM_LSR;so.shiftimm:=8;
  720. tmpreg:=getintregister(list,OS_INT);
  721. usedtmpref:=ref;
  722. if target_info.endian=endian_big then
  723. inc(usedtmpref.offset,1);
  724. usedtmpref:=a_internal_load_reg_ref(list,OS_8,OS_8,reg,usedtmpref);
  725. inc(usedtmpref.offset,dir);
  726. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,tmpreg,reg,so));
  727. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  728. end;
  729. OS_32,OS_S32:
  730. begin
  731. shifterop_reset(so);so.shiftmode:=SM_LSR;so.shiftimm:=8;
  732. tmpreg:=getintregister(list,OS_INT);
  733. usedtmpref:=ref;
  734. if target_info.endian=endian_big then
  735. inc(usedtmpref.offset,3);
  736. usedtmpref:=a_internal_load_reg_ref(list,OS_8,OS_8,reg,usedtmpref);
  737. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,tmpreg,reg,so));
  738. inc(usedtmpref.offset,dir);
  739. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  740. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,tmpreg,tmpreg,so));
  741. inc(usedtmpref.offset,dir);
  742. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  743. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,tmpreg,tmpreg,so));
  744. inc(usedtmpref.offset,dir);
  745. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  746. end
  747. else
  748. handle_load_store(list,A_STR,oppostfix,reg,ref);
  749. end;
  750. end
  751. else
  752. handle_load_store(list,A_STR,oppostfix,reg,ref);
  753. end;
  754. procedure tcgarm.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);
  755. var
  756. oppostfix:toppostfix;
  757. usedtmpref: treference;
  758. tmpreg,tmpreg2,tmpreg3 : tregister;
  759. so : tshifterop;
  760. dir : integer;
  761. begin
  762. case FromSize of
  763. { signed integer registers }
  764. OS_8:
  765. oppostfix:=PF_B;
  766. OS_S8:
  767. oppostfix:=PF_SB;
  768. OS_16:
  769. oppostfix:=PF_H;
  770. OS_S16:
  771. oppostfix:=PF_SH;
  772. OS_32,
  773. OS_S32:
  774. oppostfix:=PF_None;
  775. else
  776. InternalError(200308297);
  777. end;
  778. if Ref.alignment<>0 then
  779. begin
  780. if target_info.endian=endian_big then
  781. dir:=-1
  782. else
  783. dir:=1;
  784. case FromSize of
  785. OS_16,OS_S16:
  786. begin
  787. { only complicated references need an extra loadaddr }
  788. if assigned(ref.symbol) or
  789. (ref.index<>NR_NO) or
  790. (ref.offset<-4095) or
  791. (ref.offset>4094) or
  792. { sometimes the compiler reused registers }
  793. (reg=ref.index) or
  794. (reg=ref.base) then
  795. begin
  796. tmpreg3:=getintregister(list,OS_INT);
  797. a_loadaddr_ref_reg(list,ref,tmpreg3);
  798. reference_reset_base(usedtmpref,tmpreg3,0);
  799. end
  800. else
  801. usedtmpref:=ref;
  802. if target_info.endian=endian_big then
  803. inc(usedtmpref.offset,1);
  804. shifterop_reset(so);so.shiftmode:=SM_LSL;so.shiftimm:=8;
  805. tmpreg:=getintregister(list,OS_INT);
  806. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  807. inc(usedtmpref.offset,dir);
  808. tmpreg2:=getintregister(list,OS_INT);
  809. if FromSize=OS_16 then
  810. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg2)
  811. else
  812. a_internal_load_ref_reg(list,OS_S8,OS_S8,usedtmpref,tmpreg2);
  813. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,tmpreg,tmpreg2,so));
  814. end;
  815. OS_32,OS_S32:
  816. begin
  817. tmpreg:=getintregister(list,OS_INT);
  818. tmpreg2:=getintregister(list,OS_INT);
  819. { only complicated references need an extra loadaddr }
  820. if assigned(ref.symbol) or
  821. (ref.index<>NR_NO) or
  822. (ref.offset<-4095) or
  823. (ref.offset>4092) or
  824. { sometimes the compiler reused registers }
  825. (reg=ref.index) or
  826. (reg=ref.base) then
  827. begin
  828. tmpreg3:=getintregister(list,OS_INT);
  829. a_loadaddr_ref_reg(list,ref,tmpreg3);
  830. reference_reset_base(usedtmpref,tmpreg3,0);
  831. end
  832. else
  833. usedtmpref:=ref;
  834. if target_info.endian=endian_big then
  835. inc(usedtmpref.offset,3);
  836. shifterop_reset(so);so.shiftmode:=SM_LSL;so.shiftimm:=8;
  837. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  838. inc(usedtmpref.offset,dir);
  839. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  840. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,tmpreg2,reg,tmpreg,so));
  841. inc(usedtmpref.offset,dir);
  842. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  843. so.shiftimm:=16;
  844. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,tmpreg,tmpreg2,reg,so));
  845. inc(usedtmpref.offset,dir);
  846. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg2);
  847. so.shiftimm:=24;
  848. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,tmpreg,tmpreg2,so));
  849. end
  850. else
  851. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  852. end;
  853. end
  854. else
  855. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  856. if (fromsize=OS_S8) and (tosize = OS_16) then
  857. a_load_reg_reg(list,OS_16,OS_32,reg,reg);
  858. end;
  859. function tcgarm.a_internal_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference):treference;
  860. var
  861. oppostfix:toppostfix;
  862. begin
  863. case ToSize of
  864. { signed integer registers }
  865. OS_8,
  866. OS_S8:
  867. oppostfix:=PF_B;
  868. OS_16,
  869. OS_S16:
  870. oppostfix:=PF_H;
  871. OS_32,
  872. OS_S32:
  873. oppostfix:=PF_None;
  874. else
  875. InternalError(2003082910);
  876. end;
  877. result:=handle_load_store(list,A_STR,oppostfix,reg,ref);
  878. end;
  879. function tcgarm.a_internal_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister):treference;
  880. var
  881. oppostfix:toppostfix;
  882. begin
  883. case FromSize of
  884. { signed integer registers }
  885. OS_8:
  886. oppostfix:=PF_B;
  887. OS_S8:
  888. oppostfix:=PF_SB;
  889. OS_16:
  890. oppostfix:=PF_H;
  891. OS_S16:
  892. oppostfix:=PF_SH;
  893. OS_32,
  894. OS_S32:
  895. oppostfix:=PF_None;
  896. else
  897. InternalError(200308291);
  898. end;
  899. result:=handle_load_store(list,A_LDR,oppostfix,reg,ref);
  900. end;
  901. procedure tcgarm.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  902. var
  903. so : tshifterop;
  904. procedure do_shift(shiftmode : tshiftmode; shiftimm : byte; reg : tregister);
  905. begin
  906. so.shiftmode:=shiftmode;
  907. so.shiftimm:=shiftimm;
  908. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg,so));
  909. end;
  910. var
  911. instr: taicpu;
  912. conv_done: boolean;
  913. begin
  914. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) then
  915. internalerror(2002090901);
  916. conv_done:=false;
  917. if tosize<>fromsize then
  918. begin
  919. shifterop_reset(so);
  920. conv_done:=true;
  921. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  922. fromsize:=tosize;
  923. case fromsize of
  924. OS_8:
  925. list.concat(taicpu.op_reg_reg_const(A_AND,reg2,reg1,$ff));
  926. OS_S8:
  927. begin
  928. do_shift(SM_LSL,24,reg1);
  929. if tosize=OS_16 then
  930. begin
  931. do_shift(SM_ASR,8,reg2);
  932. do_shift(SM_LSR,16,reg2);
  933. end
  934. else
  935. do_shift(SM_ASR,24,reg2);
  936. end;
  937. OS_16:
  938. begin
  939. do_shift(SM_LSL,16,reg1);
  940. do_shift(SM_LSR,16,reg2);
  941. end;
  942. OS_S16:
  943. begin
  944. do_shift(SM_LSL,16,reg1);
  945. do_shift(SM_ASR,16,reg2)
  946. end;
  947. else
  948. conv_done:=false;
  949. end;
  950. end;
  951. if not conv_done and (reg1<>reg2) then
  952. begin
  953. { same size, only a register mov required }
  954. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  955. list.Concat(instr);
  956. { Notify the register allocator that we have written a move instruction so
  957. it can try to eliminate it. }
  958. add_move_instruction(instr);
  959. end;
  960. end;
  961. procedure tcgarm.a_paramfpu_ref(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);
  962. var
  963. href,href2 : treference;
  964. hloc : pcgparalocation;
  965. begin
  966. href:=ref;
  967. hloc:=paraloc.location;
  968. while assigned(hloc) do
  969. begin
  970. case hloc^.loc of
  971. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  972. a_loadfpu_ref_reg(list,size,size,ref,hloc^.register);
  973. LOC_REGISTER :
  974. case hloc^.size of
  975. OS_F32:
  976. a_load_ref_reg(list,OS_32,OS_32,href,hloc^.register);
  977. OS_64,
  978. OS_F64:
  979. cg64.a_param64_ref(list,href,paraloc);
  980. else
  981. a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register);
  982. end;
  983. LOC_REFERENCE :
  984. begin
  985. reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset);
  986. { concatcopy should choose the best way to copy the data }
  987. g_concatcopy(list,href,href2,tcgsize2size[size]);
  988. end;
  989. else
  990. internalerror(200408241);
  991. end;
  992. inc(href.offset,tcgsize2size[hloc^.size]);
  993. hloc:=hloc^.next;
  994. end;
  995. end;
  996. procedure tcgarm.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  997. begin
  998. list.concat(setoppostfix(taicpu.op_reg_reg(A_MVF,reg2,reg1),cgsize2fpuoppostfix[tosize]));
  999. end;
  1000. procedure tcgarm.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1001. var
  1002. oppostfix:toppostfix;
  1003. begin
  1004. case tosize of
  1005. OS_32,
  1006. OS_F32:
  1007. oppostfix:=PF_S;
  1008. OS_64,
  1009. OS_F64:
  1010. oppostfix:=PF_D;
  1011. OS_F80:
  1012. oppostfix:=PF_E;
  1013. else
  1014. InternalError(200309021);
  1015. end;
  1016. handle_load_store(list,A_LDF,oppostfix,reg,ref);
  1017. end;
  1018. procedure tcgarm.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1019. var
  1020. oppostfix:toppostfix;
  1021. begin
  1022. case tosize of
  1023. OS_F32:
  1024. oppostfix:=PF_S;
  1025. OS_F64:
  1026. oppostfix:=PF_D;
  1027. OS_F80:
  1028. oppostfix:=PF_E;
  1029. else
  1030. InternalError(200309022);
  1031. end;
  1032. handle_load_store(list,A_STF,oppostfix,reg,ref);
  1033. end;
  1034. { comparison operations }
  1035. procedure tcgarm.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  1036. l : tasmlabel);
  1037. var
  1038. tmpreg : tregister;
  1039. b : byte;
  1040. begin
  1041. if is_shifter_const(a,b) then
  1042. list.concat(taicpu.op_reg_const(A_CMP,reg,a))
  1043. { CMN reg,0 and CMN reg,$80000000 are different from CMP reg,$ffffffff
  1044. and CMP reg,$7fffffff regarding the flags according to the ARM manual }
  1045. else if (a<>$7fffffff) and (a<>-1) and is_shifter_const(-a,b) then
  1046. list.concat(taicpu.op_reg_const(A_CMN,reg,-a))
  1047. else
  1048. begin
  1049. tmpreg:=getintregister(list,size);
  1050. a_load_const_reg(list,size,a,tmpreg);
  1051. list.concat(taicpu.op_reg_reg(A_CMP,reg,tmpreg));
  1052. end;
  1053. a_jmp_cond(list,cmp_op,l);
  1054. end;
  1055. procedure tcgarm.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1056. begin
  1057. list.concat(taicpu.op_reg_reg(A_CMP,reg2,reg1));
  1058. a_jmp_cond(list,cmp_op,l);
  1059. end;
  1060. procedure tcgarm.a_jmp_name(list : TAsmList;const s : string);
  1061. var
  1062. ai : taicpu;
  1063. begin
  1064. ai:=taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol(s));
  1065. ai.is_jmp:=true;
  1066. list.concat(ai);
  1067. end;
  1068. procedure tcgarm.a_jmp_always(list : TAsmList;l: tasmlabel);
  1069. var
  1070. ai : taicpu;
  1071. begin
  1072. ai:=taicpu.op_sym(A_B,l);
  1073. ai.is_jmp:=true;
  1074. list.concat(ai);
  1075. end;
  1076. procedure tcgarm.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1077. var
  1078. ai : taicpu;
  1079. begin
  1080. ai:=setcondition(taicpu.op_sym(A_B,l),flags_to_cond(f));
  1081. ai.is_jmp:=true;
  1082. list.concat(ai);
  1083. end;
  1084. procedure tcgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1085. begin
  1086. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f)));
  1087. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond(flags_to_cond(f))));
  1088. end;
  1089. procedure tcgarm.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1090. var
  1091. ref : treference;
  1092. shift : byte;
  1093. firstfloatreg,lastfloatreg,
  1094. r : byte;
  1095. regs : tcpuregisterset;
  1096. begin
  1097. LocalSize:=align(LocalSize,4);
  1098. if not(nostackframe) then
  1099. begin
  1100. firstfloatreg:=RS_NO;
  1101. { save floating point registers? }
  1102. for r:=RS_F0 to RS_F7 do
  1103. if r in rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall) then
  1104. begin
  1105. if firstfloatreg=RS_NO then
  1106. firstfloatreg:=r;
  1107. lastfloatreg:=r;
  1108. end;
  1109. a_reg_alloc(list,NR_STACK_POINTER_REG);
  1110. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1111. begin
  1112. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  1113. a_reg_alloc(list,NR_R12);
  1114. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
  1115. end;
  1116. { save int registers }
  1117. reference_reset(ref);
  1118. ref.index:=NR_STACK_POINTER_REG;
  1119. ref.addressmode:=AM_PREINDEXED;
  1120. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1121. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1122. regs:=regs+[RS_R11,RS_R12,RS_R14,RS_R15]
  1123. else
  1124. if (regs<>[]) or (pi_do_call in current_procinfo.flags) then
  1125. include(regs,RS_R14);
  1126. if regs<>[] then
  1127. list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,regs),PF_FD));
  1128. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1129. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_FRAME_POINTER_REG,NR_R12,4));
  1130. { allocate necessary stack size
  1131. not necessary according to Yury Sidorov
  1132. { don't use a_op_const_reg_reg here because we don't allow register allocations
  1133. in the entry/exit code }
  1134. if (target_info.system in [system_arm_wince]) and
  1135. (localsize>=winstackpagesize) then
  1136. begin
  1137. if localsize div winstackpagesize<=5 then
  1138. begin
  1139. if is_shifter_const(localsize,shift) then
  1140. list.concat(Taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,localsize))
  1141. else
  1142. begin
  1143. a_load_const_reg(list,OS_ADDR,localsize,NR_R12);
  1144. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  1145. end;
  1146. for i:=1 to localsize div winstackpagesize do
  1147. begin
  1148. if localsize-i*winstackpagesize<4096 then
  1149. reference_reset_base(href,NR_STACK_POINTER_REG,-(localsize-i*winstackpagesize))
  1150. else
  1151. begin
  1152. a_load_const_reg(list,OS_ADDR,-(localsize-i*winstackpagesize),NR_R12);
  1153. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1154. href.index:=NR_R12;
  1155. end;
  1156. { the data stored doesn't matter }
  1157. list.concat(Taicpu.op_reg_ref(A_STR,NR_R0,href));
  1158. end;
  1159. a_reg_dealloc(list,NR_R12);
  1160. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1161. { the data stored doesn't matter }
  1162. list.concat(Taicpu.op_reg_ref(A_STR,NR_R0,href));
  1163. end
  1164. else
  1165. begin
  1166. current_asmdata.getjumplabel(again);
  1167. list.concat(Taicpu.op_reg_const(A_MOV,NR_R12,localsize div winstackpagesize));
  1168. a_label(list,again);
  1169. { always shifterop }
  1170. list.concat(Taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,winstackpagesize));
  1171. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1172. { the data stored doesn't matter }
  1173. list.concat(Taicpu.op_reg_ref(A_STR,NR_R0,href));
  1174. list.concat(Taicpu.op_reg_reg_const(A_SUB,NR_R12,NR_R12,1));
  1175. a_jmp_cond(list,OC_NE,again);
  1176. if is_shifter_const(localsize mod winstackpagesize,shift) then
  1177. list.concat(Taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,localsize mod winstackpagesize))
  1178. else
  1179. begin
  1180. a_load_const_reg(list,OS_ADDR,localsize mod winstackpagesize,NR_R12);
  1181. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  1182. end;
  1183. a_reg_dealloc(list,NR_R12);
  1184. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1185. { the data stored doesn't matter }
  1186. list.concat(Taicpu.op_reg_ref(A_STR,NR_R0,href));
  1187. end
  1188. end
  1189. else
  1190. }
  1191. if LocalSize<>0 then
  1192. if not(is_shifter_const(localsize,shift)) then
  1193. begin
  1194. if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  1195. a_reg_alloc(list,NR_R12);
  1196. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  1197. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  1198. a_reg_dealloc(list,NR_R12);
  1199. end
  1200. else
  1201. begin
  1202. a_reg_dealloc(list,NR_R12);
  1203. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
  1204. end;
  1205. if firstfloatreg<>RS_NO then
  1206. begin
  1207. reference_reset(ref);
  1208. if tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023 then
  1209. begin
  1210. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  1211. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  1212. ref.base:=NR_R12;
  1213. end
  1214. else
  1215. begin
  1216. ref.base:=current_procinfo.framepointer;
  1217. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  1218. end;
  1219. list.concat(taicpu.op_reg_const_ref(A_SFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  1220. lastfloatreg-firstfloatreg+1,ref));
  1221. end;
  1222. end;
  1223. end;
  1224. procedure tcgarm.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1225. var
  1226. ref : treference;
  1227. firstfloatreg,lastfloatreg,
  1228. r : byte;
  1229. shift : byte;
  1230. regs : tcpuregisterset;
  1231. LocalSize : longint;
  1232. begin
  1233. if not(nostackframe) then
  1234. begin
  1235. { restore floating point register }
  1236. firstfloatreg:=RS_NO;
  1237. { save floating point registers? }
  1238. for r:=RS_F0 to RS_F7 do
  1239. if r in rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall) then
  1240. begin
  1241. if firstfloatreg=RS_NO then
  1242. firstfloatreg:=r;
  1243. lastfloatreg:=r;
  1244. end;
  1245. if firstfloatreg<>RS_NO then
  1246. begin
  1247. reference_reset(ref);
  1248. if tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023 then
  1249. begin
  1250. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  1251. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  1252. ref.base:=NR_R12;
  1253. end
  1254. else
  1255. begin
  1256. ref.base:=current_procinfo.framepointer;
  1257. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  1258. end;
  1259. list.concat(taicpu.op_reg_const_ref(A_LFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  1260. lastfloatreg-firstfloatreg+1,ref));
  1261. end;
  1262. if (current_procinfo.framepointer=NR_STACK_POINTER_REG) then
  1263. begin
  1264. LocalSize:=current_procinfo.calc_stackframe_size;
  1265. if LocalSize<>0 then
  1266. if not(is_shifter_const(LocalSize,shift)) then
  1267. begin
  1268. a_reg_alloc(list,NR_R12);
  1269. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  1270. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  1271. a_reg_dealloc(list,NR_R12);
  1272. end
  1273. else
  1274. begin
  1275. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
  1276. end;
  1277. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1278. if (pi_do_call in current_procinfo.flags) or (regs<>[]) then
  1279. begin
  1280. exclude(regs,RS_R14);
  1281. include(regs,RS_R15);
  1282. end;
  1283. if regs=[] then
  1284. list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14))
  1285. else
  1286. begin
  1287. reference_reset(ref);
  1288. ref.index:=NR_STACK_POINTER_REG;
  1289. ref.addressmode:=AM_PREINDEXED;
  1290. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,regs),PF_FD));
  1291. end;
  1292. end
  1293. else
  1294. begin
  1295. { restore int registers and return }
  1296. reference_reset(ref);
  1297. ref.index:=NR_FRAME_POINTER_REG;
  1298. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall)+[RS_R11,RS_R13,RS_R15]),PF_EA));
  1299. end;
  1300. end
  1301. else
  1302. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14));
  1303. end;
  1304. procedure tcgarm.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1305. var
  1306. b : byte;
  1307. tmpref : treference;
  1308. instr : taicpu;
  1309. begin
  1310. if ref.addressmode<>AM_OFFSET then
  1311. internalerror(200309071);
  1312. tmpref:=ref;
  1313. { Be sure to have a base register }
  1314. if (tmpref.base=NR_NO) then
  1315. begin
  1316. if tmpref.shiftmode<>SM_None then
  1317. internalerror(200308294);
  1318. if tmpref.signindex<0 then
  1319. internalerror(200312023);
  1320. tmpref.base:=tmpref.index;
  1321. tmpref.index:=NR_NO;
  1322. end;
  1323. if assigned(tmpref.symbol) or
  1324. not((is_shifter_const(tmpref.offset,b)) or
  1325. (is_shifter_const(-tmpref.offset,b))
  1326. ) then
  1327. fixref(list,tmpref);
  1328. { expect a base here if there is an index }
  1329. if (tmpref.base=NR_NO) and (tmpref.index<>NR_NO) then
  1330. internalerror(200312022);
  1331. if tmpref.index<>NR_NO then
  1332. begin
  1333. if tmpref.shiftmode<>SM_None then
  1334. internalerror(200312021);
  1335. if tmpref.signindex<0 then
  1336. a_op_reg_reg_reg(list,OP_SUB,OS_ADDR,tmpref.base,tmpref.index,r)
  1337. else
  1338. a_op_reg_reg_reg(list,OP_ADD,OS_ADDR,tmpref.base,tmpref.index,r);
  1339. if tmpref.offset<>0 then
  1340. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,r,r);
  1341. end
  1342. else
  1343. begin
  1344. if tmpref.base=NR_NO then
  1345. a_load_const_reg(list,OS_ADDR,tmpref.offset,r)
  1346. else
  1347. if tmpref.offset<>0 then
  1348. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,tmpref.base,r)
  1349. else
  1350. begin
  1351. instr:=taicpu.op_reg_reg(A_MOV,r,tmpref.base);
  1352. list.concat(instr);
  1353. add_move_instruction(instr);
  1354. end;
  1355. end;
  1356. end;
  1357. procedure tcgarm.fixref(list : TAsmList;var ref : treference);
  1358. var
  1359. tmpreg : tregister;
  1360. tmpref : treference;
  1361. l : tasmlabel;
  1362. begin
  1363. { absolute symbols can't be handled directly, we've to store the symbol reference
  1364. in the text segment and access it pc relative
  1365. For now, we assume that references where base or index equals to PC are already
  1366. relative, all other references are assumed to be absolute and thus they need
  1367. to be handled extra.
  1368. A proper solution would be to change refoptions to a set and store the information
  1369. if the symbol is absolute or relative there.
  1370. }
  1371. { create consts entry }
  1372. reference_reset(tmpref);
  1373. current_asmdata.getjumplabel(l);
  1374. cg.a_label(current_procinfo.aktlocaldata,l);
  1375. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  1376. if assigned(ref.symbol) then
  1377. current_procinfo.aktlocaldata.concat(tai_const.create_sym_offset(ref.symbol,ref.offset))
  1378. else
  1379. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ref.offset));
  1380. { load consts entry }
  1381. tmpreg:=getintregister(list,OS_INT);
  1382. tmpref.symbol:=l;
  1383. tmpref.base:=NR_PC;
  1384. list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
  1385. if (ref.base<>NR_NO) then
  1386. begin
  1387. if ref.index<>NR_NO then
  1388. begin
  1389. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  1390. ref.base:=tmpreg;
  1391. end
  1392. else
  1393. if ref.base<>NR_PC then
  1394. begin
  1395. ref.index:=tmpreg;
  1396. ref.shiftimm:=0;
  1397. ref.signindex:=1;
  1398. ref.shiftmode:=SM_None;
  1399. end
  1400. else
  1401. ref.base:=tmpreg;
  1402. end
  1403. else
  1404. ref.base:=tmpreg;
  1405. ref.offset:=0;
  1406. ref.symbol:=nil;
  1407. end;
  1408. procedure tcgarm.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  1409. var
  1410. paraloc1,paraloc2,paraloc3 : TCGPara;
  1411. begin
  1412. paraloc1.init;
  1413. paraloc2.init;
  1414. paraloc3.init;
  1415. paramanager.getintparaloc(pocall_default,1,paraloc1);
  1416. paramanager.getintparaloc(pocall_default,2,paraloc2);
  1417. paramanager.getintparaloc(pocall_default,3,paraloc3);
  1418. paramanager.allocparaloc(list,paraloc3);
  1419. a_param_const(list,OS_INT,len,paraloc3);
  1420. paramanager.allocparaloc(list,paraloc2);
  1421. a_paramaddr_ref(list,dest,paraloc2);
  1422. paramanager.allocparaloc(list,paraloc2);
  1423. a_paramaddr_ref(list,source,paraloc1);
  1424. paramanager.freeparaloc(list,paraloc3);
  1425. paramanager.freeparaloc(list,paraloc2);
  1426. paramanager.freeparaloc(list,paraloc1);
  1427. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1428. alloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  1429. a_call_name(list,'FPC_MOVE');
  1430. dealloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  1431. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1432. paraloc3.done;
  1433. paraloc2.done;
  1434. paraloc1.done;
  1435. end;
  1436. procedure tcgarm.g_concatcopy_internal(list : TAsmList;const source,dest : treference;len : aint;aligned : boolean);
  1437. const
  1438. maxtmpreg=10;{roozbeh: can be reduced to 8 or lower if might conflick with reserved ones,also +2 is used becouse of regs required for referencing}
  1439. var
  1440. srcref,dstref,usedtmpref,usedtmpref2:treference;
  1441. srcreg,destreg,countreg,r,tmpreg:tregister;
  1442. helpsize:aint;
  1443. copysize:byte;
  1444. cgsize:Tcgsize;
  1445. tmpregisters:array[1..maxtmpreg] of tregister;
  1446. tmpregi,tmpregi2:byte;
  1447. { will never be called with count<=4 }
  1448. procedure genloop(count : aword;size : byte);
  1449. const
  1450. size2opsize : array[1..4] of tcgsize = (OS_8,OS_16,OS_NO,OS_32);
  1451. var
  1452. l : tasmlabel;
  1453. begin
  1454. current_asmdata.getjumplabel(l);
  1455. if count<size then size:=1;
  1456. a_load_const_reg(list,OS_INT,count div size,countreg);
  1457. cg.a_label(list,l);
  1458. srcref.addressmode:=AM_POSTINDEXED;
  1459. dstref.addressmode:=AM_POSTINDEXED;
  1460. srcref.offset:=size;
  1461. dstref.offset:=size;
  1462. r:=getintregister(list,size2opsize[size]);
  1463. a_load_ref_reg(list,size2opsize[size],size2opsize[size],srcref,r);
  1464. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,countreg,countreg,1),PF_S));
  1465. a_load_reg_ref(list,size2opsize[size],size2opsize[size],r,dstref);
  1466. a_jmp_flags(list,F_NE,l);
  1467. srcref.offset:=1;
  1468. dstref.offset:=1;
  1469. case count mod size of
  1470. 1:
  1471. begin
  1472. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1473. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1474. end;
  1475. 2:
  1476. if aligned then
  1477. begin
  1478. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  1479. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  1480. end
  1481. else
  1482. begin
  1483. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1484. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1485. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1486. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1487. end;
  1488. 3:
  1489. if aligned then
  1490. begin
  1491. srcref.offset:=2;
  1492. dstref.offset:=2;
  1493. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  1494. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  1495. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1496. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1497. end
  1498. else
  1499. begin
  1500. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1501. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1502. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1503. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1504. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1505. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1506. end;
  1507. end;
  1508. { keep the registers alive }
  1509. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1510. list.concat(taicpu.op_reg_reg(A_MOV,srcreg,srcreg));
  1511. list.concat(taicpu.op_reg_reg(A_MOV,destreg,destreg));
  1512. end;
  1513. begin
  1514. if len=0 then
  1515. exit;
  1516. helpsize:=12+maxtmpreg*4;//52 with maxtmpreg=10
  1517. dstref:=dest;
  1518. srcref:=source;
  1519. if cs_opt_size in current_settings.optimizerswitches then
  1520. helpsize:=8;
  1521. if (len<=helpsize) and aligned then
  1522. begin
  1523. tmpregi:=0;
  1524. srcreg:=getintregister(list,OS_ADDR);
  1525. { explicit pc relative addressing, could be
  1526. e.g. a floating point constant }
  1527. if source.base=NR_PC then
  1528. begin
  1529. { ... then we don't need a loadaddr }
  1530. srcref:=source;
  1531. end
  1532. else
  1533. begin
  1534. a_loadaddr_ref_reg(list,source,srcreg);
  1535. reference_reset_base(srcref,srcreg,0);
  1536. end;
  1537. while (len div 4 <> 0) and (tmpregi<maxtmpreg) do
  1538. begin
  1539. inc(tmpregi);
  1540. tmpregisters[tmpregi]:=getintregister(list,OS_32);
  1541. a_load_ref_reg(list,OS_32,OS_32,srcref,tmpregisters[tmpregi]);
  1542. inc(srcref.offset,4);
  1543. dec(len,4);
  1544. end;
  1545. destreg:=getintregister(list,OS_ADDR);
  1546. a_loadaddr_ref_reg(list,dest,destreg);
  1547. reference_reset_base(dstref,destreg,0);
  1548. tmpregi2:=1;
  1549. while (tmpregi2<=tmpregi) do
  1550. begin
  1551. a_load_reg_ref(list,OS_32,OS_32,tmpregisters[tmpregi2],dstref);
  1552. inc(dstref.offset,4);
  1553. inc(tmpregi2);
  1554. end;
  1555. copysize:=4;
  1556. cgsize:=OS_32;
  1557. while len<>0 do
  1558. begin
  1559. if len<2 then
  1560. begin
  1561. copysize:=1;
  1562. cgsize:=OS_8;
  1563. end
  1564. else if len<4 then
  1565. begin
  1566. copysize:=2;
  1567. cgsize:=OS_16;
  1568. end;
  1569. dec(len,copysize);
  1570. r:=getintregister(list,cgsize);
  1571. a_load_ref_reg(list,cgsize,cgsize,srcref,r);
  1572. a_load_reg_ref(list,cgsize,cgsize,r,dstref);
  1573. inc(srcref.offset,copysize);
  1574. inc(dstref.offset,copysize);
  1575. end;{end of while}
  1576. end
  1577. else
  1578. begin
  1579. cgsize:=OS_32;
  1580. if (len<=4) then{len<=4 and not aligned}
  1581. begin
  1582. r:=getintregister(list,cgsize);
  1583. usedtmpref:=a_internal_load_ref_reg(list,OS_8,OS_8,srcref,r);
  1584. if Len=1 then
  1585. a_load_reg_ref(list,OS_8,OS_8,r,dstref)
  1586. else
  1587. begin
  1588. tmpreg:=getintregister(list,cgsize);
  1589. usedtmpref2:=a_internal_load_reg_ref(list,OS_8,OS_8,r,dstref);
  1590. inc(usedtmpref.offset,1);
  1591. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  1592. inc(usedtmpref2.offset,1);
  1593. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  1594. if len>2 then
  1595. begin
  1596. inc(usedtmpref.offset,1);
  1597. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  1598. inc(usedtmpref2.offset,1);
  1599. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  1600. if len>3 then
  1601. begin
  1602. inc(usedtmpref.offset,1);
  1603. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  1604. inc(usedtmpref2.offset,1);
  1605. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  1606. end;
  1607. end;
  1608. end;
  1609. end{end of if len<=4}
  1610. else
  1611. begin{unaligned & 4<len<helpsize **or** aligned/unaligned & len>helpsize}
  1612. destreg:=getintregister(list,OS_ADDR);
  1613. a_loadaddr_ref_reg(list,dest,destreg);
  1614. reference_reset_base(dstref,destreg,0);
  1615. srcreg:=getintregister(list,OS_ADDR);
  1616. a_loadaddr_ref_reg(list,source,srcreg);
  1617. reference_reset_base(srcref,srcreg,0);
  1618. countreg:=getintregister(list,OS_32);
  1619. // if cs_opt_size in current_settings.optimizerswitches then
  1620. { roozbeh : it seems loading 1 byte is faster becouse of caching/fetching(?) }
  1621. {if aligned then
  1622. genloop(len,4)
  1623. else}
  1624. genloop(len,1);
  1625. end;
  1626. end;
  1627. end;
  1628. procedure tcgarm.g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : aint);
  1629. begin
  1630. g_concatcopy_internal(list,source,dest,len,false);
  1631. end;
  1632. procedure tcgarm.g_concatcopy(list : TAsmList;const source,dest : treference;len : aint);
  1633. begin
  1634. if (source.alignment in [1..3]) or
  1635. (dest.alignment in [1..3]) then
  1636. g_concatcopy_internal(list,source,dest,len,false)
  1637. else
  1638. g_concatcopy_internal(list,source,dest,len,true);
  1639. end;
  1640. procedure tcgarm.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1641. var
  1642. ovloc : tlocation;
  1643. begin
  1644. ovloc.loc:=LOC_VOID;
  1645. g_overflowCheck_loc(list,l,def,ovloc);
  1646. end;
  1647. procedure tcgarm.g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);
  1648. var
  1649. hl : tasmlabel;
  1650. ai:TAiCpu;
  1651. hflags : tresflags;
  1652. begin
  1653. if not(cs_check_overflow in current_settings.localswitches) then
  1654. exit;
  1655. current_asmdata.getjumplabel(hl);
  1656. case ovloc.loc of
  1657. LOC_VOID:
  1658. begin
  1659. ai:=taicpu.op_sym(A_B,hl);
  1660. ai.is_jmp:=true;
  1661. if not((def.typ=pointerdef) or
  1662. ((def.typ=orddef) and
  1663. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,bool8bit,bool16bit,bool32bit]))) then
  1664. ai.SetCondition(C_VC)
  1665. else
  1666. if TAiCpu(List.Last).opcode in [A_RSB,A_RSC,A_SBC,A_SUB] then
  1667. ai.SetCondition(C_CS)
  1668. else
  1669. ai.SetCondition(C_CC);
  1670. list.concat(ai);
  1671. end;
  1672. LOC_FLAGS:
  1673. begin
  1674. hflags:=ovloc.resflags;
  1675. inverse_flags(hflags);
  1676. cg.a_jmp_flags(list,hflags,hl);
  1677. end;
  1678. else
  1679. internalerror(200409281);
  1680. end;
  1681. a_call_name(list,'FPC_OVERFLOW');
  1682. a_label(list,hl);
  1683. end;
  1684. procedure tcgarm.g_save_registers(list : TAsmList);
  1685. begin
  1686. { this work is done in g_proc_entry }
  1687. end;
  1688. procedure tcgarm.g_restore_registers(list : TAsmList);
  1689. begin
  1690. { this work is done in g_proc_exit }
  1691. end;
  1692. procedure tcgarm.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1693. var
  1694. ai : taicpu;
  1695. begin
  1696. ai:=Taicpu.Op_sym(A_B,l);
  1697. ai.SetCondition(OpCmp2AsmCond[cond]);
  1698. ai.is_jmp:=true;
  1699. list.concat(ai);
  1700. end;
  1701. procedure tcgarm.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1702. procedure loadvmttor12;
  1703. var
  1704. href : treference;
  1705. begin
  1706. reference_reset_base(href,NR_R0,0);
  1707. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R12);
  1708. end;
  1709. procedure op_onr12methodaddr;
  1710. var
  1711. href : treference;
  1712. begin
  1713. if (procdef.extnumber=$ffff) then
  1714. Internalerror(200006139);
  1715. { call/jmp vmtoffs(%eax) ; method offs }
  1716. reference_reset_base(href,NR_R12,procdef._class.vmtmethodoffset(procdef.extnumber));
  1717. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R12);
  1718. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R12));
  1719. end;
  1720. var
  1721. make_global : boolean;
  1722. begin
  1723. if not(procdef.proctypeoption in [potype_function,potype_procedure]) then
  1724. Internalerror(200006137);
  1725. if not assigned(procdef._class) or
  1726. (procdef.procoptions*[po_classmethod, po_staticmethod,
  1727. po_methodpointer, po_interrupt, po_iocheck]<>[]) then
  1728. Internalerror(200006138);
  1729. if procdef.owner.symtabletype<>ObjectSymtable then
  1730. Internalerror(200109191);
  1731. make_global:=false;
  1732. if (not current_module.is_unit) or
  1733. create_smartlink or
  1734. (procdef.owner.defowner.owner.symtabletype=globalsymtable) then
  1735. make_global:=true;
  1736. if make_global then
  1737. list.concat(Tai_symbol.Createname_global(labelname,AT_FUNCTION,0))
  1738. else
  1739. list.concat(Tai_symbol.Createname(labelname,AT_FUNCTION,0));
  1740. { set param1 interface to self }
  1741. g_adjust_self_value(list,procdef,ioffset);
  1742. { case 4 }
  1743. if po_virtualmethod in procdef.procoptions then
  1744. begin
  1745. loadvmttor12;
  1746. op_onr12methodaddr;
  1747. end
  1748. { case 0 }
  1749. else
  1750. list.concat(taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol(procdef.mangledname)));
  1751. list.concat(Tai_symbol_end.Createname(labelname));
  1752. end;
  1753. procedure tcgarm.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
  1754. const
  1755. overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NOT,OP_NEG];
  1756. begin
  1757. if (op in overflowops) and
  1758. (size in [OS_8,OS_S8,OS_16,OS_S16]) then
  1759. a_load_reg_reg(list,OS_32,size,dst,dst);
  1760. end;
  1761. procedure tcg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1762. begin
  1763. case op of
  1764. OP_NEG:
  1765. begin
  1766. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0),PF_S));
  1767. list.concat(taicpu.op_reg_reg_const(A_RSC,regdst.reghi,regsrc.reghi,0));
  1768. end;
  1769. OP_NOT:
  1770. begin
  1771. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reglo,regdst.reglo);
  1772. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reghi,regdst.reghi);
  1773. end;
  1774. else
  1775. a_op64_reg_reg_reg(list,op,size,regsrc,regdst,regdst);
  1776. end;
  1777. end;
  1778. procedure tcg64farm.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1779. begin
  1780. a_op64_const_reg_reg(list,op,size,value,reg,reg);
  1781. end;
  1782. procedure tcg64farm.a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);
  1783. var
  1784. ovloc : tlocation;
  1785. begin
  1786. a_op64_const_reg_reg_checkoverflow(list,op,size,value,regsrc,regdst,false,ovloc);
  1787. end;
  1788. procedure tcg64farm.a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
  1789. var
  1790. ovloc : tlocation;
  1791. begin
  1792. a_op64_reg_reg_reg_checkoverflow(list,op,size,regsrc1,regsrc2,regdst,false,ovloc);
  1793. end;
  1794. procedure tcg64farm.a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  1795. var
  1796. tmpreg : tregister;
  1797. b : byte;
  1798. begin
  1799. ovloc.loc:=LOC_VOID;
  1800. case op of
  1801. OP_NEG,
  1802. OP_NOT :
  1803. internalerror(200306017);
  1804. end;
  1805. if (setflags or tcgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
  1806. begin
  1807. case op of
  1808. OP_ADD:
  1809. begin
  1810. if is_shifter_const(lo(value),b) then
  1811. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,lo(value)),PF_S))
  1812. else
  1813. begin
  1814. tmpreg:=cg.getintregister(list,OS_32);
  1815. cg.a_load_const_reg(list,OS_32,lo(value),tmpreg);
  1816. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  1817. end;
  1818. if is_shifter_const(hi(value),b) then
  1819. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADC,regdst.reghi,regsrc.reghi,hi(value)),PF_S))
  1820. else
  1821. begin
  1822. tmpreg:=cg.getintregister(list,OS_32);
  1823. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  1824. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc.reghi,tmpreg),PF_S));
  1825. end;
  1826. end;
  1827. OP_SUB:
  1828. begin
  1829. if is_shifter_const(lo(value),b) then
  1830. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,lo(value)),PF_S))
  1831. else
  1832. begin
  1833. tmpreg:=cg.getintregister(list,OS_32);
  1834. cg.a_load_const_reg(list,OS_32,lo(value),tmpreg);
  1835. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  1836. end;
  1837. if is_shifter_const(hi(value),b) then
  1838. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SBC,regdst.reghi,regsrc.reghi,aint(hi(value))),PF_S))
  1839. else
  1840. begin
  1841. tmpreg:=cg.getintregister(list,OS_32);
  1842. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  1843. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc.reghi,tmpreg),PF_S));
  1844. end;
  1845. end;
  1846. else
  1847. internalerror(200502131);
  1848. end;
  1849. if size=OS_64 then
  1850. begin
  1851. { the arm has an weired opinion how flags for SUB/ADD are handled }
  1852. ovloc.loc:=LOC_FLAGS;
  1853. case op of
  1854. OP_ADD:
  1855. ovloc.resflags:=F_CS;
  1856. OP_SUB:
  1857. ovloc.resflags:=F_CC;
  1858. end;
  1859. end;
  1860. end
  1861. else
  1862. begin
  1863. case op of
  1864. OP_AND,OP_OR,OP_XOR:
  1865. begin
  1866. cg.a_op_const_reg_reg(list,op,OS_32,aint(lo(value)),regsrc.reglo,regdst.reglo);
  1867. cg.a_op_const_reg_reg(list,op,OS_32,aint(hi(value)),regsrc.reghi,regdst.reghi);
  1868. end;
  1869. OP_ADD:
  1870. begin
  1871. if is_shifter_const(aint(lo(value)),b) then
  1872. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S))
  1873. else
  1874. begin
  1875. tmpreg:=cg.getintregister(list,OS_32);
  1876. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  1877. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  1878. end;
  1879. if is_shifter_const(aint(hi(value)),b) then
  1880. list.concat(taicpu.op_reg_reg_const(A_ADC,regdst.reghi,regsrc.reghi,aint(hi(value))))
  1881. else
  1882. begin
  1883. tmpreg:=cg.getintregister(list,OS_32);
  1884. cg.a_load_const_reg(list,OS_32,aint(hi(value)),tmpreg);
  1885. list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc.reghi,tmpreg));
  1886. end;
  1887. end;
  1888. OP_SUB:
  1889. begin
  1890. if is_shifter_const(aint(lo(value)),b) then
  1891. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S))
  1892. else
  1893. begin
  1894. tmpreg:=cg.getintregister(list,OS_32);
  1895. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  1896. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  1897. end;
  1898. if is_shifter_const(aint(hi(value)),b) then
  1899. list.concat(taicpu.op_reg_reg_const(A_SBC,regdst.reghi,regsrc.reghi,aint(hi(value))))
  1900. else
  1901. begin
  1902. tmpreg:=cg.getintregister(list,OS_32);
  1903. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  1904. list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc.reghi,tmpreg));
  1905. end;
  1906. end;
  1907. else
  1908. internalerror(2003083101);
  1909. end;
  1910. end;
  1911. end;
  1912. procedure tcg64farm.a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  1913. begin
  1914. ovloc.loc:=LOC_VOID;
  1915. case op of
  1916. OP_NEG,
  1917. OP_NOT :
  1918. internalerror(200306017);
  1919. end;
  1920. if (setflags or tcgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
  1921. begin
  1922. case op of
  1923. OP_ADD:
  1924. begin
  1925. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S));
  1926. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi),PF_S));
  1927. end;
  1928. OP_SUB:
  1929. begin
  1930. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S));
  1931. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi),PF_S));
  1932. end;
  1933. else
  1934. internalerror(2003083101);
  1935. end;
  1936. if size=OS_64 then
  1937. begin
  1938. { the arm has an weired opinion how flags for SUB/ADD are handled }
  1939. ovloc.loc:=LOC_FLAGS;
  1940. case op of
  1941. OP_ADD:
  1942. ovloc.resflags:=F_CS;
  1943. OP_SUB:
  1944. ovloc.resflags:=F_CC;
  1945. end;
  1946. end;
  1947. end
  1948. else
  1949. begin
  1950. case op of
  1951. OP_AND,OP_OR,OP_XOR:
  1952. begin
  1953. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
  1954. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
  1955. end;
  1956. OP_ADD:
  1957. begin
  1958. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S));
  1959. list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  1960. end;
  1961. OP_SUB:
  1962. begin
  1963. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S));
  1964. list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi));
  1965. end;
  1966. else
  1967. internalerror(2003083101);
  1968. end;
  1969. end;
  1970. end;
  1971. begin
  1972. cg:=tcgarm.create;
  1973. cg64:=tcg64farm.create;
  1974. end.