popt386.pas 88 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1993-98 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. Interface
  20. Uses Aasm;
  21. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  22. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  23. Implementation
  24. Uses
  25. globtype,systems,
  26. globals,verbose,hcodegen,
  27. cpubase,cpuasm,DAOpt386;
  28. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  29. Begin
  30. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  31. RegUsedAfterInstruction := Reg in UsedRegs
  32. End;
  33. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  34. {First pass of peepholeoptimizations}
  35. Var
  36. l : longint;
  37. p ,hp1, hp2 : pai;
  38. {$ifdef foropt}
  39. hp3, hp4: pai;
  40. {$endif foropt}
  41. TmpBool1, TmpBool2: Boolean;
  42. TmpRef: PReference;
  43. UsedRegs, TmpUsedRegs: TRegSet;
  44. Procedure GetFinalDestination(hp: paicpu);
  45. {traces sucessive jumps to their final destination and sets it, e.g.
  46. je l1 je l3
  47. <code> <code>
  48. l1: becomes l1:
  49. je l2 je l3
  50. <code> <code>
  51. l2: l2:
  52. jmp l3 jmp l3}
  53. Var p1: pai;
  54. Function SkipLabels(hp: Pai): Pai;
  55. {skips all labels and returns the next "real" instruction; it is
  56. assumed that hp is of the type ait_label}
  57. Begin
  58. While assigned(hp^.next) and
  59. (pai(hp^.next)^.typ In SkipInstr + [ait_label]) Do
  60. hp := pai(hp^.next);
  61. If assigned(hp^.next)
  62. Then SkipLabels := pai(hp^.next)
  63. Else SkipLabels := hp;
  64. End;
  65. Begin
  66. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  67. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  68. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  69. Begin
  70. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  71. p1 := SkipLabels(p1);
  72. If (pai(p1)^.typ = ait_instruction) and
  73. (paicpu(p1)^.is_jmp) and
  74. (paicpu(p1)^.condition = hp^.condition) Then
  75. Begin
  76. GetFinalDestination(paicpu(p1));
  77. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  78. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  79. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  80. End;
  81. End;
  82. End;
  83. Function DoSubAddOpt(var p: Pai): Boolean;
  84. Begin
  85. DoSubAddOpt := False;
  86. If GetLastInstruction(p, hp1) And
  87. (hp1^.typ = ait_instruction) And
  88. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  89. Case Paicpu(hp1)^.opcode Of
  90. A_DEC:
  91. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  92. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  93. Begin
  94. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  95. AsmL^.Remove(hp1);
  96. Dispose(hp1, Done)
  97. End;
  98. A_SUB:
  99. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  100. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  101. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  102. Begin
  103. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  104. AsmL^.Remove(hp1);
  105. Dispose(hp1, Done)
  106. End;
  107. A_ADD:
  108. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  109. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  110. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  111. Begin
  112. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  113. AsmL^.Remove(hp1);
  114. Dispose(hp1, Done);
  115. If (Paicpu(p)^.oper[0].val = 0) Then
  116. Begin
  117. hp1 := Pai(p^.next);
  118. AsmL^.Remove(p);
  119. Dispose(p, Done);
  120. If Not GetLastInstruction(hp1, p) Then
  121. p := hp1;
  122. DoSubAddOpt := True;
  123. End
  124. End;
  125. End;
  126. End;
  127. Begin
  128. P := BlockStart;
  129. UsedRegs := [];
  130. While (P <> BlockEnd) Do
  131. Begin
  132. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  133. Case P^.Typ Of
  134. ait_instruction:
  135. Begin
  136. { Handle Jmp Optimizations }
  137. if Paicpu(p)^.is_jmp then
  138. begin
  139. {the following if-block removes all code between a jmp and the next label,
  140. because it can never be executed}
  141. If (paicpu(p)^.opcode = A_JMP) Then
  142. Begin
  143. While GetNextInstruction(p, hp1) and
  144. ((hp1^.typ <> ait_label) or
  145. { skip unused labels, they're not referenced anywhere }
  146. Not(Pai_Label(hp1)^.l^.is_used)) Do
  147. If (hp1^.typ <> ait_label) Then
  148. Begin
  149. AsmL^.Remove(hp1);
  150. Dispose(hp1, done);
  151. End;
  152. End;
  153. If GetNextInstruction(p, hp1) then
  154. Begin
  155. If (pai(hp1)^.typ=ait_instruction) and
  156. (paicpu(hp1)^.opcode=A_JMP) and
  157. GetNextInstruction(hp1, hp2) And
  158. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  159. Then
  160. Begin
  161. if paicpu(p)^.opcode=A_Jcc then
  162. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  163. else
  164. begin
  165. If (LabDif <> 0) Then
  166. GetFinalDestination(paicpu(p));
  167. p:=pai(p^.next);
  168. continue;
  169. end;
  170. Dec(pai_label(hp2)^.l^.refs);
  171. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  172. Inc(paicpu(p)^.oper[0].sym^.refs);
  173. asml^.remove(hp1);
  174. dispose(hp1,done);
  175. If (LabDif <> 0) Then
  176. GetFinalDestination(paicpu(p));
  177. end
  178. else
  179. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  180. Begin
  181. hp2:=pai(hp1^.next);
  182. asml^.remove(p);
  183. dispose(p,done);
  184. p:=hp2;
  185. continue;
  186. end
  187. Else
  188. If (LabDif <> 0) Then
  189. GetFinalDestination(paicpu(p));
  190. end
  191. end
  192. else
  193. { All other optimizes }
  194. begin
  195. For l := 0 to 2 Do
  196. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  197. With Paicpu(p)^.oper[l].ref^ Do
  198. Begin
  199. If (base = R_NO) And
  200. (index <> R_NO) And
  201. (scalefactor in [0,1])
  202. Then
  203. Begin
  204. base := index;
  205. index := R_NO
  206. End
  207. End;
  208. Case Paicpu(p)^.opcode Of
  209. A_AND:
  210. Begin
  211. If (Paicpu(p)^.oper[0].typ = top_const) And
  212. (Paicpu(p)^.oper[1].typ = top_reg) And
  213. GetNextInstruction(p, hp1) And
  214. (Pai(hp1)^.typ = ait_instruction) And
  215. (Paicpu(hp1)^.opcode = A_AND) And
  216. (Paicpu(hp1)^.oper[0].typ = top_const) And
  217. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  218. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  219. Then
  220. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  221. Begin
  222. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  223. AsmL^.Remove(hp1);
  224. Dispose(hp1, Done)
  225. End
  226. Else
  227. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  228. jump}
  229. If (Paicpu(p)^.oper[1].typ = top_reg) And
  230. GetNextInstruction(p, hp1) And
  231. (hp1^.typ = ait_instruction) And
  232. (Paicpu(hp1)^.is_jmp) and
  233. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  234. Paicpu(p)^.opcode := A_TEST;
  235. End;
  236. A_CMP:
  237. Begin
  238. If (Paicpu(p)^.oper[0].typ = top_const) And
  239. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  240. (Paicpu(p)^.oper[0].val = 0) Then
  241. {$ifdef foropt}
  242. If GetNextInstruction(p, hp1) And
  243. (hp1^.typ = ait_instruction) And
  244. (Paicpu(hp1)^.is_jmp) and
  245. (paicpu(hp1)^.opcode=A_Jcc) and
  246. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  247. GetNextInstruction(hp1,hp2) and
  248. (hp2^.typ = ait_instruction) and
  249. (Paicpu(hp2)^.opcode = A_DEC) And
  250. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  251. GetNextInstruction(hp2, hp3) And
  252. (hp3^.typ = ait_instruction) and
  253. (Paicpu(hp3)^.is_jmp) and
  254. (Paicpu(hp3)^.opcode = A_JMP) And
  255. GetNextInstruction(hp3, hp4) And
  256. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  257. Then
  258. Begin
  259. Paicpu(hp2)^.Opcode := A_SUB;
  260. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  261. Paicpu(hp2)^.LoadConst(0,1);
  262. Paicpu(hp2)^.ops:=2;
  263. Paicpu(hp3)^.Opcode := A_Jcc;
  264. Case paicpu(hp1)^.condition of
  265. C_LE: Paicpu(hp3)^.condition := C_GE;
  266. C_BE: Paicpu(hp3)^.condition := C_AE;
  267. End;
  268. AsmL^.Remove(p);
  269. AsmL^.Remove(hp1);
  270. Dispose(p, Done);
  271. Dispose(hp1, Done);
  272. p := hp2;
  273. continue;
  274. End
  275. Else
  276. {$endif foropt}
  277. {change "cmp $0, %reg" to "test %reg, %reg"}
  278. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  279. Begin
  280. Paicpu(p)^.opcode := A_TEST;
  281. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  282. End;
  283. End;
  284. A_FLD:
  285. Begin
  286. If (Paicpu(p)^.oper[0].typ = top_reg) And
  287. GetNextInstruction(p, hp1) And
  288. (hp1^.typ = Ait_Instruction) And
  289. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  290. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  291. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  292. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  293. { change to
  294. fld reg fxxx reg,st
  295. fxxxp st, st1 (hp1)
  296. Remark: non commutative operations must be reversed!
  297. }
  298. begin
  299. Case Paicpu(hp1)^.opcode Of
  300. A_FMULP,A_FADDP,
  301. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  302. begin
  303. Case Paicpu(hp1)^.opcode Of
  304. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  305. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  306. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  307. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  308. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  309. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  310. End;
  311. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  312. Paicpu(hp1)^.oper[1].reg := R_ST;
  313. AsmL^.Remove(p);
  314. Dispose(p, Done);
  315. p := hp1;
  316. Continue;
  317. end;
  318. end;
  319. end
  320. else
  321. If (Paicpu(p)^.oper[0].typ = top_ref) And
  322. GetNextInstruction(p, hp2) And
  323. (hp2^.typ = Ait_Instruction) And
  324. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  325. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  326. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  327. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  328. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  329. If GetLastInstruction(p, hp1) And
  330. (hp1^.typ = Ait_Instruction) And
  331. ((Paicpu(hp1)^.opcode = A_FLD) Or
  332. (Paicpu(hp1)^.opcode = A_FST)) And
  333. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  334. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  335. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  336. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  337. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  338. { change to
  339. fld/fst mem1 (hp1) fld/fst mem1
  340. fld mem1 (p) fadd/
  341. faddp/ fmul st, st
  342. fmulp st, st1 (hp2) }
  343. Begin
  344. AsmL^.Remove(p);
  345. Dispose(p, Done);
  346. p := hp1;
  347. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  348. Paicpu(hp2)^.opcode := A_FADD
  349. Else
  350. Paicpu(hp2)^.opcode := A_FMUL;
  351. Paicpu(hp2)^.oper[1].reg := R_ST;
  352. End
  353. Else
  354. { change to
  355. fld/fst mem1 (hp1) fld/fst mem1
  356. fld mem1 (p) fld st}
  357. Begin
  358. Paicpu(p)^.changeopsize(S_FL);
  359. Paicpu(p)^.loadreg(0,R_ST);
  360. End
  361. Else
  362. Begin
  363. Case Paicpu(hp2)^.opcode Of
  364. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  365. { change to
  366. fld/fst mem1 (hp1) fld/fst mem1
  367. fld mem2 (p) fxxx mem2
  368. fxxxp st, st1 (hp2) }
  369. Begin
  370. Case Paicpu(hp2)^.opcode Of
  371. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  372. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  373. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  374. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  375. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  376. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  377. End;
  378. AsmL^.Remove(hp2);
  379. Dispose(hp2, Done)
  380. End
  381. End
  382. End
  383. End;
  384. A_FSTP,A_FISTP:
  385. Begin
  386. If (Paicpu(p)^.oper[0].typ = top_ref) And
  387. GetNextInstruction(p, hp1) And
  388. (Pai(hp1)^.typ = ait_instruction) And
  389. (((Paicpu(hp1)^.opcode = A_FLD) And
  390. (Paicpu(p)^.opcode = A_FSTP)) Or
  391. ((Paicpu(p)^.opcode = A_FISTP) And
  392. (Paicpu(hp1)^.opcode = A_FILD))) And
  393. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  394. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  395. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  396. Then
  397. Begin
  398. If GetNextInstruction(hp1, hp2) And
  399. (hp2^.typ = ait_instruction) And
  400. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  401. (Paicpu(hp2)^.opcode = A_RET)) And
  402. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  403. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.RetOffset) And
  404. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  405. Then
  406. Begin
  407. AsmL^.Remove(p);
  408. AsmL^.Remove(hp1);
  409. Dispose(p, Done);
  410. Dispose(hp1, Done);
  411. p := hp2;
  412. Continue
  413. End
  414. Else
  415. {fst can't store an extended value!}
  416. If (Paicpu(p)^.opsize <> S_FX) And
  417. (Paicpu(p)^.opsize <> S_IQ) Then
  418. Begin
  419. If (Paicpu(p)^.opcode = A_FSTP) Then
  420. Paicpu(p)^.opcode := A_FST
  421. Else Paicpu(p)^.opcode := A_FIST;
  422. AsmL^.Remove(hp1);
  423. Dispose(hp1, done)
  424. End
  425. End;
  426. End;
  427. A_IMUL:
  428. {changes certain "imul const, %reg"'s to lea sequences}
  429. Begin
  430. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  431. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  432. (Paicpu(p)^.opsize = S_L) Then
  433. If (Paicpu(p)^.oper[0].val = 1) Then
  434. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  435. {remove "imul $1, reg"}
  436. Begin
  437. hp1 := Pai(p^.Next);
  438. AsmL^.Remove(p);
  439. Dispose(p, Done);
  440. p := hp1;
  441. Continue;
  442. End
  443. Else
  444. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  445. Begin
  446. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  447. hp1^.fileinfo := p^.fileinfo;
  448. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  449. Dispose(p, Done);
  450. p := hp1;
  451. End
  452. Else If
  453. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  454. (Paicpu(p)^.oper[2].typ = Top_None)) And
  455. (aktoptprocessor < ClassP6) And
  456. (Paicpu(p)^.oper[0].val <= 12) And
  457. Not(CS_LittleSize in aktglobalswitches) And
  458. (Not(GetNextInstruction(p, hp1)) Or
  459. {GetNextInstruction(p, hp1) And}
  460. Not((Pai(hp1)^.typ = ait_instruction) And
  461. ((paicpu(hp1)^.opcode=A_Jcc) and
  462. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  463. Then
  464. Begin
  465. New(TmpRef);
  466. Reset_reference(tmpref^);
  467. Case Paicpu(p)^.oper[0].val Of
  468. 3: Begin
  469. {imul 3, reg1, reg2 to
  470. lea (reg1,reg1,2), reg2
  471. imul 3, reg1 to
  472. lea (reg1,reg1,2), reg1}
  473. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  474. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  475. TmpRef^.ScaleFactor := 2;
  476. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  477. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  478. Else
  479. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  480. hp1^.fileinfo := p^.fileinfo;
  481. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  482. Dispose(p, Done);
  483. p := hp1;
  484. End;
  485. 5: Begin
  486. {imul 5, reg1, reg2 to
  487. lea (reg1,reg1,4), reg2
  488. imul 5, reg1 to
  489. lea (reg1,reg1,4), reg1}
  490. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  491. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  492. TmpRef^.ScaleFactor := 4;
  493. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  494. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  495. Else
  496. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  497. hp1^.fileinfo:= p^.fileinfo;
  498. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  499. Dispose(p, Done);
  500. p := hp1;
  501. End;
  502. 6: Begin
  503. {imul 6, reg1, reg2 to
  504. lea (,reg1,2), reg2
  505. lea (reg2,reg1,4), reg2
  506. imul 6, reg1 to
  507. lea (reg1,reg1,2), reg1
  508. add reg1, reg1}
  509. If (aktoptprocessor <= Class386)
  510. Then
  511. Begin
  512. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  513. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  514. Then
  515. Begin
  516. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  517. TmpRef^.ScaleFactor := 4;
  518. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  519. End
  520. Else
  521. Begin
  522. Dispose(TmpRef);
  523. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  524. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  525. End;
  526. hp1^.fileinfo := p^.fileinfo;
  527. InsertLLItem(AsmL,p, p^.next, hp1);
  528. New(TmpRef);
  529. Reset_reference(tmpref^);
  530. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  531. TmpRef^.ScaleFactor := 2;
  532. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  533. Then
  534. Begin
  535. TmpRef^.base := R_NO;
  536. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  537. Paicpu(p)^.oper[2].reg));
  538. End
  539. Else
  540. Begin
  541. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  542. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  543. End;
  544. hp1^.fileinfo := p^.fileinfo;
  545. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  546. Dispose(p, Done);
  547. p := Pai(hp1^.next);
  548. End
  549. Else Dispose(TmpRef);
  550. End;
  551. 9: Begin
  552. {imul 9, reg1, reg2 to
  553. lea (reg1,reg1,8), reg2
  554. imul 9, reg1 to
  555. lea (reg1,reg1,8), reg1}
  556. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  557. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  558. TmpRef^.ScaleFactor := 8;
  559. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  560. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  561. Else
  562. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  563. hp1^.fileinfo := p^.fileinfo;
  564. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  565. Dispose(p, Done);
  566. p := hp1;
  567. End;
  568. 10: Begin
  569. {imul 10, reg1, reg2 to
  570. lea (reg1,reg1,4), reg2
  571. add reg2, reg2
  572. imul 10, reg1 to
  573. lea (reg1,reg1,4), reg1
  574. add reg1, reg1}
  575. If (aktoptprocessor <= Class386) Then
  576. Begin
  577. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  578. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  579. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  580. Else
  581. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  582. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  583. hp1^.fileinfo := p^.fileinfo;
  584. InsertLLItem(AsmL,p, p^.next, hp1);
  585. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  586. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  587. TmpRef^.ScaleFactor := 4;
  588. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  589. Then
  590. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg))
  591. Else
  592. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  593. hp1^.fileinfo := p^.fileinfo;
  594. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  595. Dispose(p, Done);
  596. p := Pai(hp1^.next);
  597. End
  598. Else Dispose(TmpRef);
  599. End;
  600. 12: Begin
  601. {imul 12, reg1, reg2 to
  602. lea (,reg1,4), reg2
  603. lea (,reg1,8) reg2
  604. imul 12, reg1 to
  605. lea (reg1,reg1,2), reg1
  606. lea (,reg1,4), reg1}
  607. If (aktoptprocessor <= Class386)
  608. Then
  609. Begin
  610. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  611. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  612. Begin
  613. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  614. TmpRef^.ScaleFactor := 8;
  615. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  616. End
  617. Else
  618. Begin
  619. TmpRef^.base := R_NO;
  620. TmpRef^.ScaleFactor := 4;
  621. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  622. End;
  623. hp1^.fileinfo := p^.fileinfo;
  624. InsertLLItem(AsmL,p, p^.next, hp1);
  625. New(TmpRef);
  626. Reset_reference(tmpref^);
  627. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  628. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  629. Begin
  630. TmpRef^.base := R_NO;
  631. TmpRef^.ScaleFactor := 4;
  632. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  633. End
  634. Else
  635. Begin
  636. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  637. TmpRef^.ScaleFactor := 2;
  638. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  639. End;
  640. hp1^.fileinfo := p^.fileinfo;
  641. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  642. Dispose(p, Done);
  643. p := Pai(hp1^.next);
  644. End
  645. Else Dispose(TmpRef);
  646. End
  647. Else Dispose(TmpRef);
  648. End;
  649. End;
  650. End;
  651. A_LEA:
  652. Begin
  653. {removes seg register prefixes from LEA operations, as they
  654. don't do anything}
  655. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  656. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  657. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  658. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  659. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  660. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  661. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  662. Then
  663. Begin
  664. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  665. Paicpu(p)^.oper[1].reg));
  666. hp1^.fileinfo := p^.fileinfo;
  667. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  668. Dispose(p, Done);
  669. p := hp1;
  670. Continue;
  671. End
  672. Else
  673. Begin
  674. hp1 := Pai(p^.Next);
  675. AsmL^.Remove(p);
  676. Dispose(p, Done);
  677. p := hp1;
  678. Continue;
  679. End;
  680. End;
  681. A_MOV:
  682. Begin
  683. TmpUsedRegs := UsedRegs;
  684. If (Paicpu(p)^.oper[1].typ = top_reg) And
  685. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  686. GetNextInstruction(p, hp1) And
  687. (Pai(hp1)^.typ = ait_instruction) And
  688. (Paicpu(hp1)^.opcode = A_MOV) And
  689. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  690. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  691. Then
  692. {we have "mov x, %treg; mov %treg, y}
  693. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  694. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  695. Case Paicpu(p)^.oper[0].typ Of
  696. top_reg:
  697. Begin
  698. { change "mov %reg, %treg; mov %treg, y"
  699. to "mov %reg, y" }
  700. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  701. AsmL^.Remove(p);
  702. Dispose(p, Done);
  703. p := hp1;
  704. continue;
  705. End;
  706. top_ref:
  707. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  708. Begin
  709. { change "mov mem, %treg; mov %treg, %reg"
  710. to "mov mem, %reg" }
  711. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  712. AsmL^.Remove(hp1);
  713. Dispose(hp1, Done);
  714. continue;
  715. End;
  716. End
  717. Else
  718. {remove an instruction which never makes sense: we've got
  719. "mov mem, %reg1; mov %reg1, %edi" and then EDI isn't used anymore!}
  720. { Begin
  721. If (Paicpu(hp1)^.oper[1].reg = R_EDI) And
  722. Not(GetNextInstruction(hp1, hp2) And
  723. (Pai(hp2)^.typ = ait_instruction) And
  724. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  725. (Paicpu(hp2)^.oper[1] = Pointer(R_ESI))) Then
  726. Begin
  727. AsmL^.Remove(hp1);
  728. Dispose(hp1, Done);
  729. Continue;
  730. End
  731. End}
  732. Else
  733. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  734. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  735. penalty}
  736. If (Paicpu(p)^.oper[0].typ = top_reg) And
  737. (Paicpu(p)^.oper[1].typ = top_reg) And
  738. GetNextInstruction(p,hp1) And
  739. (Pai(hp1)^.typ = ait_instruction) And
  740. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  741. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  742. Then
  743. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  744. Begin
  745. If ((Paicpu(hp1)^.opcode = A_OR) Or
  746. (Paicpu(hp1)^.opcode = A_TEST)) And
  747. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  748. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  749. Then
  750. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  751. Begin
  752. TmpUsedRegs := UsedRegs;
  753. If GetNextInstruction(hp1, hp2) And
  754. (hp2^.typ = ait_instruction) And
  755. paicpu(hp2)^.is_jmp and
  756. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  757. Then
  758. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  759. "test %reg1, %reg1; jxx"}
  760. Begin
  761. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  762. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  763. AsmL^.Remove(p);
  764. Dispose(p, done);
  765. p := hp1;
  766. continue
  767. End
  768. Else
  769. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  770. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  771. Begin
  772. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  773. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  774. End;
  775. End
  776. { Else
  777. If (Paicpu(p^.next)^.opcode
  778. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  779. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  780. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  781. End
  782. Else
  783. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  784. x >= RetOffset) as it doesn't do anything (it writes either to a
  785. parameter or to the temporary storage room for the function
  786. result)}
  787. If GetNextInstruction(p, hp1) And
  788. (Pai(hp1)^.typ = ait_instruction)
  789. Then
  790. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  791. (Paicpu(hp1)^.opcode = A_RET)) And
  792. (Paicpu(p)^.oper[1].typ = top_ref) And
  793. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  794. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.RetOffset) And
  795. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  796. (Paicpu(p)^.oper[0].typ = top_reg)
  797. Then
  798. Begin
  799. AsmL^.Remove(p);
  800. Dispose(p, done);
  801. p := hp1;
  802. End
  803. Else
  804. If (Paicpu(p)^.oper[0].typ = top_reg) And
  805. (Paicpu(p)^.oper[1].typ = top_ref) And
  806. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  807. (Paicpu(hp1)^.opcode = A_CMP) And
  808. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  809. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  810. Then
  811. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  812. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  813. { Next instruction is also a MOV ? }
  814. If GetNextInstruction(p, hp1) And
  815. (pai(hp1)^.typ = ait_instruction) and
  816. (Paicpu(hp1)^.opcode = A_MOV) and
  817. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  818. Then
  819. Begin
  820. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  821. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  822. Then
  823. {mov reg1, mem1 or mov mem1, reg1
  824. mov mem2, reg2 mov reg2, mem2}
  825. Begin
  826. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  827. {mov reg1, mem1 or mov mem1, reg1
  828. mov mem2, reg1 mov reg2, mem1}
  829. Begin
  830. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  831. { Removes the second statement from
  832. mov reg1, mem1
  833. mov mem1, reg1 }
  834. Begin
  835. AsmL^.remove(hp1);
  836. Dispose(hp1,done);
  837. End
  838. Else
  839. Begin
  840. TmpUsedRegs := UsedRegs;
  841. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  842. If (Paicpu(p)^.oper[0].typ = top_reg) And
  843. { mov reg1, mem1
  844. mov mem2, reg1 }
  845. GetNextInstruction(hp1, hp2) And
  846. (hp2^.typ = ait_instruction) And
  847. (Paicpu(hp2)^.opcode = A_CMP) And
  848. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  849. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  850. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  851. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  852. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  853. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  854. { change to
  855. mov reg1, mem1 mov reg1, mem1
  856. mov mem2, reg1 cmp reg1, mem2
  857. cmp mem1, reg1 }
  858. Begin
  859. AsmL^.Remove(hp2);
  860. Dispose(hp2, Done);
  861. Paicpu(hp1)^.opcode := A_CMP;
  862. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  863. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  864. End;
  865. End;
  866. End
  867. Else
  868. Begin
  869. If GetNextInstruction(hp1, hp2) And
  870. (Paicpu(p)^.oper[0].typ = top_ref) And
  871. (Paicpu(p)^.oper[1].typ = top_reg) And
  872. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  873. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  874. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  875. (Pai(hp2)^.typ = ait_instruction) And
  876. (Paicpu(hp2)^.opcode = A_MOV) And
  877. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  878. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  879. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  880. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^)
  881. Then
  882. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI])
  883. Then
  884. { mov mem1, %edi
  885. mov %edi, mem2
  886. mov mem2, reg2
  887. to:
  888. mov mem1, reg2
  889. mov reg2, mem2}
  890. Begin
  891. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  892. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  893. AsmL^.Remove(hp2);
  894. Dispose(hp2,Done);
  895. End
  896. Else
  897. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  898. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  899. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  900. Then
  901. { mov mem1, reg1 mov mem1, reg1
  902. mov reg1, mem2 mov reg1, mem2
  903. mov mem2, reg2 mov mem2, reg1
  904. to: to:
  905. mov mem1, reg1 mov mem1, reg1
  906. mov mem1, reg2 mov reg1, mem2
  907. mov reg1, mem2
  908. or (if mem1 depends on reg1
  909. and/or if mem2 depends on reg2)
  910. to:
  911. mov mem1, reg1
  912. mov reg1, mem2
  913. mov reg1, reg2
  914. }
  915. Begin
  916. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  917. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  918. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  919. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  920. End
  921. Else
  922. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  923. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  924. Else
  925. Begin
  926. AsmL^.Remove(hp2);
  927. Dispose(hp2, Done);
  928. End
  929. End;
  930. End
  931. Else
  932. (* {movl [mem1],reg1
  933. movl [mem1],reg2
  934. to:
  935. movl [mem1],reg1
  936. movl reg1,reg2 }
  937. If (Paicpu(p)^.oper[0].typ = top_ref) and
  938. (Paicpu(p)^.oper[1].typ = top_reg) and
  939. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  940. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  941. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  942. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  943. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  944. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  945. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  946. Else*)
  947. { movl const1,[mem1]
  948. movl [mem1],reg1
  949. to:
  950. movl const1,reg1
  951. movl reg1,[mem1] }
  952. If (Paicpu(p)^.oper[0].typ = top_const) and
  953. (Paicpu(p)^.oper[1].typ = top_ref) and
  954. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  955. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  956. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  957. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  958. Begin
  959. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  960. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  961. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  962. End
  963. End;
  964. {changes "mov $0, %reg" into "xor %reg, %reg"}
  965. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  966. (Paicpu(p)^.oper[0].val = 0) And
  967. (Paicpu(p)^.oper[1].typ = Top_Reg)
  968. Then
  969. Begin
  970. Paicpu(p)^.opcode := A_XOR;
  971. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  972. End;
  973. End;
  974. A_MOVZX:
  975. Begin
  976. {removes superfluous And's after movzx's}
  977. If (Paicpu(p)^.oper[1].typ = top_reg) And
  978. GetNextInstruction(p, hp1) And
  979. (Pai(hp1)^.typ = ait_instruction) And
  980. (Paicpu(hp1)^.opcode = A_AND) And
  981. (Paicpu(hp1)^.oper[0].typ = top_const) And
  982. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  983. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  984. Then
  985. Case Paicpu(p)^.opsize Of
  986. S_BL, S_BW:
  987. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  988. Begin
  989. AsmL^.Remove(hp1);
  990. Dispose(hp1, Done);
  991. End;
  992. S_WL:
  993. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  994. Begin
  995. AsmL^.Remove(hp1);
  996. Dispose(hp1, Done);
  997. End;
  998. End;
  999. {changes some movzx constructs to faster synonims (all examples
  1000. are given with eax/ax, but are also valid for other registers)}
  1001. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1002. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1003. Case Paicpu(p)^.opsize of
  1004. S_BW:
  1005. Begin
  1006. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1007. Not(CS_LittleSize In aktglobalswitches)
  1008. Then
  1009. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1010. Begin
  1011. Paicpu(p)^.opcode := A_AND;
  1012. Paicpu(p)^.changeopsize(S_W);
  1013. Paicpu(p)^.LoadConst(0,$ff);
  1014. End
  1015. Else
  1016. If GetNextInstruction(p, hp1) And
  1017. (Pai(hp1)^.typ = ait_instruction) And
  1018. (Paicpu(hp1)^.opcode = A_AND) And
  1019. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1020. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1021. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1022. Then
  1023. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1024. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1025. Begin
  1026. Paicpu(p)^.opcode := A_MOV;
  1027. Paicpu(p)^.changeopsize(S_W);
  1028. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1029. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1030. End;
  1031. End;
  1032. S_BL:
  1033. Begin
  1034. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1035. Not(CS_LittleSize in aktglobalswitches)
  1036. Then
  1037. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1038. Begin
  1039. Paicpu(p)^.opcode := A_AND;
  1040. Paicpu(p)^.changeopsize(S_L);
  1041. Paicpu(p)^.loadconst(0,$ff)
  1042. End
  1043. Else
  1044. If GetNextInstruction(p, hp1) And
  1045. (Pai(hp1)^.typ = ait_instruction) And
  1046. (Paicpu(hp1)^.opcode = A_AND) And
  1047. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1048. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1049. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1050. Then
  1051. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1052. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1053. Begin
  1054. Paicpu(p)^.opcode := A_MOV;
  1055. Paicpu(p)^.changeopsize(S_L);
  1056. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1057. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1058. End
  1059. End;
  1060. S_WL:
  1061. Begin
  1062. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1063. Not(CS_LittleSize In aktglobalswitches)
  1064. Then
  1065. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1066. Begin
  1067. Paicpu(p)^.opcode := A_AND;
  1068. Paicpu(p)^.changeopsize(S_L);
  1069. Paicpu(p)^.LoadConst(0,$ffff);
  1070. End
  1071. Else
  1072. If GetNextInstruction(p, hp1) And
  1073. (Pai(hp1)^.typ = ait_instruction) And
  1074. (Paicpu(hp1)^.opcode = A_AND) And
  1075. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1076. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1077. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1078. Then
  1079. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1080. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1081. Begin
  1082. Paicpu(p)^.opcode := A_MOV;
  1083. Paicpu(p)^.changeopsize(S_L);
  1084. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1085. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1086. End;
  1087. End;
  1088. End
  1089. Else
  1090. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1091. Begin
  1092. If GetNextInstruction(p, hp1) And
  1093. (Pai(hp1)^.typ = ait_instruction) And
  1094. (Paicpu(hp1)^.opcode = A_AND) And
  1095. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1096. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1097. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1098. Begin
  1099. Paicpu(p)^.opcode := A_MOV;
  1100. Case Paicpu(p)^.opsize Of
  1101. S_BL:
  1102. Begin
  1103. Paicpu(p)^.changeopsize(S_L);
  1104. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1105. End;
  1106. S_WL:
  1107. Begin
  1108. Paicpu(p)^.changeopsize(S_L);
  1109. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1110. End;
  1111. S_BW:
  1112. Begin
  1113. Paicpu(p)^.changeopsize(S_W);
  1114. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1115. End;
  1116. End;
  1117. End;
  1118. End;
  1119. End;
  1120. A_POP:
  1121. Begin
  1122. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1123. GetNextInstruction(p, hp1) And
  1124. (pai(hp1)^.typ=ait_instruction) and
  1125. (Paicpu(hp1)^.opcode=A_PUSH) and
  1126. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1127. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1128. { This can't be done, because the register which is popped
  1129. can still be used after the push (PFV)
  1130. If (Not(cs_regalloc in aktglobalswitches)) Then
  1131. Begin
  1132. hp2:=pai(hp1^.next);
  1133. asml^.remove(p);
  1134. asml^.remove(hp1);
  1135. dispose(p,done);
  1136. dispose(hp1,done);
  1137. p:=hp2;
  1138. continue
  1139. End
  1140. Else }
  1141. Begin
  1142. { change it to a two op operation }
  1143. Paicpu(p)^.oper[1].typ:=top_none;
  1144. Paicpu(p)^.ops:=2;
  1145. Paicpu(p)^.opcode := A_MOV;
  1146. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1147. New(TmpRef);
  1148. Reset_reference(tmpref^);
  1149. TmpRef^.base := R_ESP;
  1150. Paicpu(p)^.LoadRef(0,TmpRef);
  1151. AsmL^.Remove(hp1);
  1152. Dispose(hp1, Done)
  1153. End;
  1154. end;
  1155. A_PUSH:
  1156. Begin
  1157. If (Paicpu(p)^.opsize = S_W) And
  1158. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1159. GetNextInstruction(p, hp1) And
  1160. (Pai(hp1)^.typ = ait_instruction) And
  1161. (Paicpu(hp1)^.opcode = A_PUSH) And
  1162. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1163. (Paicpu(hp1)^.opsize = S_W) Then
  1164. Begin
  1165. Paicpu(p)^.changeopsize(S_L);
  1166. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + Paicpu(hp1)^.oper[0].val);
  1167. AsmL^.Remove(hp1);
  1168. Dispose(hp1, Done)
  1169. End;
  1170. End;
  1171. A_SHL, A_SAL:
  1172. Begin
  1173. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1174. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1175. (Paicpu(p)^.opsize = S_L) And
  1176. (Paicpu(p)^.oper[0].val <= 3)
  1177. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1178. Then
  1179. Begin
  1180. TmpBool1 := True; {should we check the next instruction?}
  1181. TmpBool2 := False; {have we found an add/sub which could be
  1182. integrated in the lea?}
  1183. New(TmpRef);
  1184. Reset_reference(tmpref^);
  1185. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1186. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1187. While TmpBool1 And
  1188. GetNextInstruction(p, hp1) And
  1189. (Pai(hp1)^.typ = ait_instruction) And
  1190. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1191. (Paicpu(hp1)^.opcode = A_SUB)) And
  1192. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1193. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1194. Begin
  1195. TmpBool1 := False;
  1196. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1197. Then
  1198. Begin
  1199. TmpBool1 := True;
  1200. TmpBool2 := True;
  1201. If Paicpu(hp1)^.opcode = A_ADD Then
  1202. Inc(TmpRef^.offset, Paicpu(hp1)^.oper[0].val)
  1203. Else
  1204. Dec(TmpRef^.offset, Paicpu(hp1)^.oper[0].val);
  1205. AsmL^.Remove(hp1);
  1206. Dispose(hp1, Done);
  1207. End
  1208. Else
  1209. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1210. (Paicpu(hp1)^.opcode = A_ADD) And
  1211. (TmpRef^.base = R_NO) Then
  1212. Begin
  1213. TmpBool1 := True;
  1214. TmpBool2 := True;
  1215. TmpRef^.base := Paicpu(hp1)^.oper[0].reg;
  1216. AsmL^.Remove(hp1);
  1217. Dispose(hp1, Done);
  1218. End;
  1219. End;
  1220. If TmpBool2 Or
  1221. ((aktoptprocessor < ClassP6) And
  1222. (Paicpu(p)^.oper[0].val <= 3) And
  1223. Not(CS_LittleSize in aktglobalswitches))
  1224. Then
  1225. Begin
  1226. If Not(TmpBool2) And
  1227. (Paicpu(p)^.oper[0].val = 1)
  1228. Then
  1229. Begin
  1230. Dispose(TmpRef);
  1231. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1232. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1233. End
  1234. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  1235. Paicpu(p)^.oper[1].reg));
  1236. hp1^.fileinfo := p^.fileinfo;
  1237. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1238. Dispose(p, Done);
  1239. p := hp1;
  1240. End;
  1241. End
  1242. Else
  1243. If (aktoptprocessor < ClassP6) And
  1244. (Paicpu(p)^.oper[0].typ = top_const) And
  1245. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1246. If (Paicpu(p)^.oper[0].val = 1)
  1247. Then
  1248. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1249. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1250. (unlike shl, which is only pairable in the U pipe)}
  1251. Begin
  1252. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1253. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1254. hp1^.fileinfo := p^.fileinfo;
  1255. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1256. Dispose(p, done);
  1257. p := hp1;
  1258. End
  1259. Else If (Paicpu(p)^.opsize = S_L) and
  1260. (Paicpu(p)^.oper[0].val<= 3) Then
  1261. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1262. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1263. Begin
  1264. New(TmpRef);
  1265. Reset_reference(tmpref^);
  1266. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1267. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1268. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,TmpRef, Paicpu(p)^.oper[1].reg));
  1269. hp1^.fileinfo := p^.fileinfo;
  1270. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1271. Dispose(p, done);
  1272. p := hp1;
  1273. End
  1274. End;
  1275. A_SAR, A_SHR:
  1276. {changes the code sequence
  1277. shr/sar const1, x
  1278. shl const2, x
  1279. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1280. Begin
  1281. If GetNextInstruction(p, hp1) And
  1282. (pai(hp1)^.typ = ait_instruction) and
  1283. (Paicpu(hp1)^.opcode = A_SHL) and
  1284. (Paicpu(p)^.oper[0].typ = top_const) and
  1285. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1286. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1287. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1288. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1289. Then
  1290. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1291. Not(CS_LittleSize In aktglobalswitches)
  1292. Then
  1293. { shr/sar const1, %reg
  1294. shl const2, %reg
  1295. with const1 > const2 }
  1296. Begin
  1297. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1298. Paicpu(hp1)^.opcode := A_AND;
  1299. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1300. Case Paicpu(p)^.opsize Of
  1301. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1302. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1303. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1304. End;
  1305. End
  1306. Else
  1307. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1308. Not(CS_LittleSize In aktglobalswitches)
  1309. Then
  1310. { shr/sar const1, %reg
  1311. shl const2, %reg
  1312. with const1 < const2 }
  1313. Begin
  1314. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1315. Paicpu(p)^.opcode := A_AND;
  1316. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1317. Case Paicpu(p)^.opsize Of
  1318. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1319. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1320. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1321. End;
  1322. End
  1323. Else
  1324. { shr/sar const1, %reg
  1325. shl const2, %reg
  1326. with const1 = const2 }
  1327. Begin
  1328. Paicpu(p)^.opcode := A_AND;
  1329. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1330. Case Paicpu(p)^.opsize Of
  1331. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1332. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1333. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1334. End;
  1335. AsmL^.remove(hp1);
  1336. dispose(hp1, done);
  1337. End;
  1338. End;
  1339. A_SETcc :
  1340. Begin
  1341. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1342. GetNextInstruction(p, hp1) And
  1343. GetNextInstruction(hp1, hp2) And
  1344. (hp2^.typ = ait_instruction) And
  1345. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1346. (Paicpu(hp2)^.opcode = A_RET)) And
  1347. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1348. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1349. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.RetOffset) And
  1350. (hp1^.typ = ait_instruction) And
  1351. (Paicpu(hp1)^.opcode = A_MOV) And
  1352. (Paicpu(hp1)^.opsize = S_B) And
  1353. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1354. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1355. Begin
  1356. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1357. AsmL^.Remove(hp1);
  1358. Dispose(hp1, Done)
  1359. End
  1360. End;
  1361. A_SUB:
  1362. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1363. { * change "sub/add const1, reg" or "dec reg" followed by
  1364. "sub const2, reg" to one "sub ..., reg" }
  1365. Begin
  1366. If (Paicpu(p)^.oper[0].typ = top_const) And
  1367. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1368. If (Paicpu(p)^.oper[0].val = 2) And
  1369. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1370. Begin
  1371. hp1 := Pai(p^.next);
  1372. While Assigned(hp1) And
  1373. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1374. Not((Pai(hp1)^.typ = ait_instruction) And
  1375. ((Paicpu(hp1)^.opcode = A_CALL) or
  1376. (Paicpu(hp1)^.opcode = A_PUSH) or
  1377. ((Paicpu(hp1)^.opcode = A_MOV) And
  1378. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1379. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1380. hp1 := Pai(hp1^.next);
  1381. If Assigned(hp1) And
  1382. (Pai(hp1)^.typ = ait_instruction) And
  1383. (Paicpu(hp1)^.opcode = A_PUSH) And
  1384. (Paicpu(hp1)^.opsize = S_W)
  1385. Then
  1386. Begin
  1387. Paicpu(hp1)^.changeopsize(S_L);
  1388. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1389. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1390. hp1 := Pai(p^.next);
  1391. AsmL^.Remove(p);
  1392. Dispose(p, Done);
  1393. p := hp1;
  1394. Continue
  1395. End;
  1396. If DoSubAddOpt(p) Then continue;
  1397. End
  1398. Else If DoSubAddOpt(p) Then Continue
  1399. End;
  1400. A_TEST, A_OR:
  1401. {removes the line marked with (x) from the sequence
  1402. And/or/xor/add/sub/... $x, %y
  1403. test/or %y, %y (x)
  1404. j(n)z _Label
  1405. as the first instruction already adjusts the ZF}
  1406. Begin
  1407. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1408. If GetLastInstruction(p, hp1) And
  1409. (pai(hp1)^.typ = ait_instruction) Then
  1410. Case Paicpu(hp1)^.opcode Of
  1411. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1412. Begin
  1413. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1414. Begin
  1415. hp1 := pai(p^.next);
  1416. asml^.remove(p);
  1417. dispose(p, done);
  1418. p := pai(hp1);
  1419. continue
  1420. End;
  1421. End;
  1422. A_DEC, A_INC, A_NEG:
  1423. Begin
  1424. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1425. Begin
  1426. Case Paicpu(hp1)^.opcode Of
  1427. A_DEC, A_INC:
  1428. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1429. Begin
  1430. Case Paicpu(hp1)^.opcode Of
  1431. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1432. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1433. End;
  1434. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1435. Paicpu(hp1)^.LoadConst(0,1);
  1436. Paicpu(hp1)^.ops:=2;
  1437. End
  1438. End;
  1439. hp1 := pai(p^.next);
  1440. asml^.remove(p);
  1441. dispose(p, done);
  1442. p := pai(hp1);
  1443. continue
  1444. End;
  1445. End
  1446. End
  1447. Else
  1448. End;
  1449. End;
  1450. end; { if is_jmp }
  1451. End;
  1452. { ait_label:
  1453. Begin
  1454. If Not(Pai_Label(p)^.l^.is_used)
  1455. Then
  1456. Begin
  1457. hp1 := Pai(p^.next);
  1458. AsmL^.Remove(p);
  1459. Dispose(p, Done);
  1460. p := hp1;
  1461. Continue
  1462. End;
  1463. End;}
  1464. End;
  1465. p:=pai(p^.next);
  1466. end;
  1467. end;
  1468. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1469. var
  1470. p,hp1,hp2: pai;
  1471. Begin
  1472. P := BlockStart;
  1473. While (P <> BlockEnd) Do
  1474. Begin
  1475. Case P^.Typ Of
  1476. Ait_Instruction:
  1477. Begin
  1478. Case Paicpu(p)^.opcode Of
  1479. A_CALL:
  1480. If (AktOptProcessor < ClassP6) And
  1481. GetNextInstruction(p, hp1) And
  1482. (hp1^.typ = ait_instruction) And
  1483. (paicpu(hp1)^.opcode = A_JMP) Then
  1484. Begin
  1485. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1486. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1487. hp2^.fileinfo := p^.fileinfo;
  1488. InsertLLItem(AsmL, p^.previous, p, hp2);
  1489. Paicpu(p)^.opcode := A_JMP;
  1490. AsmL^.Remove(hp1);
  1491. Dispose(hp1, Done)
  1492. End;
  1493. A_MOV:
  1494. Begin
  1495. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1496. (Paicpu(p)^.oper[1].typ = top_reg) And
  1497. GetNextInstruction(p, hp1) And
  1498. (hp1^.typ = ait_Instruction) And
  1499. ((Paicpu(hp1)^.opcode = A_MOV) or
  1500. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1501. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1502. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1503. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1504. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1505. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1506. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1507. {mov reg1, reg2
  1508. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1509. Begin
  1510. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1511. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1512. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1513. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1514. AsmL^.Remove(p);
  1515. Dispose(p, Done);
  1516. p := hp1;
  1517. Continue;
  1518. End;
  1519. End;
  1520. A_MOVZX:
  1521. Begin
  1522. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1523. If (Paicpu(p)^.oper[0].typ = top_reg)
  1524. Then
  1525. Case Paicpu(p)^.opsize of
  1526. S_BL:
  1527. Begin
  1528. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1529. Not(CS_LittleSize in aktglobalswitches) And
  1530. (aktoptprocessor = ClassP5)
  1531. Then
  1532. {Change "movzbl %reg1, %reg2" to
  1533. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1534. PentiumMMX}
  1535. Begin
  1536. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1537. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1538. hp1^.fileinfo := p^.fileinfo;
  1539. InsertLLItem(AsmL,p^.previous, p, hp1);
  1540. Paicpu(p)^.opcode := A_MOV;
  1541. Paicpu(p)^.changeopsize(S_B);
  1542. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1543. End;
  1544. End;
  1545. End
  1546. Else
  1547. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1548. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1549. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1550. Not(CS_LittleSize in aktglobalswitches) And
  1551. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1552. (aktoptprocessor = ClassP5) And
  1553. (Paicpu(p)^.opsize = S_BL)
  1554. Then
  1555. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1556. Pentium and PentiumMMX}
  1557. Begin
  1558. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1559. Paicpu(p)^.oper[1].reg));
  1560. hp1^.fileinfo := p^.fileinfo;
  1561. Paicpu(p)^.opcode := A_MOV;
  1562. Paicpu(p)^.changeopsize(S_B);
  1563. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1564. InsertLLItem(AsmL,p^.previous, p, hp1);
  1565. End;
  1566. End;
  1567. End;
  1568. End;
  1569. End;
  1570. p := Pai(p^.next)
  1571. End;
  1572. End;
  1573. End.
  1574. {
  1575. $Log$
  1576. Revision 1.66 1999-09-27 23:44:55 peter
  1577. * procinfo is now a pointer
  1578. * support for result setting in sub procedure
  1579. Revision 1.65 1999/09/05 14:27:19 florian
  1580. + fld reg;fxxx to fxxxr reg optimization
  1581. Revision 1.64 1999/08/25 12:00:02 jonas
  1582. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1583. Revision 1.63 1999/08/23 10:20:46 jonas
  1584. * fixed pop/push optmization
  1585. Revision 1.62 1999/08/10 12:30:00 pierre
  1586. * avoid unused locals
  1587. Revision 1.61 1999/08/05 15:02:48 jonas
  1588. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1589. Revision 1.60 1999/08/04 00:23:16 florian
  1590. * renamed i386asm and i386base to cpuasm and cpubase
  1591. Revision 1.59 1999/08/03 17:13:28 jonas
  1592. * fix for sar/shr-shl optimization
  1593. Revision 1.58 1999/07/30 18:17:55 jonas
  1594. * fix so (,reg) gets optimized to (reg)
  1595. Revision 1.57 1999/07/01 18:12:16 jonas
  1596. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1597. a movzx or movsx
  1598. Revision 1.56 1999/06/23 12:33:52 jonas
  1599. * merged
  1600. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1601. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1602. Revision 1.55 1999/06/18 09:55:31 peter
  1603. * merged
  1604. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1605. * pop;push -> mov (esp),reg always instead of being removed
  1606. Revision 1.54 1999/05/27 19:44:49 peter
  1607. * removed oldasm
  1608. * plabel -> pasmlabel
  1609. * -a switches to source writing automaticly
  1610. * assembler readers OOPed
  1611. * asmsymbol automaticly external
  1612. * jumptables and other label fixes for asm readers
  1613. Revision 1.53 1999/05/12 00:19:52 peter
  1614. * removed R_DEFAULT_SEG
  1615. * uniform float names
  1616. Revision 1.52 1999/05/05 16:19:04 jonas
  1617. + remove the segment prefixes from LEA instructions
  1618. Revision 1.51 1999/05/05 10:05:54 florian
  1619. * a delphi compiled compiler recompiles ppc
  1620. Revision 1.50 1999/05/02 21:33:55 florian
  1621. * several bugs regarding -Or fixed
  1622. Revision 1.49 1999/05/02 14:26:31 peter
  1623. * fixed dec -> sub $1 opt which didn't set ops=2
  1624. Revision 1.48 1999/05/01 13:24:34 peter
  1625. * merged nasm compiler
  1626. * old asm moved to oldasm/
  1627. Revision 1.5 1999/04/30 12:36:50 jonas
  1628. * fix from Brussels: call/jmp => push/jmp transformation didn't
  1629. count correctly the jmp references
  1630. Revision 1.4 1999/04/10 16:14:11 peter
  1631. * fixed optimizer
  1632. Revision 1.3 1999/04/09 08:33:18 peter
  1633. * fixed mov reg,treg;mov treg,x bug
  1634. Revision 1.2 1999/03/29 16:05:51 peter
  1635. * optimizer working for ag386bin
  1636. Revision 1.1 1999/03/26 00:01:15 peter
  1637. * first things for optimizer (compiles but cycle crashes)
  1638. Revision 1.39 1999/02/26 00:48:22 peter
  1639. * assembler writers fixed for ag386bin
  1640. Revision 1.38 1999/02/25 21:02:44 peter
  1641. * ag386bin updates
  1642. + coff writer
  1643. Revision 1.37 1999/02/22 02:15:30 peter
  1644. * updates for ag386bin
  1645. Revision 1.36 1999/01/04 22:04:15 jonas
  1646. + mov reg, mem1 to mov reg, mem1
  1647. mov mem2, reg cmp reg, mem2
  1648. cmp mem1, reg
  1649. # reg released
  1650. Revision 1.35 1999/01/04 12:58:55 jonas
  1651. * no fistp/fild optimization for S_IQ (fistq doesn't exist)
  1652. Revision 1.34 1998/12/29 18:48:17 jonas
  1653. + optimize pascal code surrounding assembler blocks
  1654. Revision 1.33 1998/12/23 15:16:21 jonas
  1655. * change "inc x/dec x; test x, x" to "add 1, x/sub 1,x" because inc and dec
  1656. don't affect the carry flag (test does). This *doesn't* fix the problem with
  1657. cardinal, that's a cg issue.
  1658. Revision 1.32 1998/12/16 12:09:29 jonas
  1659. * fixed fistp/fild optimization
  1660. Revision 1.31 1998/12/15 22:30:39 jonas
  1661. + change "sub/add const1, reg" or "dec reg" followed by "sub const2, reg" to one
  1662. "sub const3, reg"
  1663. * some small cleaning up
  1664. Revision 1.30 1998/12/15 15:43:20 jonas
  1665. * fixed bug in shr/shl optimization
  1666. Revision 1.29 1998/12/15 11:53:54 peter
  1667. * removed commentlevel
  1668. Revision 1.28 1998/12/14 22:01:45 jonas
  1669. - removed $ifdef ver0_99_11's
  1670. Revision 1.27 1998/12/11 00:03:35 peter
  1671. + globtype,tokens,version unit splitted from globals
  1672. Revision 1.26 1998/12/09 18:16:13 jonas
  1673. * corrected small syntax error in part between ifdef ver0_99_11
  1674. + added fistp/fild optimization between ifdef ver0_99_11
  1675. Revision 1.25 1998/12/02 16:23:29 jonas
  1676. * changed "if longintvar in set" to case or "if () or () .." statements
  1677. * tree.pas: changed inlinenumber (and associated constructor/vars) to a byte
  1678. Revision 1.24 1998/11/26 15:41:45 jonas
  1679. + change "setxx mem; movb mem, reg8" to "setxx reg8" if mem is a local
  1680. variable/parameter or function result (between $ifdef ver0_99_11)
  1681. Revision 1.23 1998/11/03 16:26:09 jonas
  1682. * "call x;jmp y" optimization not done anymore for P6 and equivalents
  1683. * made FPU optimizations simpler and more effective
  1684. Revision 1.22 1998/10/29 18:37:55 jonas
  1685. + change "call x; jmp y" to "push y; jmp x" (suggestion from Daniel)
  1686. Revision 1.19 1998/10/23 15:38:23 jonas
  1687. + some small FPU peephole optimizations (use value in FP regs instead of loading it
  1688. from memory if possible, mostly with var1+var1 and var1*var1)
  1689. Revision 1.18 1998/10/05 14:41:14 jonas
  1690. * fixed small memory leak
  1691. * fixed small inefficiency
  1692. * tested multiple line comments ability of my new MacCVS client :)
  1693. Revision 1.17 1998/10/02 17:29:56 jonas
  1694. + removal of "lea (reg), reg)", "imul $1, reg", change "mov reg1, reg2; mov (reg2), reg2" to "mov (reg1), reg2"
  1695. Revision 1.16 1998/10/01 20:19:57 jonas
  1696. * moved UpdateUsedRegs (+ bugfix) to daopt386
  1697. Revision 1.15 1998/09/30 12:18:29 peter
  1698. * fixed subl $2,esp;psuhw bug
  1699. Revision 1.14 1998/09/20 17:11:51 jonas
  1700. * released REGALLOC
  1701. Revision 1.13 1998/09/16 18:00:00 jonas
  1702. * optimizer now completely dependant on GetNext/GetLast instruction, works again with -dRegAlloc
  1703. Revision 1.12 1998/09/15 14:05:22 jonas
  1704. * fixed optimizer incompatibilities with freelabel code in psub
  1705. Revision 1.11 1998/08/28 10:57:02 peter
  1706. * removed warnings
  1707. Revision 1.10 1998/08/27 15:17:50 florian
  1708. * reinstated Jonas' bugfix
  1709. Revision 1.9 1998/08/25 16:58:59 pierre
  1710. * removed a line that add no sense and
  1711. introduce garbage in the asmlist
  1712. (uninitialized data !)
  1713. Revision 1.7 1998/08/19 16:07:53 jonas
  1714. * changed optimizer switches + cleanup of DestroyRefs in daopt386.pas
  1715. Revision 1.6 1998/08/10 14:50:14 peter
  1716. + localswitches, moduleswitches, globalswitches splitting
  1717. Revision 1.5 1998/08/06 19:40:28 jonas
  1718. * removed $ before and after Log in comment
  1719. Revision 1.4 1998/08/05 16:27:17 jonas
  1720. * fstp/fld bugfix (fstt does not exist)
  1721. Revision 1.3 1998/08/05 16:00:15 florian
  1722. * some fixes for ansi strings
  1723. * log to Log changed
  1724. }