aoptcpu.pas 23 KB

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  1. {
  2. Copyright (c) 1998-2014 by the Free Pascal development team
  3. This unit calls the optimization procedures to optimize the assembler
  4. code for m68k
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. {$define DEBUG_AOPTCPU}
  21. Interface
  22. uses
  23. cpubase, aoptobj, aoptcpub, aopt, aasmtai,
  24. cgbase;
  25. Type
  26. TCpuAsmOptimizer = class(TAsmOptimizer)
  27. function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean; override;
  28. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  29. function TryToRemoveTST(var p: tai): boolean;
  30. function TryToOptimizeMove(var p: tai): boolean;
  31. function MaybeRealConstOperSimplify(var p: tai): boolean;
  32. function OptPass1LEA(var p: tai): Boolean;
  33. function OptPass1MOVEM(var p: tai): Boolean;
  34. function OptPass1Bitwise(var p: tai): Boolean;
  35. { outputs a debug message into the assembler file }
  36. procedure DebugMsg(const s: string; p: tai);
  37. End;
  38. Implementation
  39. uses
  40. cutils, aasmcpu, cgutils, globtype, globals, verbose, cpuinfo, itcpugas, procinfo, cpupi,
  41. aoptutils;
  42. { Range check must be disabled explicitly as conversions between signed and unsigned
  43. 32-bit values are done without explicit typecasts }
  44. {$R-}
  45. function opname(var p: tai): string;
  46. begin
  47. result:=upcase(gas_op2str[taicpu(p).opcode]);
  48. end;
  49. function RefsEqual(const r1, r2: treference): boolean;
  50. begin
  51. RefsEqual :=
  52. (r1.offset = r2.offset) and
  53. (r1.base = r2.base) and
  54. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  55. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  56. (r1.relsymbol = r2.relsymbol) and
  57. (r1.volatility=[]) and
  58. (r2.volatility=[]);
  59. end;
  60. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean;
  61. begin
  62. result := oper1.typ = oper2.typ;
  63. if result then
  64. case oper1.typ of
  65. top_const:
  66. Result:=oper1.val = oper2.val;
  67. top_reg:
  68. Result:=oper1.reg = oper2.reg;
  69. top_ref:
  70. Result:=RefsEqual(oper1.ref^, oper2.ref^);
  71. else
  72. internalerror(2016112401);
  73. end
  74. end;
  75. function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
  76. begin
  77. result :=
  78. (instr.typ = ait_instruction) and
  79. (taicpu(instr).opcode = op) and
  80. ((opsize = []) or (taicpu(instr).opsize in opsize));
  81. end;
  82. function MatchInstruction(const instr : tai;const ops : array of TAsmOp;
  83. const opsize : topsizes) : boolean;
  84. var
  85. op : TAsmOp;
  86. begin
  87. result:=false;
  88. for op in ops do
  89. begin
  90. if (instr.typ = ait_instruction) and
  91. (taicpu(instr).opcode = op) and
  92. ((opsize = []) or (taicpu(instr).opsize in opsize)) then
  93. begin
  94. result:=true;
  95. exit;
  96. end;
  97. end;
  98. end;
  99. function TCpuAsmOptimizer.MaybeRealConstOperSimplify(var p: tai): boolean;
  100. var
  101. tmpint64: int64;
  102. tmpsingle: single;
  103. begin
  104. result:=false;
  105. if (taicpu(p).oper[0]^.typ = top_realconst) then
  106. begin
  107. { if we work with actual integers, turn the operand into one }
  108. if frac(taicpu(p).oper[0]^.val_real) = 0 then
  109. begin
  110. tmpint64:=trunc(taicpu(p).oper[0]^.val_real);
  111. if (high(shortint) >= tmpint64) and (low(shortint) <= tmpint64) then
  112. begin
  113. taicpu(p).opsize := S_B;
  114. taicpu(p).oper[0]^.typ:=top_const;
  115. end
  116. else
  117. if (high(smallint) >= tmpint64) and (low(smallint) <= tmpint64) then
  118. begin
  119. taicpu(p).opsize := S_W;
  120. taicpu(p).oper[0]^.typ:=top_const;
  121. end
  122. else
  123. if (high(longint) >= tmpint64) and (low(longint) <= tmpint64) then
  124. begin
  125. taicpu(p).opsize := S_L;
  126. taicpu(p).oper[0]^.typ:=top_const;
  127. end;
  128. if (taicpu(p).oper[0]^.typ) = top_const then
  129. begin
  130. DebugMsg('Optimizer: FPU real const to integer',p);
  131. taicpu(p).oper[0]^.val:=tmpint64;
  132. result:=true;
  133. end;
  134. end
  135. else
  136. begin
  137. tmpsingle:=taicpu(p).oper[0]^.val_real;
  138. if (taicpu(p).opsize = S_FD) and
  139. ((taicpu(p).oper[0]^.val_real - tmpsingle) = 0.0) then
  140. begin
  141. DebugMsg('Optimizer: FPU real const to lesser precision',p);
  142. taicpu(p).opsize:=S_FS;
  143. result:=true;
  144. end;
  145. end;
  146. end;
  147. end;
  148. function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  149. var
  150. p: taicpu;
  151. begin
  152. if not assigned(hp) or
  153. (hp.typ <> ait_instruction) then
  154. begin
  155. Result := false;
  156. exit;
  157. end;
  158. p := taicpu(hp);
  159. Result :=
  160. (((p.opcode=A_MOVE) or (p.opcode=A_MOVEA) or (p.opcode=A_MVS) or
  161. (p.opcode=A_MVZ) or (p.opcode=A_MOVEQ) or (p.opcode=A_LEA)) and
  162. (p.oper[1]^.typ = top_reg) and
  163. (SuperRegistersEqual(p.oper[1]^.reg,reg)) and
  164. ((p.oper[0]^.typ = top_const) or
  165. ((p.oper[0]^.typ = top_reg) and
  166. not(SuperRegistersEqual(p.oper[0]^.reg,reg))) or
  167. ((p.oper[0]^.typ = top_ref) and
  168. not RegInRef(reg,p.oper[0]^.ref^)))) or
  169. ((p.opcode = A_FMOVE) and
  170. (p.oper[1]^.typ = top_reg) and
  171. (SuperRegistersEqual(p.oper[1]^.reg,reg)) and
  172. ((p.oper[0]^.typ = top_realconst) or
  173. ((p.oper[0]^.typ = top_reg) and
  174. not(SuperRegistersEqual(p.oper[0]^.reg,reg))))) or
  175. ((p.opcode = A_MOVEM) and
  176. (p.oper[1]^.typ = top_regset) and
  177. ((getsupreg(reg) in p.oper[1]^.dataregset) or
  178. (getsupreg(reg) in p.oper[1]^.addrregset))) or
  179. ((p.opcode = A_FMOVEM) and
  180. (p.oper[1]^.typ = top_regset) and
  181. (getsupreg(reg) in p.oper[1]^.fpuregset));
  182. end;
  183. {$ifdef DEBUG_AOPTCPU}
  184. procedure TCpuAsmOptimizer.DebugMsg(const s: string; p : tai);
  185. begin
  186. asml.insertbefore(tai_comment.Create(strpnew(s)), p);
  187. end;
  188. {$else DEBUG_AOPTCPU}
  189. procedure TCpuAsmOptimizer.DebugMsg(const s: string; p : tai);inline;
  190. begin
  191. end;
  192. {$endif DEBUG_AOPTCPU}
  193. function TCpuAsmOptimizer.TryToRemoveTST(var p: tai): boolean;
  194. var
  195. next, next2: tai;
  196. opstr: string[15];
  197. begin
  198. result:=false;
  199. if not((taicpu(p).oper[1]^.typ=top_reg) and isaddressregister(taicpu(p).oper[1]^.reg)) and
  200. GetNextInstruction(p,next) and
  201. MatchInstruction(next,A_TST,[taicpu(p).opsize]) and
  202. MatchOperand(taicpu(p).oper[1]^,taicpu(next).oper[0]^) and
  203. GetNextInstruction(next,next2) and
  204. MatchInstruction(next2,[A_BXX,A_SXX],[S_NO]) and
  205. (taicpu(next2).condition in [C_NE,C_EQ,C_PL,C_MI]) then
  206. begin
  207. opstr:=opname(p);
  208. DebugMsg('Optimizer: '+opstr+', TST, Jxx/Sxx to '+opstr+', Jxx/Sxx',p);
  209. asml.remove(next);
  210. next.free;
  211. result:=true;
  212. end;
  213. end;
  214. function TCpuAsmOptimizer.TryToOptimizeMove(var p: tai): boolean;
  215. var
  216. next, next2: tai;
  217. opstr: string[15];
  218. begin
  219. result:=false;
  220. if (taicpu(p).opcode=A_MOVE) then
  221. begin
  222. result:=TryToRemoveTST(p);
  223. if result then
  224. exit;
  225. end;
  226. if GetNextInstruction(p,next) and
  227. (next.typ = ait_instruction) and
  228. (taicpu(next).opcode = taicpu(p).opcode) and
  229. (taicpu(p).opsize = taicpu(next).opsize) and
  230. (taicpu(p).oper[1]^.typ = top_reg) and
  231. MatchOperand(taicpu(p).oper[1]^,taicpu(next).oper[0]^) then
  232. begin
  233. if not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(next).oper[1]^)) and
  234. RegEndOfLife(taicpu(next).oper[0]^.reg, taicpu(next)) then
  235. begin
  236. opstr:=opname(p);
  237. case taicpu(p).oper[0]^.typ of
  238. top_reg:
  239. { do not optimize away FPU to INT to FPU reg moves. These are used for
  240. to-single-rounding on FPUs which have no FSMOVE/FDMOVE. (KB) }
  241. if not ((taicpu(p).opcode = A_FMOVE) and
  242. (getregtype(taicpu(p).oper[0]^.reg) <> getregtype(taicpu(p).oper[1]^.reg))) then
  243. begin
  244. { move %reg0, %tmpreg; move %tmpreg, <ea> -> move %reg0, <ea> }
  245. taicpu(p).loadOper(1,taicpu(next).oper[1]^);
  246. asml.remove(next);
  247. next.free;
  248. result:=true;
  249. { also remove leftover move %reg0, %reg0, which can occur as the result
  250. of the previous optimization, if %reg0 and %tmpreg was different types
  251. (addr vs. data), so these moves were left in by the cg }
  252. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  253. begin
  254. DebugMsg('Optimizer: '+opstr+' + '+opstr+' removed',p);
  255. GetNextInstruction(p,next);
  256. asml.remove(p);
  257. p.free;
  258. p:=next;
  259. end
  260. else
  261. DebugMsg('Optimizer: '+opstr+' + '+opstr+' to '+opstr+' #1',p)
  262. end;
  263. top_const:
  264. begin
  265. // DebugMsg('Optimizer: '+opstr+' + '+opstr+' to '+opstr+' #2',p);
  266. end;
  267. top_ref:
  268. begin
  269. { move ref, %tmpreg; move %tmpreg, <ea> -> move ref, <ea> }
  270. { we only want to do this when <ea> is a reg or a simple reference }
  271. with taicpu(next).oper[1]^ do
  272. if (taicpu(next).opcode <> A_FMOVE) and
  273. ((typ = top_reg) or
  274. ((typ = top_ref) and
  275. ((ref^.index = NR_NO) or
  276. (ref^.base = NR_NO)) and
  277. (ref^.symbol = nil) and
  278. (ref^.offset = 0))) then
  279. begin
  280. DebugMsg('Optimizer: '+opstr+' + '+opstr+' to '+opstr+' #3',p);
  281. taicpu(p).loadOper(1,taicpu(next).oper[1]^);
  282. asml.remove(next);
  283. next.free;
  284. result:=true;
  285. end;
  286. end;
  287. else
  288. ;
  289. end;
  290. end;
  291. exit;
  292. end;
  293. if GetNextInstruction(p,next) and
  294. (next.typ = ait_instruction) and
  295. GetNextInstruction(next,next2) and
  296. (next2.typ = ait_instruction) and
  297. (taicpu(next).opcode <> taicpu(p).opcode) and
  298. (taicpu(next2).opcode = taicpu(p).opcode) and
  299. (taicpu(p).oper[0]^.typ = top_reg) and
  300. (taicpu(p).oper[1]^.typ = top_reg) and
  301. (getregtype(taicpu(p).oper[0]^.reg) = getregtype(taicpu(p).oper[1]^.reg)) and
  302. MatchOperand(taicpu(p).oper[1]^,taicpu(next2).oper[0]^) and
  303. MatchOperand(taicpu(next2).oper[1]^,taicpu(p).oper[0]^) and
  304. (taicpu(p).opsize = taicpu(next2).opsize) and
  305. ((taicpu(p).opcode = A_FMOVE) or
  306. (taicpu(p).opsize = taicpu(next).opsize)) then
  307. begin
  308. opstr:=opname(p);
  309. if not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(next2).oper[1]^)) and
  310. not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(next).oper[0]^)) and
  311. RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(next2)) then
  312. begin
  313. { move %reg0, %tmpreg
  314. op ???, %tmpreg
  315. move %tmpreg, %reg0
  316. to:
  317. op ???, %reg0 }
  318. if MatchOperand(taicpu(p).oper[1]^,taicpu(next).oper[taicpu(next).ops-1]^) then
  319. begin
  320. {
  321. Disabled, because it breaks some tests... :( (KB)
  322. DebugMsg('Optimizer: '+opstr+' + OP + '+opstr+' to OP #1',next);
  323. taicpu(next).loadOper(taicpu(next).ops-1,taicpu(p).oper[0]^);
  324. asml.remove(p);
  325. asml.remove(next2);
  326. p.free;
  327. next2.free;
  328. result:=true;
  329. }
  330. end;
  331. end;
  332. end;
  333. end;
  334. function TCpuAsmOptimizer.OptPass1LEA(var p: tai): Boolean;
  335. var
  336. next: tai;
  337. begin
  338. Result:=false;
  339. { LEA (Ax),Ax is a NOP if src and dest reg is equal, so remove it. }
  340. if not assigned(taicpu(p).oper[0]^.ref^.symbol) and
  341. (((taicpu(p).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
  342. (taicpu(p).oper[0]^.ref^.index = NR_NO)) or
  343. ((taicpu(p).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  344. (taicpu(p).oper[0]^.ref^.base = NR_NO))) and
  345. (taicpu(p).oper[0]^.ref^.offset = 0) then
  346. begin
  347. DebugMsg('Optimizer: LEA 0(Ax),Ax removed',p);
  348. GetNextInstruction(p,next);
  349. asml.remove(p);
  350. p.free;
  351. p:=next;
  352. result:=true;
  353. exit;
  354. end;
  355. if (taicpu(p).oper[1]^.reg=NR_A7) and
  356. (taicpu(p).oper[0]^.ref^.base=NR_A7) and
  357. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  358. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  359. (taicpu(p).oper[0]^.ref^.direction=dir_none) and
  360. GetNextInstruction(p,next) and
  361. MatchInstruction(next,A_MOVEM,[S_L]) and
  362. MatchOpType(taicpu(next),top_regset,top_ref) and
  363. ((taicpu(p).oper[0]^.ref^.offset=-(PopCnt(Byte(taicpu(next).oper[0]^.dataregset))+PopCnt(Byte(taicpu(next).oper[0]^.addrregset)))*4)) and
  364. (taicpu(next).oper[1]^.ref^.base=NR_A7) and
  365. (taicpu(next).oper[1]^.ref^.index=NR_NO) and
  366. (taicpu(next).oper[1]^.ref^.symbol=nil) and
  367. (taicpu(next).oper[1]^.ref^.direction=dir_none) and
  368. not (current_settings.cputype in cpu_coldfire) then
  369. begin
  370. DebugMsg('Optimizer: LEA, MOVE(M) to MOVE(M) predecremented',p);
  371. taicpu(next).oper[1]^.ref^.direction:=dir_dec;
  372. asml.remove(p);
  373. p.free;
  374. p:=next;
  375. result:=true;
  376. exit;
  377. end;
  378. end;
  379. function TCpuAsmOptimizer.OptPass1MOVEM(var p: tai): Boolean;
  380. var
  381. next: tai;
  382. begin
  383. Result:=false;
  384. if MatchOpType(taicpu(p),top_ref,top_regset) and
  385. (taicpu(p).oper[0]^.ref^.base=NR_A7) and
  386. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  387. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  388. (taicpu(p).oper[0]^.ref^.direction=dir_none) and
  389. GetNextInstruction(p,next) and
  390. MatchInstruction(next,A_LEA,[S_NO]) and
  391. (taicpu(next).oper[1]^.reg=NR_A7) and
  392. (taicpu(next).oper[0]^.ref^.base=NR_A7) and
  393. (taicpu(next).oper[0]^.ref^.index=NR_NO) and
  394. (taicpu(next).oper[0]^.ref^.symbol=nil) and
  395. (taicpu(next).oper[0]^.ref^.direction=dir_none) and
  396. ((taicpu(next).oper[0]^.ref^.offset=(PopCnt(Byte(taicpu(p).oper[1]^.dataregset))+PopCnt(Byte(taicpu(p).oper[1]^.addrregset)))*4)) and
  397. not (current_settings.cputype in cpu_coldfire) then
  398. begin
  399. DebugMsg('Optimizer: MOVE(M), LEA to MOVE(M) postincremented',p);
  400. taicpu(p).oper[0]^.ref^.direction:=dir_inc;
  401. asml.remove(next);
  402. next.free;
  403. result:=true;
  404. exit;
  405. end;
  406. end;
  407. function TCpuAsmOptimizer.OptPass1Bitwise(var p: tai): Boolean;
  408. begin
  409. Result:=TryToRemoveTST(p);
  410. end;
  411. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  412. var
  413. next: tai;
  414. tmpref: treference;
  415. begin
  416. result:=false;
  417. case p.typ of
  418. ait_instruction:
  419. begin
  420. //asml.insertbefore(tai_comment.Create(strpnew('pass1 called for instr')), p);
  421. case taicpu(p).opcode of
  422. A_MOVE:
  423. result:=TryToOptimizeMove(p);
  424. A_MOVEM:
  425. result:=OptPass1MOVEM(p);
  426. A_LEA:
  427. result:=OptPass1LEA(p);
  428. { Bitwise operations }
  429. A_AND,A_OR,A_EOR:
  430. result:=OptPass1Bitwise(p);
  431. { Address register sub/add can be replaced with ADDQ/SUBQ or LEA if the value is in the
  432. SmallInt range, which is shorter to encode and faster to execute on most 68k }
  433. A_SUB,A_SUBA,A_ADD,A_ADDA:
  434. if (taicpu(p).oper[1]^.typ = top_reg) and isaddressregister(taicpu(p).oper[1]^.reg) and
  435. (taicpu(p).oper[0]^.typ = top_const) then
  436. begin
  437. if isvalueforaddqsubq(taicpu(p).oper[0]^.val) then
  438. begin
  439. DebugMsg('Optimizer: SUB/ADD #val,Ax to SUBQ/ADDQ',p);
  440. taicpu(p).opsize:=S_L; // this is safe, because we're targetting an address reg
  441. if taicpu(p).opcode in [A_ADD,A_ADDA] then
  442. taicpu(p).opcode:=A_ADDQ
  443. else
  444. taicpu(p).opcode:=A_SUBQ;
  445. result:=true;
  446. end
  447. else
  448. if isvalue16bit(abs(taicpu(p).oper[0]^.val)) then
  449. begin
  450. DebugMsg('Optimizer: SUB/ADD #val,Ax to LEA val(Ax),Ax',p);
  451. if (taicpu(p).opcode=A_SUB) or (taicpu(p).opcode=A_SUBA) then
  452. reference_reset_base(tmpref,taicpu(p).oper[1]^.reg,-taicpu(p).oper[0]^.val,ctempposinvalid,0,[])
  453. else
  454. reference_reset_base(tmpref,taicpu(p).oper[1]^.reg,taicpu(p).oper[0]^.val,ctempposinvalid,0,[]);
  455. taicpu(p).opcode:=A_LEA;
  456. taicpu(p).opsize:=S_NO;
  457. taicpu(p).loadref(0,tmpref);
  458. result:=true;
  459. end;
  460. end
  461. else
  462. result:=TryToRemoveTST(p);
  463. A_SUBQ,A_ADDQ:
  464. result:=TryToRemoveTST(p);
  465. { MOVEA #0,Ax to SUBA Ax,Ax, because it's shorter }
  466. A_MOVEA:
  467. if (taicpu(p).oper[0]^.typ = top_const) and
  468. (taicpu(p).oper[0]^.val = 0) then
  469. begin
  470. DebugMsg('Optimizer: MOVEA #0,Ax to SUBA Ax,Ax',p);
  471. taicpu(p).opcode:=A_SUBA;
  472. taicpu(p).opsize:=S_L; { otherwise it will be .W -> BOOM }
  473. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  474. result:=true;
  475. end;
  476. { CLR.L Dx on a 68000 is slower than MOVEQ #0,Dx }
  477. A_CLR:
  478. if (current_settings.cputype in [cpu_mc68000]) and
  479. (taicpu(p).oper[0]^.typ = top_reg) and
  480. (taicpu(p).opsize = S_L) and
  481. isintregister(taicpu(p).oper[0]^.reg) then
  482. begin
  483. //DebugMsg('Optimizer: CLR.L Dx to MOVEQ #0,Dx',p);
  484. taicpu(p).opcode:=A_MOVEQ;
  485. taicpu(p).loadoper(1,taicpu(p).oper[0]^);
  486. taicpu(p).loadconst(0,0);
  487. taicpu(p).ops:=2;
  488. result:=true;
  489. end;
  490. A_JSR:
  491. begin
  492. if (cs_opt_level4 in current_settings.optimizerswitches) and
  493. GetNextInstruction(p,next) and
  494. MatchInstruction(next,A_RTS,[S_NO]) and
  495. { play safe: if any parameter is pushed on the stack, we cannot to this optimization
  496. as the bottom stack element might be a parameter and not the return address as it is expected
  497. after a call (which we simulate by a jmp)
  498. Actually, as in this case the stack pointer is no used as a frame pointer and
  499. there will be more instructions to restore the stack frame before jsr, so this
  500. is unlikedly to happen }
  501. (current_procinfo.maxpushedparasize=0) then
  502. begin
  503. DebugMsg('Optimizer: JSR, RTS to JMP',p);
  504. taicpu(p).opcode:=A_JMP;
  505. asml.remove(next);
  506. next.free;
  507. result:=true;
  508. end;
  509. end;
  510. { CMP #0,<ea> equals to TST <ea>, just shorter and TST is more flexible anyway }
  511. A_CMP,A_CMPI:
  512. if (taicpu(p).oper[0]^.typ = top_const) and
  513. (taicpu(p).oper[0]^.val = 0) then
  514. begin
  515. DebugMsg('Optimizer: CMP #0 to TST',p);
  516. taicpu(p).opcode:=A_TST;
  517. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  518. taicpu(p).clearop(1);
  519. taicpu(p).ops:=1;
  520. result:=true;
  521. end;
  522. A_FCMP:
  523. if (taicpu(p).oper[0]^.typ = top_realconst) then
  524. begin
  525. if (taicpu(p).oper[0]^.val_real = 0.0) then
  526. begin
  527. DebugMsg('Optimizer: FCMP #0.0 to FTST',p);
  528. taicpu(p).opcode:=A_FTST;
  529. taicpu(p).opsize:=S_FX;
  530. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  531. taicpu(p).clearop(1);
  532. taicpu(p).ops:=1;
  533. result:=true;
  534. end
  535. else
  536. result:=result or MaybeRealConstOperSimplify(p);
  537. end;
  538. A_FMOVE,A_FSMOVE,A_FDMOVE,
  539. A_FADD,A_FSADD,A_FDADD,A_FSUB,A_FSSUB,A_FDSUB,
  540. A_FMUL,A_FSMUL,A_FDMUL,A_FDIV,A_FSDIV,A_FDDIV,
  541. A_FSGLMUL,A_FSGLDIV:
  542. begin
  543. if (taicpu(p).opcode = A_FMOVE) and TryToOptimizeMove(p) then
  544. begin
  545. result:=true;
  546. exit;
  547. end;
  548. result:=result or MaybeRealConstOperSimplify(p);
  549. end;
  550. else
  551. ;
  552. end;
  553. end;
  554. else
  555. ;
  556. end;
  557. end;
  558. begin
  559. casmoptimizer:=TCpuAsmOptimizer;
  560. end.