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aoptcpu.pas
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0cd70844f1
+ take into account the fact that lea doesn't read the segment register of its
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8 years ago |
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aoptcpub.pas
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3c2dab9878
* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same
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9 years ago |
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aoptcpud.pas
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3c2dab9878
* i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same
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9 years ago |
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cgcpu.pas
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af235cae86
* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr
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8 years ago |
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cpubase.inc
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bfbb0c5b9d
* optimize mov/lea
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11 years ago |
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cpuelf.pas
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901275b4a1
Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen).
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10 years ago |
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cpuinfo.pas
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5f87ac5d47
+ added 486 to the list of supported CPUs on the i8086 and i386 targets
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9 years ago |
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cpunode.pas
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a0efde8167
* automatically generate necessary indirect symbols when a new assembler
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9 years ago |
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cpupara.pas
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4c68ea1000
* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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8 years ago |
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cpupi.pas
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880d438704
* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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8 years ago |
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cputarg.pas
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4431ba2c08
merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run.
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11 years ago |
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hlcgcpu.pas
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a25ebbba3e
+ added volatility information to all memory references
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8 years ago |
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i386att.inc
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56252d59f0
+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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8 years ago |
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i386atts.inc
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870fda34d5
* x86 AT&T reader and writer: cleaned up usage of attsufMM suffix:
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8 years ago |
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i386int.inc
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56252d59f0
+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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8 years ago |
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i386nop.inc
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133fcb5ab2
* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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8 years ago |
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i386op.inc
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56252d59f0
+ support for the PREFETCHTW1 instruction based on a patch by Emelyanov Roman, resolves #30933
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8 years ago |
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i386prop.inc
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af48d176ec
+ precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions
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8 years ago |
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i386tab.inc
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133fcb5ab2
* Fixed VMOVQ instruction encoding, now assembles correctly also in 32-bit code.
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8 years ago |
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n386add.pas
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a25ebbba3e
+ added volatility information to all memory references
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8 years ago |
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n386cal.pas
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f5f895e2a3
syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed
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8 years ago |
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n386flw.pas
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a25ebbba3e
+ added volatility information to all memory references
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8 years ago |
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n386inl.pas
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66e82f1655
+ i386: generate optimized code for 64-bit arithmetic shifts by constant amount. Shifts by 63 and by less than 32 take just two instructions, shifts by 32..62 bits are done with 3 instructions.
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11 years ago |
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n386ld.pas
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3c6aa91a96
* factored out the loading of threadvars in its own method, and put the
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10 years ago |
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n386mat.pas
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af235cae86
* use TEST CL,32 instead of TEST ECX,32 in the beginning of a 64-bit shl/shr
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8 years ago |
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n386mem.pas
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338c064beb
* moved x86-specific tpointerdef functionality to architecture-specific
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11 years ago |
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n386set.pas
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d0db391d7c
* cleanup of unused units
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12 years ago |
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r386ari.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386att.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386con.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386dwrf.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386int.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386iri.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386nasm.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386nor.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386nri.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386num.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386ot.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386rni.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386sri.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386stab.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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r386std.inc
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c8487c4150
+ added individual bits of the x86 flags register as subregisters
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8 years ago |
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ra386att.pas
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757ed4e8d3
* standard assembler reader for i386
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20 years ago |
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ra386int.pas
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6c6bf452ca
* Fixed level 2 comment warnings.
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17 years ago |
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rgcpu.pas
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b7fe6797bf
Merged revisions 2921-2922,2925 via svnmerge from
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19 years ago |
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symcpu.pas
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f402b0d7df
* changed getpointerdef() into a tpointerdef.getreusable() class method
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10 years ago |
nickysn
af48d176ec
+ precise flag information for the ucomiss,ucomisd,vucomiss and vucomisd x86 instructions