cgcpu.pas 61 KB

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  1. {
  2. Copyright (c) 2014 by Jonas Maebe
  3. This unit implements the code generator for Xtensa
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit cgcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. globtype,parabase,
  22. cgbase,cgutils,cgobj,
  23. aasmbase,aasmtai,aasmdata,aasmcpu,
  24. cpubase,cpuinfo,
  25. node,symconst,SymType,symdef,
  26. rgcpu,
  27. cg64f32;
  28. type
  29. tcgcpu=class(tcg)
  30. private
  31. procedure fixref(list : TAsmList; var ref : treference);
  32. procedure g_concatcopy_move(list : tasmlist; const Source,dest : treference; len : tcgint);
  33. public
  34. procedure init_register_allocators;override;
  35. procedure done_register_allocators;override;
  36. { move instructions }
  37. procedure a_load_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister);override;
  38. procedure a_load_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister;const ref: TReference);override;
  39. procedure a_load_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: TReference; reg: tregister);override;
  40. procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; reg: tregister);override;
  41. procedure a_loadaddr_ref_reg(list: TAsmList; const ref: TReference; r: tregister);override;
  42. procedure a_op_reg_reg(list: TAsmList; op: topcg; size: tcgsize; src, dst: tregister);override;
  43. procedure a_op_const_reg(list: TAsmList; op: topcg; size: tcgsize; a: tcgint; reg: tregister);override;
  44. procedure a_op_reg_reg_reg(list: TAsmList; op: topcg; size: tcgsize; src1, src2, dst: tregister);override;
  45. procedure a_op_const_reg_reg(list : TAsmList; op : TOpCg; size : tcgsize; a : tcgint; src,dst : tregister);override;
  46. procedure a_call_name(list:TAsmList;const s:string; weak: boolean);override;
  47. procedure a_call_reg(list:TAsmList;Reg:tregister);override;
  48. procedure a_jmp_name(list: TAsmList; const s: string);override;
  49. procedure a_jmp_flags(list: TAsmList; const f: TResFlags; l: tasmlabel);override;
  50. procedure g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);override;
  51. procedure g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean);override;
  52. { comparison operations }
  53. procedure a_cmp_const_reg_label(list: TAsmList; size: tcgsize; cmp_op: topcmp; a: tcgint; reg: tregister; l: tasmlabel); override;
  54. procedure a_cmp_reg_reg_label(list: TAsmList; size: tcgsize; cmp_op: topcmp; reg1, reg2: tregister; l: tasmlabel);override;
  55. procedure a_jmp_always(list: TAsmList; l: TAsmLabel);override;
  56. procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; srcsize, dstsize: TCGSize; src, dst: TRegister);override;
  57. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: tresflags; reg: TRegister);override;
  58. procedure g_concatcopy(list : TAsmList; const source,dest : treference; len : tcgint);override;
  59. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister);override;
  60. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister);override;
  61. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);override;
  62. procedure a_loadfpu_intreg_reg(list: TAsmList; fromsize, tosize: tcgsize; intreg, fpureg: tregister);override;
  63. procedure a_loadfpu_reg_intreg(list: TAsmList; fromsize, tosize: tcgsize; fpureg, intreg: tregister);override;
  64. procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
  65. procedure g_overflowcheck(list: TAsmList; const Loc:tlocation; def:tdef);override;
  66. function create_data_entry(symbol: TAsmSymbol; offset: asizeint): TAsmLabel;
  67. end;
  68. tcg64fxtensa = class(tcg64f32)
  69. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  70. procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
  71. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  72. procedure a_op64_reg_reg_reg(list : TAsmList; op : TOpCG;size : tcgsize; regsrc1,regsrc2,regdst : tregister64);override;
  73. //procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  74. //procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  75. //procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  76. //procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  77. //procedure a_loadmm_intreg64_reg(list: TAsmList; mmsize: tcgsize; intreg: tregister64; mmreg: tregister);override;
  78. //procedure a_loadmm_reg_intreg64(list: TAsmList; mmsize: tcgsize; mmreg: tregister; intreg: tregister64);override;
  79. end;
  80. procedure create_codegen;
  81. const
  82. TOpCG2AsmOp: array[topcg] of TAsmOp = (
  83. A_NONE,A_MOV,A_ADD,A_AND,A_NONE,A_NONE,A_MULL,A_MULL,A_NEG,A_NONE,A_OR,A_SRA,A_SLL,A_SRL,A_SUB,A_XOR,A_NONE,A_NONE
  84. );
  85. {
  86. );TOpCG2AsmOpReg: array[topcg] of TAsmOp = (
  87. A_NONE,A_MOV,A_ADD,A_AND,A_UDIV,A_SDIV,A_MUL,A_MUL,A_NEG,A_MVN,A_ORR,A_ASRV,A_LSLV,A_LSRV,A_SUB,A_EOR,A_NONE,A_RORV
  88. );
  89. TOpCG2AsmOpImm: array[topcg] of TAsmOp = (
  90. A_NONE,A_MOV,A_ADD,A_AND,A_UDIV,A_SDIV,A_MUL,A_MUL,A_NEG,A_MVN,A_ORR,A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_NONE,A_ROR
  91. );
  92. TOpCmp2AsmCond: array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_GT,
  93. C_LT,C_GE,C_LE,C_NE,C_LS,C_CC,C_CS,C_HI
  94. );
  95. }
  96. implementation
  97. uses
  98. globals,verbose,systems,cutils,
  99. paramgr,fmodule,
  100. symtable,symsym,
  101. tgobj,
  102. procinfo,cpupi;
  103. const
  104. TOpCmp2AsmCond: array[TOpCmp] of TAsmCond = (
  105. C_None,
  106. C_EQ,
  107. C_None,
  108. C_LT,
  109. C_GE,
  110. C_None,
  111. C_NE,
  112. C_None,
  113. C_LTU,
  114. C_GEU,
  115. C_None
  116. );
  117. procedure tcgcpu.init_register_allocators;
  118. begin
  119. inherited init_register_allocators;
  120. if target_info.abi = abi_xtensa_call0 then
  121. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  122. [RS_A2,RS_A3,RS_A4,RS_A5,RS_A6,RS_A7,{RS_A8,}RS_A9,
  123. RS_A10,RS_A11,RS_A12,RS_A13,RS_A14{,RS_A15}],first_int_imreg,[])
  124. else
  125. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  126. [RS_A2,RS_A3,RS_A4,RS_A5,RS_A6,RS_A7,RS_A8,RS_A9,
  127. RS_A10,RS_A11,RS_A12,RS_A13,RS_A14,RS_A15],first_int_imreg,[]);
  128. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  129. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,
  130. RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15],first_fpu_imreg,[]);
  131. rg[R_SPECIALREGISTER]:=trgcpu.create(R_SPECIALREGISTER,R_SUBNONE,
  132. [RS_B0,RS_B1,RS_B2,RS_B3,RS_B4,RS_B5,RS_B6,RS_B7,RS_B8,RS_B9,
  133. RS_B10,RS_B11,RS_B12,RS_B13,RS_B14,RS_B15],first_flag_imreg,[]);
  134. end;
  135. procedure tcgcpu.done_register_allocators;
  136. begin
  137. rg[R_INTREGISTER].free;
  138. rg[R_FPUREGISTER].free;
  139. rg[R_SPECIALREGISTER].free;
  140. inherited done_register_allocators;
  141. end;
  142. procedure tcgcpu.a_load_reg_reg(list : TAsmList; fromsize,tosize : tcgsize;
  143. reg1,reg2 : tregister);
  144. var
  145. conv_done : Boolean;
  146. instr : taicpu;
  147. begin
  148. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  149. internalerror(2020030710);
  150. conv_done:=false;
  151. if tosize<>fromsize then
  152. begin
  153. conv_done:=true;
  154. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  155. fromsize:=tosize;
  156. case fromsize of
  157. OS_8:
  158. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8));
  159. OS_S8:
  160. begin
  161. if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
  162. list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7))
  163. else
  164. begin
  165. list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,24));
  166. list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,24));
  167. end;
  168. if tosize=OS_16 then
  169. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16));
  170. end;
  171. OS_16:
  172. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16));
  173. OS_S16:
  174. if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
  175. list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15))
  176. else
  177. begin
  178. list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,16));
  179. list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,16));
  180. end;
  181. else
  182. conv_done:=false;
  183. end;
  184. end;
  185. if not conv_done and (reg1<>reg2) then
  186. begin
  187. { same size, only a register mov required }
  188. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  189. list.Concat(instr);
  190. { Notify the register allocator that we have written a move instruction so
  191. it can try to eliminate it. }
  192. add_move_instruction(instr);
  193. end;
  194. end;
  195. procedure tcgcpu.a_load_reg_ref(list : TAsmList; fromsize,tosize : tcgsize;
  196. reg : tregister; const ref : TReference);
  197. var
  198. op: TAsmOp;
  199. href : treference;
  200. begin
  201. if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
  202. FromSize := ToSize;
  203. case tosize of
  204. { signed integer registers }
  205. OS_8,
  206. OS_S8:
  207. op:=A_S8I;
  208. OS_16,
  209. OS_S16:
  210. op:=A_S16I;
  211. OS_32,
  212. OS_S32:
  213. op:=A_S32I;
  214. else
  215. InternalError(2020030804);
  216. end;
  217. href:=ref;
  218. if assigned(href.symbol) or
  219. (href.index<>NR_NO) or
  220. ((op=A_S8I) and ((href.offset<0) or (href.offset>255))) or
  221. ((op=A_S16I) and ((href.offset<0) or (href.offset>510) or (href.offset mod 2<>0))) or
  222. ((op=A_S32I) and ((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) then
  223. fixref(list,href);
  224. list.concat(taicpu.op_reg_ref(op,reg,href));
  225. end;
  226. procedure tcgcpu.a_load_ref_reg(list : TAsmList; fromsize,tosize : tcgsize;
  227. const ref : TReference; reg : tregister);
  228. var
  229. href: treference;
  230. op: TAsmOp;
  231. tmpreg: TRegister;
  232. begin
  233. case fromsize of
  234. OS_8: op:=A_L8UI;
  235. OS_16: op:=A_L16UI;
  236. OS_S8: op:=A_L8UI;
  237. OS_S16: op:=A_L16SI;
  238. OS_64,OS_S64, { This only happens if tosize is smaller than fromsize }
  239. { We can therefore only consider the low 32-bit of the 64bit value }
  240. OS_32,
  241. OS_S32: op:=A_L32I;
  242. else
  243. internalerror(2020030805);
  244. end;
  245. href:=ref;
  246. if assigned(href.symbol) or
  247. (href.index<>NR_NO) or
  248. ((op=A_L8UI) and ((href.offset<0) or (href.offset>255))) or
  249. ((op in [A_L16SI,A_L16UI]) and ((href.offset<0) or (href.offset>510) or (href.offset mod 2<>0))) or
  250. ((op=A_L32I) and ((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) or
  251. ((href.base=NR_NO) and (href.index=NR_NO)) then
  252. fixref(list,href);
  253. list.concat(taicpu.op_reg_ref(op,reg,href));
  254. if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then
  255. if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
  256. list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7))
  257. else
  258. begin
  259. list.concat(taicpu.op_reg_reg_const(A_SLLI,reg,reg,24));
  260. list.concat(taicpu.op_reg_reg_const(A_SRAI,reg,reg,24));
  261. end;
  262. if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
  263. a_load_reg_reg(list,fromsize,tosize,reg,reg);
  264. end;
  265. procedure tcgcpu.a_load_const_reg(list : TAsmList; size : tcgsize;
  266. a : tcgint; reg : tregister);
  267. var
  268. hr : treference;
  269. l : TAsmLabel;
  270. begin
  271. if (a>=-2048) and (a<=2047) then
  272. list.Concat(taicpu.op_reg_const(A_MOVI,reg,a))
  273. else
  274. begin
  275. reference_reset(hr,4,[]);
  276. hr.symbol:=create_data_entry(nil,longint(a));
  277. list.concat(taicpu.op_reg_ref(A_L32R,reg,hr));
  278. end;
  279. end;
  280. procedure tcgcpu.fixref(list : TAsmList;var ref : treference);
  281. var
  282. tmpreg, tmpreg2 : tregister;
  283. tmpref : treference;
  284. l : tasmlabel;
  285. begin
  286. { create consts entry }
  287. if assigned(ref.symbol) or (ref.offset<-2048) or (ref.offset>2047) or
  288. ((ref.base=NR_NO) and (ref.index=NR_NO)) then
  289. begin
  290. reference_reset(tmpref,4,[]);
  291. tmpreg:=NR_NO;
  292. { load consts entry }
  293. tmpreg:=getintregister(list,OS_INT);
  294. if ref.symbol=nil then
  295. a_load_const_reg(list,OS_ADDR,ref.offset,tmpreg)
  296. else
  297. begin
  298. tmpref.symbol:=create_data_entry(ref.symbol,ref.offset);
  299. list.concat(taicpu.op_reg_ref(A_L32R,tmpreg,tmpref));
  300. end;
  301. if ref.base<>NR_NO then
  302. begin
  303. if ref.index<>NR_NO then
  304. begin
  305. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  306. ref.base:=tmpreg;
  307. end
  308. else
  309. ref.index:=tmpreg;
  310. end
  311. else
  312. ref.base:=tmpreg;
  313. end
  314. else if ref.offset<>0 then
  315. begin
  316. tmpreg:=getintregister(list,OS_INT);
  317. if (ref.offset>=-128) and (ref.offset<=127) then
  318. begin
  319. list.concat(taicpu.op_reg_reg_const(A_ADDI,tmpreg,ref.base,ref.offset));
  320. ref.base:=tmpreg;
  321. end
  322. else
  323. begin
  324. list.concat(taicpu.op_reg_const(A_MOVI,tmpreg,ref.offset));
  325. if ref.base<>NR_NO then
  326. begin
  327. if ref.index<>NR_NO then
  328. begin
  329. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  330. ref.base:=tmpreg;
  331. end
  332. else
  333. ref.index:=tmpreg;
  334. end
  335. else
  336. ref.base:=tmpreg;
  337. end;
  338. end;
  339. if ref.index<>NR_NO then
  340. begin
  341. if ref.base<>NR_NO then
  342. begin
  343. tmpreg:=getintregister(list,OS_INT);
  344. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,ref.index));
  345. ref.base:=tmpreg;
  346. end
  347. else
  348. ref.base:=ref.index;
  349. ref.index:=NR_NO;
  350. end;
  351. ref.offset:=0;
  352. ref.symbol:=nil;
  353. end;
  354. procedure tcgcpu.a_loadaddr_ref_reg(list : TAsmList;
  355. const ref : TReference; r : tregister);
  356. var
  357. b : byte;
  358. tmpref : treference;
  359. instr : taicpu;
  360. begin
  361. tmpref:=ref;
  362. { Be sure to have a base register }
  363. if tmpref.base=NR_NO then
  364. begin
  365. tmpref.base:=tmpref.index;
  366. tmpref.index:=NR_NO;
  367. end;
  368. if assigned(tmpref.symbol) then
  369. fixref(list,tmpref);
  370. { expect a base here if there is an index }
  371. if (tmpref.base=NR_NO) and (tmpref.index<>NR_NO) then
  372. internalerror(200312022);
  373. if tmpref.index<>NR_NO then
  374. begin
  375. a_op_reg_reg_reg(list,OP_ADD,OS_ADDR,tmpref.base,tmpref.index,r);
  376. if tmpref.offset<>0 then
  377. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,r,r);
  378. end
  379. else
  380. begin
  381. if tmpref.base=NR_NO then
  382. a_load_const_reg(list,OS_ADDR,tmpref.offset,r)
  383. else
  384. if tmpref.offset<>0 then
  385. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,tmpref.base,r)
  386. else
  387. begin
  388. instr:=taicpu.op_reg_reg(A_MOV,r,tmpref.base);
  389. list.concat(instr);
  390. add_move_instruction(instr);
  391. end;
  392. end;
  393. end;
  394. procedure tcgcpu.a_op_reg_reg(list : TAsmList; op : topcg; size : tcgsize; src,dst : tregister);
  395. var
  396. tmpreg : TRegister;
  397. begin
  398. if op = OP_NEG then
  399. begin
  400. list.concat(taicpu.op_reg_reg(A_NEG,dst,src));
  401. maybeadjustresult(list,OP_NEG,size,dst);
  402. end
  403. else if op = OP_NOT then
  404. begin
  405. tmpreg:=getintregister(list,size);
  406. list.concat(taicpu.op_reg_const(A_MOVI,tmpreg,-1));
  407. list.concat(taicpu.op_reg_reg_reg(A_XOR,dst,tmpreg,src));
  408. maybeadjustresult(list,OP_NOT,size,dst);
  409. end
  410. else
  411. a_op_reg_reg_reg(list,op,size,src,dst,dst);
  412. end;
  413. procedure tcgcpu.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
  414. var
  415. l1 : longint;
  416. tmpreg : TRegister;
  417. begin
  418. optimize_op_const(size, op, a);
  419. case op of
  420. OP_NONE:
  421. begin
  422. if src <> dst then
  423. a_load_reg_reg(list, size, size, src, dst);
  424. exit;
  425. end;
  426. OP_MOVE:
  427. begin
  428. a_load_const_reg(list, size, a, dst);
  429. exit;
  430. end;
  431. else
  432. ;
  433. end;
  434. { there could be added some more sophisticated optimizations }
  435. if (op in [OP_IMUL,OP_IDIV]) and (a=-1) then
  436. a_op_reg_reg(list,OP_NEG,size,src,dst)
  437. { we do this here instead in the peephole optimizer because
  438. it saves us a register }
  439. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) then
  440. a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
  441. else if (op=OP_ADD) and (a>=-128) and (a<=127) then
  442. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,a))
  443. else if (op=OP_ADD) and (a>=-128-32768) and (a<=127+32512) then
  444. begin
  445. {$ifdef EXTDEBUG}
  446. list.concat(tai_comment.Create(strpnew('Value: '+tostr(a))));
  447. {$endif EXTDEBUG}
  448. list.concat(taicpu.op_reg_reg_const(A_ADDMI,dst,src,Smallint((a+128) and $ff00)));
  449. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,dst,Shortint(a and $ff)));
  450. end
  451. else if (op=OP_SUB) and (a>=-127) and (a<=128) then
  452. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,-a))
  453. else if (op=OP_SUB) and (a>=-127-32512) and (a<=128+32768) then
  454. begin
  455. {$ifdef EXTDEBUG}
  456. list.concat(tai_comment.Create(strpnew('Value: '+tostr(a))));
  457. {$endif EXTDEBUG}
  458. a:=-a;
  459. list.concat(taicpu.op_reg_reg_const(A_ADDMI,dst,src,Smallint((a+128) and $ff00)));
  460. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,dst,Shortint(a and $ff)));
  461. end
  462. else if (op=OP_SHL) and (a>=1) and (a<=31) then
  463. list.concat(taicpu.op_reg_reg_const(A_SLLI,dst,src,a))
  464. else if (op=OP_SAR) and (a>=0) and (a<=31) then
  465. list.concat(taicpu.op_reg_reg_const(A_SRAI,dst,src,a))
  466. else if (op=OP_SHR) and (a>=0) and (a<=15) then
  467. list.concat(taicpu.op_reg_reg_const(A_SRLI,dst,src,a))
  468. else if (op=OP_SHR) and (a>15) and (a<=31) then
  469. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,dst,src,a,32-a))
  470. else if (op=OP_AND) and (63-BsrQWord(qword(a))+PopCnt(QWord(a))=64) and (PopCnt(QWord(a))<=16) then
  471. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,dst,src,0,PopCnt(QWord(a))))
  472. else
  473. begin
  474. tmpreg:=getintregister(list,size);
  475. a_load_const_reg(list,size,a,tmpreg);
  476. a_op_reg_reg_reg(list,op,size,tmpreg,src,dst);
  477. end;
  478. maybeadjustresult(list,op,size,dst);
  479. end;
  480. procedure tcgcpu.a_op_const_reg(list : TAsmList; op : topcg; size : tcgsize; a : tcgint; reg : tregister);
  481. begin
  482. a_op_const_reg_reg(list,op,size,a,reg,reg);
  483. end;
  484. procedure tcgcpu.a_op_reg_reg_reg(list : TAsmList; op : topcg;
  485. size : tcgsize; src1,src2,dst : tregister);
  486. var
  487. tmpreg : TRegister;
  488. begin
  489. if op=OP_NOT then
  490. begin
  491. tmpreg:=getintregister(list,size);
  492. list.concat(taicpu.op_reg_const(A_MOVI,tmpreg,-1));
  493. maybeadjustresult(list,op,size,dst);
  494. end
  495. else if op=OP_NEG then
  496. begin
  497. list.concat(taicpu.op_reg_reg(A_NEG,dst,src1));
  498. maybeadjustresult(list,op,size,dst);
  499. end
  500. else if op in [OP_SAR,OP_SHL,OP_SHR] then
  501. begin
  502. if op=OP_SHL then
  503. list.concat(taicpu.op_reg(A_SSL,src1))
  504. else
  505. list.concat(taicpu.op_reg(A_SSR,src1));
  506. list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dst,src2));
  507. maybeadjustresult(list,op,size,dst);
  508. end
  509. else
  510. case op of
  511. OP_MOVE:
  512. a_load_reg_reg(list,size,size,src1,dst);
  513. else
  514. begin
  515. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1));
  516. maybeadjustresult(list,op,size,dst);
  517. end;
  518. end;
  519. end;
  520. procedure tcgcpu.a_call_name(list : TAsmList; const s : string;
  521. weak : boolean);
  522. begin
  523. if not weak then
  524. list.concat(taicpu.op_sym(txtensaprocinfo(current_procinfo).callins,current_asmdata.RefAsmSymbol(s,AT_FUNCTION)))
  525. else
  526. list.concat(taicpu.op_sym(txtensaprocinfo(current_procinfo).callins,current_asmdata.WeakRefAsmSymbol(s,AT_FUNCTION)));
  527. end;
  528. procedure tcgcpu.a_call_reg(list : TAsmList; Reg : tregister);
  529. begin
  530. list.concat(taicpu.op_reg(txtensaprocinfo(current_procinfo).callxins,reg));
  531. end;
  532. procedure tcgcpu.a_jmp_name(list : TAsmList; const s : string);
  533. var
  534. ai : taicpu;
  535. tmpreg: TRegister;
  536. begin
  537. { for now, we use A15 here, however, this is not save as it might contain an argument }
  538. ai:=TAiCpu.op_sym_reg(A_J,current_asmdata.RefAsmSymbol(s,AT_FUNCTION),NR_A15);
  539. ai.oppostfix := PF_L; // if destination is too far for J then assembler can convert to JX
  540. ai.is_jmp:=true;
  541. list.Concat(ai);
  542. end;
  543. procedure tcgcpu.a_jmp_flags(list: TAsmList; const f: TResFlags; l: tasmlabel);
  544. var
  545. instr: taicpu;
  546. begin
  547. if CPUXTENSA_HAS_BOOLEAN_OPTION in cpu_capabilities[current_settings.cputype] then
  548. begin
  549. instr:=taicpu.op_reg_sym(A_B,f.register,l);
  550. instr.condition:=flags_to_cond(f.flag);
  551. instr.is_jmp:=true;
  552. list.concat(instr);
  553. end
  554. else
  555. Internalerror(2020070401);
  556. end;
  557. procedure tcgcpu.g_proc_entry(list : TAsmList; localsize : longint;
  558. nostackframe : boolean);
  559. var
  560. ref : treference;
  561. r : byte;
  562. regs : tcpuregisterset;
  563. stackmisalignment : pint;
  564. regoffset : LongInt;
  565. stack_parameters : Boolean;
  566. registerarea : PtrInt;
  567. l : TAsmLabel;
  568. begin
  569. LocalSize:=align(LocalSize,4);
  570. stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
  571. { call instruction does not put anything on the stack }
  572. registerarea:=0;
  573. if not(nostackframe) then
  574. begin
  575. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  576. a_reg_alloc(list,NR_STACK_POINTER_REG);
  577. case target_info.abi of
  578. abi_xtensa_call0:
  579. begin
  580. list.concat(tai_comment.Create(strpnew(' Start of abi_call0 entry localsize='+tostr(localsize))));
  581. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  582. Include(regs,RS_A15);
  583. if pi_do_call in current_procinfo.flags then
  584. Include(regs,RS_A0);
  585. if regs<>[] then
  586. begin
  587. for r:=RS_A0 to RS_A15 do
  588. if r in regs then
  589. inc(registerarea,4);
  590. end;
  591. if stack_parameters and (pi_estimatestacksize in current_procinfo.flags) then
  592. begin
  593. list.concat(tai_comment.Create(strpnew('Stackframe size was estimated before code generation due to stack parameters')));
  594. list.concat(tai_comment.Create(strpnew(' Calculated stackframe size: '+tostr(txtensaprocinfo(current_procinfo).stackframesize))));
  595. list.concat(tai_comment.Create(strpnew(' Max. outgoing parameter size: '+tostr(txtensaprocinfo(current_procinfo).maxpushedparasize))));
  596. list.concat(tai_comment.Create(strpnew(' End of last temporary location: '+tostr(tg.lasttemp))));
  597. list.concat(tai_comment.Create(strpnew(' Size of register area: '+tostr(registerarea))));
  598. list.concat(tai_comment.Create(strpnew(' Required size after code generation: '+tostr(localsize))));
  599. if localsize>txtensaprocinfo(current_procinfo).stackframesize then
  600. internalerror(2020091001);
  601. localsize:=txtensaprocinfo(current_procinfo).stackframesize;
  602. end
  603. else
  604. begin
  605. inc(localsize,registerarea);
  606. localsize:=align(localsize,current_settings.alignment.localalignmax);
  607. end;
  608. if LocalSize<>0 then
  609. begin
  610. a_reg_alloc(list,NR_STACK_POINTER_REG);
  611. { not sure if 32512 is the correct value or if it can be larger }
  612. if Localsize>32512 then
  613. begin
  614. reference_reset(ref,4,[]);
  615. ref.symbol:=create_data_entry(nil,-localsize);
  616. list.concat(tai_comment.Create(strpnew(' Decreasing stack pointer by localsize='+tostr(localsize)+' using A8 register')));
  617. list.concat(taicpu.op_reg_ref(A_L32R,NR_A8,ref));
  618. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_A8));
  619. end
  620. else
  621. begin
  622. list.concat(tai_comment.Create(strpnew(' Decreasing stack pointer by localsize='+tostr(localsize)+' using A8 register')));
  623. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,-localsize));
  624. end;
  625. end;
  626. reference_reset(ref,4,[]);
  627. ref.base:=NR_STACK_POINTER_REG;
  628. ref.offset:=localsize;
  629. if localsize>1024 then
  630. begin
  631. list.concat(tai_comment.Create(strpnew(' Special entry code of abi_xtensa_call0 entry localsize='+tostr(localsize))));
  632. if localsize<=1024+32512 then
  633. begin
  634. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_A8,NR_STACK_POINTER_REG,localsize-registerarea));
  635. reference_reset(ref,4,[]);
  636. ref.base:=NR_A8;
  637. ref.offset:=registerarea;
  638. end
  639. else
  640. begin
  641. reference_reset(ref,4,[]);
  642. ref.symbol:=create_data_entry(nil,localsize-registerarea);
  643. list.concat(taicpu.op_reg_ref(A_L32R,NR_A8,ref));
  644. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_A8,NR_A8,NR_STACK_POINTER_REG));
  645. reference_reset(ref,4,[]);
  646. ref.base:=NR_A8;
  647. ref.offset:=registerarea;
  648. end;
  649. end;
  650. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  651. begin
  652. dec(ref.offset,4);
  653. list.concat(tai_comment.Create(strpnew(' Storing reg A15 at offset='+tostr(ref.offset))));
  654. list.concat(taicpu.op_reg_ref(A_S32I,NR_A15,ref));
  655. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  656. list.concat(taicpu.op_reg_reg(A_MOV,NR_A15,NR_STACK_POINTER_REG));
  657. end;
  658. if regs<>[] then
  659. begin
  660. for r:=RS_A14 downto RS_A0 do
  661. if r in regs then
  662. begin
  663. dec(ref.offset,4);
  664. list.concat(tai_comment.Create(strpnew(' Storing reg '+std_regname(newreg(R_INTREGISTER,r,R_SUBWHOLE))+' at offset='+tostr(ref.offset))));
  665. list.concat(taicpu.op_reg_ref(A_S32I,newreg(R_INTREGISTER,r,R_SUBWHOLE),ref));
  666. end;
  667. end;
  668. end;
  669. abi_xtensa_windowed:
  670. begin
  671. list.concat(tai_comment.Create(strpnew(' Start of abi_windowed entry localsize='+tostr(localsize))));
  672. if stack_parameters and (pi_estimatestacksize in current_procinfo.flags) then
  673. begin
  674. list.concat(tai_comment.Create(strpnew('Stackframe size was estimated before code generation due to stack parameters')));
  675. list.concat(tai_comment.Create(strpnew(' Calculated stackframe size: '+tostr(txtensaprocinfo(current_procinfo).stackframesize))));
  676. list.concat(tai_comment.Create(strpnew(' Max. outgoing parameter size: '+tostr(txtensaprocinfo(current_procinfo).maxpushedparasize))));
  677. list.concat(tai_comment.Create(strpnew(' End of last temporary location: '+tostr(tg.lasttemp))));
  678. list.concat(tai_comment.Create(strpnew(' Max. window rotation in bytes: '+tostr(txtensaprocinfo(current_procinfo).maxcall*4))));
  679. list.concat(tai_comment.Create(strpnew(' Required size after code generation: '+tostr(localsize))));
  680. { should never happen as localsize is derived from
  681. txtensaprocinfo(current_procinfo).stackframesize }
  682. if localsize>txtensaprocinfo(current_procinfo).stackframesize then
  683. internalerror(2020031402);
  684. localsize:=txtensaprocinfo(current_procinfo).stackframesize;
  685. end
  686. else
  687. begin
  688. localsize:=align(localsize,current_settings.alignment.localalignmax);
  689. inc(localsize,4*4);
  690. if pi_do_call in current_procinfo.flags then
  691. inc(localsize,txtensaprocinfo(current_procinfo).maxcall*4);
  692. end;
  693. if localsize<0 then
  694. Internalerror(2020083001);
  695. if localsize>32760 then
  696. begin
  697. list.concat(taicpu.op_reg_const(A_ENTRY,NR_STACK_POINTER_REG,32));
  698. reference_reset(ref,4,[]);
  699. ref.symbol:=create_data_entry(nil,longint(localsize-32));
  700. list.concat(taicpu.op_reg_ref(A_L32R,NR_A8,ref));
  701. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_A8,NR_STACK_POINTER_REG,NR_A8));
  702. list.concat(taicpu.op_reg_reg(A_MOVSP,NR_STACK_POINTER_REG,NR_A8));
  703. end
  704. else
  705. list.concat(taicpu.op_reg_const(A_ENTRY,NR_STACK_POINTER_REG,localsize));
  706. end;
  707. else
  708. Internalerror(2020031401);
  709. end;
  710. end;
  711. end;
  712. procedure tcgcpu.g_proc_exit(list : TAsmList; parasize : longint;
  713. nostackframe : boolean);
  714. var
  715. ref : treference;
  716. r : byte;
  717. regs : tcpuregisterset;
  718. stackmisalignment : pint;
  719. regoffset : LongInt;
  720. stack_parameters : Boolean;
  721. registerarea : PtrInt;
  722. l : TAsmLabel;
  723. LocalSize: longint;
  724. begin
  725. case target_info.abi of
  726. abi_xtensa_windowed:
  727. list.Concat(taicpu.op_none(A_RETW));
  728. abi_xtensa_call0:
  729. begin
  730. if not(nostackframe) then
  731. begin
  732. LocalSize:=current_procinfo.calc_stackframe_size;
  733. LocalSize:=align(LocalSize,4);
  734. stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
  735. registerarea:=0;
  736. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  737. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  738. Include(regs,RS_A15);
  739. if pi_do_call in current_procinfo.flags then
  740. Include(regs,RS_A0);
  741. if regs<>[] then
  742. begin
  743. for r:=RS_A0 to RS_A15 do
  744. if r in regs then
  745. inc(registerarea,4);
  746. end;
  747. { do we use then estimated stack size? }
  748. if not(stack_parameters and (pi_estimatestacksize in current_procinfo.flags)) then
  749. begin
  750. inc(localsize,registerarea);
  751. localsize:=align(localsize,current_settings.alignment.localalignmax);
  752. end;
  753. if LocalSize<>0 then
  754. begin
  755. // Determine reference mode required to access stack
  756. reference_reset(ref,4,[]);
  757. ref.base:=NR_STACK_POINTER_REG;
  758. ref.offset:=localsize;
  759. if localsize>1024 then
  760. begin
  761. if localsize<=1024+32512 then
  762. begin
  763. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_A8,NR_STACK_POINTER_REG,ref.offset-registerarea));
  764. ref.offset:=registerarea;
  765. ref.base:=NR_A8;
  766. end
  767. else
  768. begin
  769. reference_reset(ref,4,[]);
  770. ref.symbol:=create_data_entry(nil,ref.offset-registerarea);
  771. list.concat(taicpu.op_reg_ref(A_L32R,NR_A8,ref));
  772. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_A8,NR_A8,NR_STACK_POINTER_REG));
  773. reference_reset(ref,4,[]);
  774. ref.base:=NR_A8;
  775. ref.offset:=registerarea;
  776. end;
  777. end;
  778. // restore a15 if used
  779. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  780. begin
  781. dec(ref.offset,4);
  782. list.concat(tai_comment.Create(strpnew(' Restoring reg A15 from offset='+tostr(ref.offset))));
  783. list.concat(taicpu.op_reg_ref(A_L32I,NR_A15,ref));
  784. a_reg_dealloc(list,NR_FRAME_POINTER_REG);
  785. end;
  786. // restore rest of registers
  787. if regs<>[] then
  788. begin
  789. for r:=RS_A14 downto RS_A0 do
  790. if r in regs then
  791. begin
  792. dec(ref.offset,4);
  793. list.concat(tai_comment.Create(strpnew(' Restoring reg '+std_regname(newreg(R_INTREGISTER,r,R_SUBWHOLE))+' from offset='+tostr(ref.offset))));
  794. list.concat(taicpu.op_reg_ref(A_L32I,newreg(R_INTREGISTER,r,R_SUBWHOLE),ref));
  795. end;
  796. end;
  797. // restore stack pointer
  798. { not sure if 32512 is the correct value or if it can be larger }
  799. list.concat(tai_comment.Create(strpnew(' Restoring stack pointer')));
  800. if Localsize>32512 then
  801. begin
  802. reference_reset(ref,4,[]);
  803. ref.symbol:=create_data_entry(nil,localsize);
  804. list.concat(taicpu.op_reg_ref(A_L32R,NR_A8,ref));
  805. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_A8));
  806. end
  807. else
  808. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,localsize));
  809. a_reg_dealloc(list,NR_STACK_POINTER_REG);
  810. end;
  811. end;
  812. list.Concat(taicpu.op_none(A_RET));
  813. end
  814. else
  815. Internalerror(2020031403);
  816. end;
  817. end;
  818. procedure tcgcpu.a_cmp_const_reg_label(list: TAsmList; size: tcgsize; cmp_op: topcmp; a: tcgint; reg: tregister; l: tasmlabel);
  819. function is_b4const(v: tcgint): boolean;
  820. begin
  821. case v of
  822. -1,1,2,3,4,5,6,7,8,
  823. 10,12,16,32,64,128,256:
  824. result:=true;
  825. else
  826. result:=false;
  827. end;
  828. end;
  829. function is_b4constu(v: tcgint): boolean;
  830. begin
  831. case v of
  832. 32768,65536,
  833. 2,3,4,5,6,7,8,
  834. 10,12,16,32,64,128,256:
  835. result:=true;
  836. else
  837. result:=false;
  838. end;
  839. end;
  840. var
  841. op: TAsmCond;
  842. instr: taicpu;
  843. begin
  844. if (a=0) and (cmp_op in [OC_EQ,OC_NE,OC_LT,OC_GTE]) then
  845. begin
  846. case cmp_op of
  847. OC_EQ: op:=C_EQZ;
  848. OC_NE: op:=C_NEZ;
  849. OC_LT: op:=C_LTZ;
  850. OC_GTE: op:=C_GEZ;
  851. else
  852. Internalerror(2020030806);
  853. end;
  854. instr:=taicpu.op_reg_sym(A_B,reg,l);
  855. instr.condition:=op;
  856. instr.is_jmp:=true;
  857. list.concat(instr);
  858. end
  859. else if is_b4const(a) and
  860. (cmp_op in [OC_EQ,OC_NE,OC_LT,OC_GTE]) then
  861. begin
  862. case cmp_op of
  863. OC_EQ: op:=C_EQI;
  864. OC_NE: op:=C_NEI;
  865. OC_LT: op:=C_LTI;
  866. OC_GTE: op:=C_GEI;
  867. else
  868. Internalerror(2020030807);
  869. end;
  870. instr:=taicpu.op_reg_const_sym(A_B,reg,a,l);
  871. instr.condition:=op;
  872. instr.is_jmp:=true;
  873. list.concat(instr);
  874. end
  875. else if is_b4constu(a) and
  876. (cmp_op in [OC_B,OC_AE]) then
  877. begin
  878. case cmp_op of
  879. OC_B: op:=C_LTUI;
  880. OC_AE: op:=C_GEUI;
  881. else
  882. Internalerror(2020030808);
  883. end;
  884. instr:=taicpu.op_reg_const_sym(A_B,reg,a,l);
  885. instr.condition:=op;
  886. instr.is_jmp:=true;
  887. list.concat(instr);
  888. end
  889. else
  890. inherited a_cmp_const_reg_label(list, size, cmp_op, a, reg, l);
  891. end;
  892. procedure tcgcpu.a_cmp_reg_reg_label(list : TAsmList; size : tcgsize;
  893. cmp_op : topcmp; reg1,reg2 : tregister; l : tasmlabel);
  894. var
  895. tmpreg: TRegister;
  896. instr: taicpu;
  897. begin
  898. if TOpCmp2AsmCond[cmp_op]=C_None then
  899. begin
  900. cmp_op:=swap_opcmp(cmp_op);
  901. tmpreg:=reg1;
  902. reg1:=reg2;
  903. reg2:=tmpreg;
  904. end;
  905. instr:=taicpu.op_reg_reg_sym(A_B,reg2,reg1,l);
  906. instr.condition:=TOpCmp2AsmCond[cmp_op];
  907. instr.is_jmp:=true;
  908. list.concat(instr);
  909. end;
  910. procedure tcgcpu.a_jmp_always(list : TAsmList; l : TAsmLabel);
  911. var
  912. ai : taicpu;
  913. begin
  914. if l.bind in [AB_GLOBAL] then
  915. begin
  916. { for now, we use A15 here, however, this is not save as it might contain an argument, I have not figured out a
  917. solution yet }
  918. ai:=taicpu.op_sym_reg(A_J,l,NR_A15);
  919. ai.oppostfix := PF_L;
  920. end
  921. else
  922. ai:=taicpu.op_sym(A_J,l);
  923. ai.is_jmp:=true;
  924. list.concat(ai);
  925. end;
  926. procedure tcgcpu.g_flags2reg(list: TAsmList; size: TCgSize; const f: tresflags; reg: TRegister);
  927. var
  928. hregister: TRegister;
  929. instr: taicpu;
  930. begin
  931. a_load_const_reg(list,size,0,reg);
  932. hregister:=getintregister(list,size);
  933. a_load_const_reg(list,size,1,hregister);
  934. instr:=taicpu.op_reg_reg_reg(A_MOV,reg,hregister,f.register);
  935. instr.condition:=flags_to_cond(f.flag);
  936. list.concat(instr);
  937. end;
  938. procedure tcgcpu.g_concatcopy_move(list: tasmlist; const Source, dest: treference; len: tcgint);
  939. var
  940. paraloc1, paraloc2, paraloc3: TCGPara;
  941. pd: tprocdef;
  942. begin
  943. pd:=search_system_proc('MOVE');
  944. paraloc1.init;
  945. paraloc2.init;
  946. paraloc3.init;
  947. paramanager.getcgtempparaloc(list, pd, 1, paraloc1);
  948. paramanager.getcgtempparaloc(list, pd, 2, paraloc2);
  949. paramanager.getcgtempparaloc(list, pd, 3, paraloc3);
  950. a_load_const_cgpara(list, OS_SINT, len, paraloc3);
  951. a_loadaddr_ref_cgpara(list, dest, paraloc2);
  952. a_loadaddr_ref_cgpara(list, Source, paraloc1);
  953. paramanager.freecgpara(list, paraloc3);
  954. paramanager.freecgpara(list, paraloc2);
  955. paramanager.freecgpara(list, paraloc1);
  956. alloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  957. alloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  958. a_call_name(list, 'FPC_MOVE', false);
  959. dealloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  960. dealloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  961. paraloc3.done;
  962. paraloc2.done;
  963. paraloc1.done;
  964. end;
  965. procedure tcgcpu.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  966. var
  967. tmpreg1, hreg, countreg: TRegister;
  968. src, dst, src2, dst2: TReference;
  969. lab: tasmlabel;
  970. Count, count2: aint;
  971. function reference_is_reusable(const ref: treference): boolean;
  972. begin
  973. result:=(ref.base<>NR_NO) and (ref.index=NR_NO) and
  974. (ref.symbol=nil);
  975. end;
  976. begin
  977. src2:=source;
  978. fixref(list,src2);
  979. dst2:=dest;
  980. fixref(list,dst2);
  981. if len > high(longint) then
  982. internalerror(2002072704);
  983. { A call (to FPC_MOVE) requires the outgoing parameter area to be properly
  984. allocated on stack. This can only be done before tmipsprocinfo.set_first_temp_offset,
  985. i.e. before secondpass. Other internal procedures request correct stack frame
  986. by setting pi_do_call during firstpass, but for this particular one it is impossible.
  987. Therefore, if the current procedure is a leaf one, we have to leave it that way. }
  988. { anybody wants to determine a good value here :)? }
  989. if (len > 100) and
  990. assigned(current_procinfo) and
  991. (pi_do_call in current_procinfo.flags) then
  992. g_concatcopy_move(list, src2, dst2, len)
  993. else
  994. begin
  995. Count := len div 4;
  996. if (count<=4) and reference_is_reusable(src2) then
  997. src:=src2
  998. else
  999. begin
  1000. reference_reset(src,sizeof(aint),[]);
  1001. { load the address of src2 into src.base }
  1002. src.base := GetAddressRegister(list);
  1003. a_loadaddr_ref_reg(list, src2, src.base);
  1004. end;
  1005. if (count<=4) and reference_is_reusable(dst2) then
  1006. dst:=dst2
  1007. else
  1008. begin
  1009. reference_reset(dst,sizeof(aint),[]);
  1010. { load the address of dst2 into dst.base }
  1011. dst.base := GetAddressRegister(list);
  1012. a_loadaddr_ref_reg(list, dst2, dst.base);
  1013. end;
  1014. { generate a loop }
  1015. if Count > 4 then
  1016. begin
  1017. countreg := GetIntRegister(list, OS_INT);
  1018. tmpreg1 := GetIntRegister(list, OS_INT);
  1019. a_load_const_reg(list, OS_INT, Count, countreg);
  1020. current_asmdata.getjumplabel(lab);
  1021. if CPUXTENSA_HAS_LOOPS in cpu_capabilities[current_settings.cputype] then
  1022. begin
  1023. list.concat(taicpu.op_reg_sym(A_LOOP, countreg, lab));
  1024. list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src));
  1025. list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst));
  1026. list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 4));
  1027. list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 4));
  1028. a_label(list, lab);
  1029. end
  1030. else
  1031. begin
  1032. a_label(list, lab);
  1033. list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src));
  1034. list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst));
  1035. list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 4));
  1036. list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 4));
  1037. list.concat(taicpu.op_reg_reg_const(A_ADDI, countreg, countreg, -1));
  1038. a_cmp_const_reg_label(list,OS_INT,OC_NE,0,countreg,lab);
  1039. { keep the registers alive }
  1040. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1041. end;
  1042. { keep the registers alive }
  1043. list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base));
  1044. list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base));
  1045. len := len mod 4;
  1046. end;
  1047. { unrolled loop }
  1048. Count := len div 4;
  1049. if Count > 0 then
  1050. begin
  1051. tmpreg1 := GetIntRegister(list, OS_INT);
  1052. for count2 := 1 to Count do
  1053. begin
  1054. list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src));
  1055. list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst));
  1056. Inc(src.offset, 4);
  1057. Inc(dst.offset, 4);
  1058. end;
  1059. len := len mod 4;
  1060. end;
  1061. if (len and 4) <> 0 then
  1062. begin
  1063. hreg := GetIntRegister(list, OS_INT);
  1064. a_load_ref_reg(list, OS_32, OS_32, src, hreg);
  1065. a_load_reg_ref(list, OS_32, OS_32, hreg, dst);
  1066. Inc(src.offset, 4);
  1067. Inc(dst.offset, 4);
  1068. end;
  1069. { copy the leftovers }
  1070. if (len and 2) <> 0 then
  1071. begin
  1072. hreg := GetIntRegister(list, OS_INT);
  1073. a_load_ref_reg(list, OS_16, OS_16, src, hreg);
  1074. a_load_reg_ref(list, OS_16, OS_16, hreg, dst);
  1075. Inc(src.offset, 2);
  1076. Inc(dst.offset, 2);
  1077. end;
  1078. if (len and 1) <> 0 then
  1079. begin
  1080. hreg := GetIntRegister(list, OS_INT);
  1081. a_load_ref_reg(list, OS_8, OS_8, src, hreg);
  1082. a_load_reg_ref(list, OS_8, OS_8, hreg, dst);
  1083. end;
  1084. end;
  1085. end;
  1086. procedure tcgcpu.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1087. var
  1088. ai: taicpu;
  1089. begin
  1090. if not(fromsize in [OS_32,OS_F32]) then
  1091. InternalError(2020032603);
  1092. ai := taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1093. ai.oppostfix := PF_S;
  1094. list.concat(ai);
  1095. end;
  1096. procedure tcgcpu.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1097. var
  1098. href: treference;
  1099. begin
  1100. if not(fromsize in [OS_32,OS_F32]) then
  1101. InternalError(2020032602);
  1102. href:=ref;
  1103. if assigned(href.symbol) or
  1104. ((href.index<>NR_NO) and (href.offset<>0)) or
  1105. (((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) then
  1106. fixref(list,href);
  1107. if (href.base<>NR_NO) and (href.index<>NR_NO) then
  1108. list.concat(taicpu.op_reg_ref(A_LSX,reg,href))
  1109. else
  1110. list.concat(taicpu.op_reg_ref(A_LSI,reg,href));
  1111. if fromsize<>tosize then
  1112. a_loadfpu_reg_reg(list,fromsize,tosize,reg,reg);
  1113. end;
  1114. procedure tcgcpu.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1115. var
  1116. href: treference;
  1117. begin
  1118. if not(fromsize in [OS_32,OS_F32]) then
  1119. InternalError(2020032604);
  1120. href:=ref;
  1121. if assigned(href.symbol) or
  1122. ((href.index<>NR_NO) and (href.offset<>0)) or
  1123. (((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) then
  1124. fixref(list,href);
  1125. if (href.base<>NR_NO) and (href.index<>NR_NO) then
  1126. list.concat(taicpu.op_reg_ref(A_SSX,reg,href))
  1127. else
  1128. list.concat(taicpu.op_reg_ref(A_SSI,reg,href));
  1129. end;
  1130. procedure tcgcpu.a_loadfpu_intreg_reg(list : TAsmList; fromsize,tosize : tcgsize; intreg,fpureg : tregister);
  1131. begin
  1132. if not(tcgsize2size[fromsize]=4) or
  1133. not(tcgsize2size[tosize]=4) then
  1134. internalerror(2020091102);
  1135. list.concat(taicpu.op_reg_reg(A_WFR,fpureg,intreg));
  1136. end;
  1137. procedure tcgcpu.a_loadfpu_reg_intreg(list : TAsmList; fromsize,tosize : tcgsize; fpureg,intreg : tregister);
  1138. begin
  1139. if not(tcgsize2size[fromsize]=4) or
  1140. not(tcgsize2size[tosize]=4) then
  1141. internalerror(2020091202);
  1142. list.concat(taicpu.op_reg_reg(A_RFR,intreg,fpureg));
  1143. end;
  1144. procedure tcgcpu.maybeadjustresult(list : TAsmList; op : TOpCg; size : tcgsize; dst : tregister);
  1145. const
  1146. overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NEG];
  1147. begin
  1148. if (op in overflowops) and
  1149. (size in [OS_8,OS_S8,OS_16,OS_S16]) then
  1150. a_load_reg_reg(list,OS_32,size,dst,dst);
  1151. end;
  1152. procedure tcgcpu.g_overflowcheck(list: TAsmList; const Loc: tlocation; def: tdef);
  1153. begin
  1154. { no overflow checking yet }
  1155. end;
  1156. function tcgcpu.create_data_entry(symbol: TAsmSymbol;offset: asizeint): TAsmLabel;
  1157. var
  1158. hp: tai;
  1159. begin
  1160. hp:=tai(current_procinfo.aktlocaldata.first);
  1161. while assigned(hp) do
  1162. begin
  1163. if (hp.typ=ait_label) and assigned(hp.Next) and
  1164. (tai(hp.Next).typ=ait_const) and
  1165. (tai_const(hp.Next).consttype=aitconst_ptr) and
  1166. (tai_const(hp.Next).sym=symbol) and
  1167. (tai_const(hp.Next).endsym=nil) and
  1168. ((assigned(symbol) and (tai_const(hp.Next).symofs=offset)) or
  1169. (not(assigned(symbol)) and (tai_const(hp.Next).value=offset))
  1170. ) then
  1171. begin
  1172. Result:=tai_label(hp).labsym;
  1173. exit;
  1174. end;
  1175. hp:=tai(hp.Next);
  1176. end;
  1177. current_asmdata.getjumplabel(Result);
  1178. cg.a_label(current_procinfo.aktlocaldata,Result);
  1179. if assigned(symbol) then
  1180. current_procinfo.aktlocaldata.concat(tai_const.create_sym_offset(symbol,offset))
  1181. else
  1182. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(offset));
  1183. end;
  1184. procedure tcgcpu.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; srcsize, dstsize: TCGSize; src, dst: TRegister);
  1185. var
  1186. ai: taicpu;
  1187. tmpreg: TRegister;
  1188. begin
  1189. if reverse then
  1190. begin
  1191. list.Concat(taicpu.op_reg_reg(A_NSAU,dst,src));
  1192. tmpreg:=getintregister(list,OS_INT);
  1193. a_load_const_reg(list,OS_INT,31,tmpreg);
  1194. a_op_reg_reg_reg(list,OP_SUB,OS_INT,dst,tmpreg,dst);
  1195. tmpreg:=getintregister(list,OS_INT);
  1196. a_load_const_reg(list,OS_INT,255,tmpreg);
  1197. ai:=taicpu.op_reg_reg_reg(A_MOV,dst,tmpreg,src);
  1198. ai.condition:=C_EQZ;
  1199. list.Concat(ai);
  1200. end
  1201. else
  1202. Internalerror(2020092604);
  1203. end;
  1204. procedure tcg64fxtensa.a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
  1205. var
  1206. instr: taicpu;
  1207. no_carry: TAsmLabel;
  1208. tmpreg: TRegister;
  1209. begin
  1210. case op of
  1211. OP_NEG,
  1212. OP_NOT :
  1213. internalerror(2020030810);
  1214. else
  1215. ;
  1216. end;
  1217. case op of
  1218. OP_AND,OP_OR,OP_XOR:
  1219. begin
  1220. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
  1221. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
  1222. end;
  1223. OP_ADD:
  1224. begin
  1225. if (regsrc1.reglo=regdst.reglo) or (regsrc1.reghi=regdst.reghi) then
  1226. Internalerror(2020082205);
  1227. list.concat(taicpu.op_reg_reg_reg(A_ADD, regdst.reglo, regsrc2.reglo, regsrc1.reglo));
  1228. list.concat(taicpu.op_reg_reg_reg(A_ADD, regdst.reghi, regsrc2.reghi, regsrc1.reghi));
  1229. current_asmdata.getjumplabel(no_carry);
  1230. cg.a_cmp_reg_reg_label(list,OS_INT,OC_AE, regsrc1.reglo, regdst.reglo, no_carry);
  1231. list.concat(taicpu.op_reg_reg_const(A_ADDI, regdst.reghi, regdst.reghi, 1));
  1232. cg.a_label(list,no_carry);
  1233. end;
  1234. OP_SUB:
  1235. begin
  1236. if (regsrc1.reglo=regdst.reglo) or (regsrc1.reghi=regdst.reghi) then
  1237. Internalerror(2020082206);
  1238. { we need the original src2 value for the comparison, do not overwrite it }
  1239. if regsrc2.reglo=regdst.reglo then
  1240. begin
  1241. tmpreg:=cg.GetIntRegister(list,OS_S32);
  1242. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc2.reglo,tmpreg);
  1243. regsrc2.reglo:=tmpreg;
  1244. end;
  1245. list.concat(taicpu.op_reg_reg_reg(A_SUB, regdst.reglo, regsrc2.reglo, regsrc1.reglo));
  1246. list.concat(taicpu.op_reg_reg_reg(A_SUB, regdst.reghi, regsrc2.reghi, regsrc1.reghi));
  1247. current_asmdata.getjumplabel(no_carry);
  1248. cg.a_cmp_reg_reg_label(list,OS_INT,OC_AE, regsrc1.reglo, regsrc2.reglo, no_carry);
  1249. list.concat(taicpu.op_reg_reg_const(A_ADDI, regdst.reghi, regdst.reghi, -1));
  1250. cg.a_label(list,no_carry);
  1251. end;
  1252. else
  1253. internalerror(2020030813);
  1254. end;
  1255. end;
  1256. procedure tcg64fxtensa.a_op64_reg_reg(list : TAsmList; op : TOpCG; size : tcgsize; regsrc,regdst : tregister64);
  1257. var
  1258. tmpreg : TRegister;
  1259. instr : taicpu;
  1260. begin
  1261. case op of
  1262. OP_NEG:
  1263. begin
  1264. tmpreg:=cg.GetIntRegister(list, OS_INT);
  1265. list.concat(taicpu.op_reg_reg(A_NEG,regdst.reglo,regsrc.reglo));
  1266. list.concat(taicpu.op_reg_reg(A_NEG,regdst.reghi,regsrc.reghi));
  1267. list.concat(taicpu.op_reg_reg_const(A_ADDI,tmpreg,regdst.reghi,-1));
  1268. instr:=taicpu.op_reg_reg_reg(A_MOV,regdst.reghi,tmpreg,regdst.reglo);
  1269. instr.condition:=C_NEZ;
  1270. list.concat(instr);
  1271. end;
  1272. OP_NOT:
  1273. begin
  1274. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reglo,regdst.reglo);
  1275. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reghi,regdst.reghi);
  1276. end;
  1277. else
  1278. a_op64_reg_reg_reg(list,op,size,regsrc,regdst,regdst);
  1279. end;
  1280. end;
  1281. procedure tcg64fxtensa.a_op64_const_reg_reg(list : TAsmList; op : TOpCG; size : tcgsize; value : int64; regsrc,regdst : tregister64);
  1282. var
  1283. tmpreg64 : tregister64;
  1284. no_carry : TAsmLabel;
  1285. tmpreg: tregister;
  1286. begin
  1287. case op of
  1288. OP_NEG,
  1289. OP_NOT :
  1290. internalerror(2020030904);
  1291. else
  1292. ;
  1293. end;
  1294. case op of
  1295. OP_AND,OP_OR,OP_XOR:
  1296. begin
  1297. cg.a_op_const_reg_reg(list,op,OS_32,aint(lo(value)),regsrc.reglo,regdst.reglo);
  1298. cg.a_op_const_reg_reg(list,op,OS_32,aint(hi(value)),regsrc.reghi,regdst.reghi);
  1299. end;
  1300. OP_ADD:
  1301. begin
  1302. { could do better here (hi(value) in 248..2047), for now we support only the simple cases }
  1303. if (value>=-2048) and (value<=2047) then
  1304. begin
  1305. { we need the original src value for the comparison, do not overwrite it }
  1306. if regsrc.reglo=regdst.reglo then
  1307. begin
  1308. tmpreg:=cg.GetIntRegister(list,OS_S32);
  1309. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reglo,tmpreg);
  1310. regsrc.reglo:=tmpreg;
  1311. end;
  1312. list.concat(taicpu.op_reg_reg_const(A_ADDI, regdst.reglo, regsrc.reglo, value));
  1313. list.concat(taicpu.op_reg_reg(A_MOV, regdst.reghi, regsrc.reghi));
  1314. current_asmdata.getjumplabel(no_carry);
  1315. cg.a_cmp_reg_reg_label(list,OS_INT,OC_AE, regsrc.reglo, regdst.reglo, no_carry);
  1316. list.concat(taicpu.op_reg_reg_const(A_ADDI, regdst.reghi, regdst.reghi, 1));
  1317. cg.a_label(list,no_carry);
  1318. end
  1319. else
  1320. begin
  1321. tmpreg64.reglo := cg.GetIntRegister(list,OS_S32);
  1322. tmpreg64.reghi := cg.GetIntRegister(list,OS_S32);
  1323. a_load64_const_reg(list,value,tmpreg64);
  1324. a_op64_reg_reg_reg(list,op,size,tmpreg64,regsrc,regdst);
  1325. end;
  1326. end;
  1327. OP_SHL:
  1328. begin
  1329. if (value>0) and (value<=16) then
  1330. begin
  1331. tmpreg:=cg.GetIntRegister(list,OS_32);
  1332. list.concat(taicpu.op_reg_reg_const_const(A_EXTUI, tmpreg, regsrc.reglo, 32-value, value));
  1333. list.concat(taicpu.op_reg_reg_const(A_SLLI, regdst.reglo, regsrc.reglo, value));
  1334. list.concat(taicpu.op_reg_reg_const(A_SLLI, regdst.reghi, regsrc.reghi, value));
  1335. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reghi, tmpreg, regdst.reghi));
  1336. end
  1337. else if value=32 then
  1338. begin
  1339. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reglo,regdst.reghi);
  1340. cg.a_load_const_reg(list,OS_INT,0,regdst.reglo);
  1341. end
  1342. else
  1343. Internalerror(2020082209);
  1344. end;
  1345. OP_SHR:
  1346. begin
  1347. if (value>0) and (value<=15) then
  1348. begin
  1349. tmpreg:=cg.GetIntRegister(list,OS_32);
  1350. list.concat(taicpu.op_reg_reg_const(A_SLLI, tmpreg, regsrc.reghi, 32-value));
  1351. list.concat(taicpu.op_reg_reg_const(A_SRLI, regdst.reglo, regsrc.reglo, value));
  1352. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reglo, tmpreg, regdst.reglo));
  1353. list.concat(taicpu.op_reg_reg_const(A_SRLI, regdst.reghi, regsrc.reghi, value));
  1354. end
  1355. else if value=32 then
  1356. begin
  1357. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reghi,regdst.reglo);
  1358. cg.a_load_const_reg(list,OS_INT,0,regdst.reghi);
  1359. end
  1360. else
  1361. Internalerror(2020082210);
  1362. end;
  1363. OP_SUB:
  1364. begin
  1365. { for now, we take the simple approach }
  1366. tmpreg64.reglo := cg.GetIntRegister(list,OS_S32);
  1367. tmpreg64.reghi := cg.GetIntRegister(list,OS_S32);
  1368. a_load64_const_reg(list,value,tmpreg64);
  1369. a_op64_reg_reg_reg(list,op,size,tmpreg64,regsrc,regdst);
  1370. end;
  1371. else
  1372. internalerror(2020030901);
  1373. end;
  1374. end;
  1375. procedure tcg64fxtensa.a_op64_const_reg(list : TAsmList; op : TOpCG; size : tcgsize; value : int64; reg : tregister64);
  1376. begin
  1377. a_op64_const_reg_reg(list,op,size,value,reg,reg);
  1378. end;
  1379. {$warnings off}
  1380. procedure create_codegen;
  1381. begin
  1382. cg:=tcgcpu.Create;
  1383. cg64:=tcg64fxtensa.Create;
  1384. end;
  1385. end.