popt386.pas 90 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  40. RegUsedAfterInstruction := Reg in UsedRegs
  41. End;
  42. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  43. {First pass of peepholeoptimizations}
  44. Var
  45. l : longint;
  46. p ,hp1, hp2 : pai;
  47. {$ifdef foropt}
  48. hp3, hp4: pai;
  49. {$endif foropt}
  50. TmpBool1, TmpBool2: Boolean;
  51. TmpRef: TReference;
  52. UsedRegs, TmpUsedRegs: TRegSet;
  53. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  54. {skips all labels and returns the next "real" instruction}
  55. Begin
  56. While assigned(hp^.next) and
  57. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  58. hp := pai(hp^.next);
  59. If assigned(hp^.next) Then
  60. Begin
  61. SkipLabels := True;
  62. hp2 := pai(hp^.next)
  63. End
  64. Else
  65. Begin
  66. hp2 := hp;
  67. SkipLabels := False
  68. End;
  69. End;
  70. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  71. {traces sucessive jumps to their final destination and sets it, e.g.
  72. je l1 je l3
  73. <code> <code>
  74. l1: becomes l1:
  75. je l2 je l3
  76. <code> <code>
  77. l2: l2:
  78. jmp l3 jmp l3}
  79. Var p1, p2: pai;
  80. l: pasmlabel;
  81. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  82. Begin
  83. FindAnyLabel := false;
  84. While assigned(hp^.next) and
  85. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  86. hp := pai(hp^.next);
  87. If assigned(hp^.next) and
  88. (pai(hp^.next)^.typ = ait_label) Then
  89. Begin
  90. FindAnyLabel := true;
  91. l := pai_label(hp^.next)^.l;
  92. End
  93. End;
  94. Begin
  95. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  96. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  97. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  98. Begin
  99. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  100. SkipLabels(p1,p1);
  101. If (pai(p1)^.typ = ait_instruction) and
  102. (paicpu(p1)^.is_jmp) Then
  103. If { the next instruction after the label where the jump hp arrives}
  104. { is unconditional or of the same type as hp, so continue }
  105. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  106. { the next instruction after the label where the jump hp arrives}
  107. { is the opposite of hp (so this one is never taken), but after }
  108. { that one there is a branch that will be taken, so perform a }
  109. { little hack: set p1 equal to this instruction (that's what the}
  110. { last SkipLabels is for, only works with short bool evaluation)}
  111. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  112. SkipLabels(p1,p2) and
  113. (p2^.typ = ait_instruction) and
  114. (paicpu(p2)^.is_jmp) and
  115. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  116. SkipLabels(p1,p1)) Then
  117. Begin
  118. GetFinalDestination(asml, paicpu(p1));
  119. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  120. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  121. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  122. End
  123. Else
  124. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  125. if not FindAnyLabel(p1,l) then
  126. begin
  127. {$ifdef finaldestdebug}
  128. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  129. strpnew('previous label inserted'))));
  130. {$endif finaldestdebug}
  131. getlabel(l);
  132. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  133. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  134. hp^.oper[0].sym := l;
  135. inc(l^.refs);
  136. { this won't work, since the new label isn't in the labeltable }
  137. { so it will fail the rangecheck. Labeltable should become a }
  138. { hashtable to support this: }
  139. { GetFinalDestination(asml, hp); }
  140. end
  141. else
  142. begin
  143. {$ifdef finaldestdebug}
  144. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  145. strpnew('next label reused'))));
  146. {$endif finaldestdebug}
  147. inc(l^.refs);
  148. hp^.oper[0].sym := l;
  149. GetFinalDestination(asml, hp);
  150. end;
  151. End;
  152. End;
  153. Function DoSubAddOpt(var p: Pai): Boolean;
  154. Begin
  155. DoSubAddOpt := False;
  156. If GetLastInstruction(p, hp1) And
  157. (hp1^.typ = ait_instruction) And
  158. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  159. Case Paicpu(hp1)^.opcode Of
  160. A_DEC:
  161. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  162. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  163. Begin
  164. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  165. AsmL^.Remove(hp1);
  166. Dispose(hp1, Done)
  167. End;
  168. A_SUB:
  169. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  170. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  171. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  172. Begin
  173. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  174. AsmL^.Remove(hp1);
  175. Dispose(hp1, Done)
  176. End;
  177. A_ADD:
  178. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  179. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  180. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  181. Begin
  182. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  183. AsmL^.Remove(hp1);
  184. Dispose(hp1, Done);
  185. If (Paicpu(p)^.oper[0].val = 0) Then
  186. Begin
  187. hp1 := Pai(p^.next);
  188. AsmL^.Remove(p);
  189. Dispose(p, Done);
  190. If Not GetLastInstruction(hp1, p) Then
  191. p := hp1;
  192. DoSubAddOpt := True;
  193. End
  194. End;
  195. End;
  196. End;
  197. Begin
  198. P := BlockStart;
  199. UsedRegs := [];
  200. While (P <> BlockEnd) Do
  201. Begin
  202. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  203. Case P^.Typ Of
  204. ait_instruction:
  205. Begin
  206. { Handle Jmp Optimizations }
  207. if Paicpu(p)^.is_jmp then
  208. begin
  209. {the following if-block removes all code between a jmp and the next label,
  210. because it can never be executed}
  211. If (paicpu(p)^.opcode = A_JMP) Then
  212. Begin
  213. While GetNextInstruction(p, hp1) and
  214. ((hp1^.typ <> ait_label) or
  215. { skip unused labels, they're not referenced anywhere }
  216. Not(Pai_Label(hp1)^.l^.is_used)) Do
  217. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  218. Begin
  219. AsmL^.Remove(hp1);
  220. Dispose(hp1, done);
  221. End;
  222. End;
  223. If GetNextInstruction(p, hp1) then
  224. Begin
  225. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  226. Begin
  227. hp2:=pai(hp1^.next);
  228. asml^.remove(p);
  229. dispose(p,done);
  230. p:=hp2;
  231. continue;
  232. end
  233. Else
  234. Begin
  235. if hp1^.typ = ait_label then
  236. SkipLabels(hp1,hp1);
  237. If (pai(hp1)^.typ=ait_instruction) and
  238. (paicpu(hp1)^.opcode=A_JMP) and
  239. GetNextInstruction(hp1, hp2) And
  240. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  241. Then
  242. Begin
  243. if paicpu(p)^.opcode=A_Jcc then
  244. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  245. else
  246. begin
  247. If (LabDif <> 0) Then
  248. GetFinalDestination(asml, paicpu(p));
  249. p:=pai(p^.next);
  250. continue;
  251. end;
  252. Dec(pai_label(hp2)^.l^.refs);
  253. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  254. Inc(paicpu(p)^.oper[0].sym^.refs);
  255. asml^.remove(hp1);
  256. dispose(hp1,done);
  257. If (LabDif <> 0) Then
  258. GetFinalDestination(asml, paicpu(p));
  259. end
  260. else
  261. If (LabDif <> 0) Then
  262. GetFinalDestination(asml, paicpu(p));
  263. end;
  264. end
  265. end
  266. else
  267. { All other optimizes }
  268. begin
  269. For l := 0 to 2 Do
  270. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  271. With Paicpu(p)^.oper[l].ref^ Do
  272. Begin
  273. If (base = R_NO) And
  274. (index <> R_NO) And
  275. (scalefactor in [0,1])
  276. Then
  277. Begin
  278. base := index;
  279. index := R_NO
  280. End
  281. End;
  282. Case Paicpu(p)^.opcode Of
  283. A_AND:
  284. Begin
  285. If (Paicpu(p)^.oper[0].typ = top_const) And
  286. (Paicpu(p)^.oper[1].typ = top_reg) And
  287. GetNextInstruction(p, hp1) And
  288. (Pai(hp1)^.typ = ait_instruction) And
  289. (Paicpu(hp1)^.opcode = A_AND) And
  290. (Paicpu(hp1)^.oper[0].typ = top_const) And
  291. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  292. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  293. Then
  294. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  295. Begin
  296. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  297. AsmL^.Remove(hp1);
  298. Dispose(hp1, Done)
  299. End
  300. Else
  301. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  302. jump, but only if it's a conditional jump (PFV) }
  303. If (Paicpu(p)^.oper[1].typ = top_reg) And
  304. GetNextInstruction(p, hp1) And
  305. (hp1^.typ = ait_instruction) And
  306. (Paicpu(hp1)^.is_jmp) and
  307. (Paicpu(hp1)^.opcode<>A_JMP) and
  308. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  309. Paicpu(p)^.opcode := A_TEST;
  310. End;
  311. A_CMP:
  312. Begin
  313. If (Paicpu(p)^.oper[0].typ = top_const) And
  314. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  315. (Paicpu(p)^.oper[0].val = 0) Then
  316. {$ifdef foropt}
  317. If GetNextInstruction(p, hp1) And
  318. (hp1^.typ = ait_instruction) And
  319. (Paicpu(hp1)^.is_jmp) and
  320. (paicpu(hp1)^.opcode=A_Jcc) and
  321. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  322. GetNextInstruction(hp1,hp2) and
  323. (hp2^.typ = ait_instruction) and
  324. (Paicpu(hp2)^.opcode = A_DEC) And
  325. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  326. GetNextInstruction(hp2, hp3) And
  327. (hp3^.typ = ait_instruction) and
  328. (Paicpu(hp3)^.is_jmp) and
  329. (Paicpu(hp3)^.opcode = A_JMP) And
  330. GetNextInstruction(hp3, hp4) And
  331. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  332. Then
  333. Begin
  334. Paicpu(hp2)^.Opcode := A_SUB;
  335. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  336. Paicpu(hp2)^.LoadConst(0,1);
  337. Paicpu(hp2)^.ops:=2;
  338. Paicpu(hp3)^.Opcode := A_Jcc;
  339. Case paicpu(hp1)^.condition of
  340. C_LE: Paicpu(hp3)^.condition := C_GE;
  341. C_BE: Paicpu(hp3)^.condition := C_AE;
  342. End;
  343. AsmL^.Remove(p);
  344. AsmL^.Remove(hp1);
  345. Dispose(p, Done);
  346. Dispose(hp1, Done);
  347. p := hp2;
  348. continue;
  349. End
  350. Else
  351. {$endif foropt}
  352. {change "cmp $0, %reg" to "test %reg, %reg"}
  353. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  354. Begin
  355. Paicpu(p)^.opcode := A_TEST;
  356. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  357. End;
  358. End;
  359. A_FLD:
  360. Begin
  361. If (Paicpu(p)^.oper[0].typ = top_reg) And
  362. GetNextInstruction(p, hp1) And
  363. (hp1^.typ = Ait_Instruction) And
  364. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  365. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  366. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  367. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  368. { change to
  369. fld reg fxxx reg,st
  370. fxxxp st, st1 (hp1)
  371. Remark: non commutative operations must be reversed!
  372. }
  373. begin
  374. Case Paicpu(hp1)^.opcode Of
  375. A_FMULP,A_FADDP,
  376. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  377. begin
  378. Case Paicpu(hp1)^.opcode Of
  379. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  380. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  381. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  382. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  383. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  384. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  385. End;
  386. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  387. Paicpu(hp1)^.oper[1].reg := R_ST;
  388. AsmL^.Remove(p);
  389. Dispose(p, Done);
  390. p := hp1;
  391. Continue;
  392. end;
  393. end;
  394. end
  395. else
  396. If (Paicpu(p)^.oper[0].typ = top_ref) And
  397. GetNextInstruction(p, hp2) And
  398. (hp2^.typ = Ait_Instruction) And
  399. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  400. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  401. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  402. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  403. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  404. If GetLastInstruction(p, hp1) And
  405. (hp1^.typ = Ait_Instruction) And
  406. ((Paicpu(hp1)^.opcode = A_FLD) Or
  407. (Paicpu(hp1)^.opcode = A_FST)) And
  408. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  409. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  410. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  411. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  412. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  413. { change to
  414. fld/fst mem1 (hp1) fld/fst mem1
  415. fld mem1 (p) fadd/
  416. faddp/ fmul st, st
  417. fmulp st, st1 (hp2) }
  418. Begin
  419. AsmL^.Remove(p);
  420. Dispose(p, Done);
  421. p := hp1;
  422. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  423. Paicpu(hp2)^.opcode := A_FADD
  424. Else
  425. Paicpu(hp2)^.opcode := A_FMUL;
  426. Paicpu(hp2)^.oper[1].reg := R_ST;
  427. End
  428. Else
  429. { change to
  430. fld/fst mem1 (hp1) fld/fst mem1
  431. fld mem1 (p) fld st}
  432. Begin
  433. Paicpu(p)^.changeopsize(S_FL);
  434. Paicpu(p)^.loadreg(0,R_ST);
  435. End
  436. Else
  437. Begin
  438. Case Paicpu(hp2)^.opcode Of
  439. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  440. { change to
  441. fld/fst mem1 (hp1) fld/fst mem1
  442. fld mem2 (p) fxxx mem2
  443. fxxxp st, st1 (hp2) }
  444. Begin
  445. Case Paicpu(hp2)^.opcode Of
  446. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  447. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  448. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  449. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  450. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  451. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  452. End;
  453. AsmL^.Remove(hp2);
  454. Dispose(hp2, Done)
  455. End
  456. End
  457. End
  458. End;
  459. A_FSTP,A_FISTP:
  460. Begin
  461. If (Paicpu(p)^.oper[0].typ = top_ref) And
  462. GetNextInstruction(p, hp1) And
  463. (Pai(hp1)^.typ = ait_instruction) And
  464. (((Paicpu(hp1)^.opcode = A_FLD) And
  465. (Paicpu(p)^.opcode = A_FSTP)) Or
  466. ((Paicpu(p)^.opcode = A_FISTP) And
  467. (Paicpu(hp1)^.opcode = A_FILD))) And
  468. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  469. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  470. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  471. Then
  472. Begin
  473. If GetNextInstruction(hp1, hp2) And
  474. (hp2^.typ = ait_instruction) And
  475. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  476. (Paicpu(hp2)^.opcode = A_RET)) And
  477. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  478. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  479. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  480. Then
  481. Begin
  482. AsmL^.Remove(p);
  483. AsmL^.Remove(hp1);
  484. Dispose(p, Done);
  485. Dispose(hp1, Done);
  486. p := hp2;
  487. Continue
  488. End
  489. Else
  490. {fst can't store an extended value!}
  491. If (Paicpu(p)^.opsize <> S_FX) And
  492. (Paicpu(p)^.opsize <> S_IQ) Then
  493. Begin
  494. If (Paicpu(p)^.opcode = A_FSTP) Then
  495. Paicpu(p)^.opcode := A_FST
  496. Else Paicpu(p)^.opcode := A_FIST;
  497. AsmL^.Remove(hp1);
  498. Dispose(hp1, done)
  499. End
  500. End;
  501. End;
  502. A_IMUL:
  503. {changes certain "imul const, %reg"'s to lea sequences}
  504. Begin
  505. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  506. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  507. (Paicpu(p)^.opsize = S_L) Then
  508. If (Paicpu(p)^.oper[0].val = 1) Then
  509. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  510. {remove "imul $1, reg"}
  511. Begin
  512. hp1 := Pai(p^.Next);
  513. AsmL^.Remove(p);
  514. Dispose(p, Done);
  515. p := hp1;
  516. Continue;
  517. End
  518. Else
  519. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  520. Begin
  521. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  522. hp1^.fileinfo := p^.fileinfo;
  523. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  524. Dispose(p, Done);
  525. p := hp1;
  526. End
  527. Else If
  528. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  529. (Paicpu(p)^.oper[2].typ = Top_None)) And
  530. (aktoptprocessor < ClassP6) And
  531. (Paicpu(p)^.oper[0].val <= 12) And
  532. Not(CS_LittleSize in aktglobalswitches) And
  533. (Not(GetNextInstruction(p, hp1)) Or
  534. {GetNextInstruction(p, hp1) And}
  535. Not((Pai(hp1)^.typ = ait_instruction) And
  536. ((paicpu(hp1)^.opcode=A_Jcc) and
  537. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  538. Then
  539. Begin
  540. Reset_reference(tmpref);
  541. Case Paicpu(p)^.oper[0].val Of
  542. 3: Begin
  543. {imul 3, reg1, reg2 to
  544. lea (reg1,reg1,2), reg2
  545. imul 3, reg1 to
  546. lea (reg1,reg1,2), reg1}
  547. TmpRef.base := Paicpu(p)^.oper[1].reg;
  548. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  549. TmpRef.ScaleFactor := 2;
  550. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  551. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  552. Else
  553. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  554. hp1^.fileinfo := p^.fileinfo;
  555. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  556. Dispose(p, Done);
  557. p := hp1;
  558. End;
  559. 5: Begin
  560. {imul 5, reg1, reg2 to
  561. lea (reg1,reg1,4), reg2
  562. imul 5, reg1 to
  563. lea (reg1,reg1,4), reg1}
  564. TmpRef.base := Paicpu(p)^.oper[1].reg;
  565. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  566. TmpRef.ScaleFactor := 4;
  567. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  568. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  569. Else
  570. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  571. hp1^.fileinfo:= p^.fileinfo;
  572. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  573. Dispose(p, Done);
  574. p := hp1;
  575. End;
  576. 6: Begin
  577. {imul 6, reg1, reg2 to
  578. lea (,reg1,2), reg2
  579. lea (reg2,reg1,4), reg2
  580. imul 6, reg1 to
  581. lea (reg1,reg1,2), reg1
  582. add reg1, reg1}
  583. If (aktoptprocessor <= Class386)
  584. Then
  585. Begin
  586. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  587. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  588. Then
  589. Begin
  590. TmpRef.base := Paicpu(p)^.oper[2].reg;
  591. TmpRef.ScaleFactor := 4;
  592. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  593. End
  594. Else
  595. Begin
  596. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  597. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  598. End;
  599. hp1^.fileinfo := p^.fileinfo;
  600. InsertLLItem(AsmL,p, p^.next, hp1);
  601. Reset_reference(tmpref);
  602. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  603. TmpRef.ScaleFactor := 2;
  604. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  605. Then
  606. Begin
  607. TmpRef.base := R_NO;
  608. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  609. Paicpu(p)^.oper[2].reg));
  610. End
  611. Else
  612. Begin
  613. TmpRef.base := Paicpu(p)^.oper[1].reg;
  614. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  615. End;
  616. hp1^.fileinfo := p^.fileinfo;
  617. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  618. Dispose(p, Done);
  619. p := Pai(hp1^.next);
  620. End
  621. End;
  622. 9: Begin
  623. {imul 9, reg1, reg2 to
  624. lea (reg1,reg1,8), reg2
  625. imul 9, reg1 to
  626. lea (reg1,reg1,8), reg1}
  627. TmpRef.base := Paicpu(p)^.oper[1].reg;
  628. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  629. TmpRef.ScaleFactor := 8;
  630. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  631. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  632. Else
  633. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  634. hp1^.fileinfo := p^.fileinfo;
  635. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  636. Dispose(p, Done);
  637. p := hp1;
  638. End;
  639. 10: Begin
  640. {imul 10, reg1, reg2 to
  641. lea (reg1,reg1,4), reg2
  642. add reg2, reg2
  643. imul 10, reg1 to
  644. lea (reg1,reg1,4), reg1
  645. add reg1, reg1}
  646. If (aktoptprocessor <= Class386) Then
  647. Begin
  648. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  649. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  650. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  651. Else
  652. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  653. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  654. hp1^.fileinfo := p^.fileinfo;
  655. InsertLLItem(AsmL,p, p^.next, hp1);
  656. TmpRef.base := Paicpu(p)^.oper[1].reg;
  657. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  658. TmpRef.ScaleFactor := 4;
  659. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  660. Then
  661. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  662. Else
  663. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  664. hp1^.fileinfo := p^.fileinfo;
  665. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  666. Dispose(p, Done);
  667. p := Pai(hp1^.next);
  668. End
  669. End;
  670. 12: Begin
  671. {imul 12, reg1, reg2 to
  672. lea (,reg1,4), reg2
  673. lea (,reg1,8) reg2
  674. imul 12, reg1 to
  675. lea (reg1,reg1,2), reg1
  676. lea (,reg1,4), reg1}
  677. If (aktoptprocessor <= Class386)
  678. Then
  679. Begin
  680. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  681. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  682. Begin
  683. TmpRef.base := Paicpu(p)^.oper[2].reg;
  684. TmpRef.ScaleFactor := 8;
  685. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  686. End
  687. Else
  688. Begin
  689. TmpRef.base := R_NO;
  690. TmpRef.ScaleFactor := 4;
  691. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  692. End;
  693. hp1^.fileinfo := p^.fileinfo;
  694. InsertLLItem(AsmL,p, p^.next, hp1);
  695. Reset_reference(tmpref);
  696. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  697. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  698. Begin
  699. TmpRef.base := R_NO;
  700. TmpRef.ScaleFactor := 4;
  701. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  702. End
  703. Else
  704. Begin
  705. TmpRef.base := Paicpu(p)^.oper[1].reg;
  706. TmpRef.ScaleFactor := 2;
  707. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  708. End;
  709. hp1^.fileinfo := p^.fileinfo;
  710. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  711. Dispose(p, Done);
  712. p := Pai(hp1^.next);
  713. End
  714. End
  715. End;
  716. End;
  717. End;
  718. A_LEA:
  719. Begin
  720. {removes seg register prefixes from LEA operations, as they
  721. don't do anything}
  722. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  723. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  724. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  725. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  726. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  727. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  728. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  729. Then
  730. Begin
  731. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  732. Paicpu(p)^.oper[1].reg));
  733. hp1^.fileinfo := p^.fileinfo;
  734. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  735. Dispose(p, Done);
  736. p := hp1;
  737. Continue;
  738. End
  739. Else
  740. Begin
  741. hp1 := Pai(p^.Next);
  742. AsmL^.Remove(p);
  743. Dispose(p, Done);
  744. p := hp1;
  745. Continue;
  746. End;
  747. End;
  748. A_MOV:
  749. Begin
  750. TmpUsedRegs := UsedRegs;
  751. If (Paicpu(p)^.oper[1].typ = top_reg) And
  752. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  753. GetNextInstruction(p, hp1) And
  754. (Pai(hp1)^.typ = ait_instruction) And
  755. (Paicpu(hp1)^.opcode = A_MOV) And
  756. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  757. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  758. Then
  759. {we have "mov x, %treg; mov %treg, y}
  760. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  761. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  762. Case Paicpu(p)^.oper[0].typ Of
  763. top_reg:
  764. Begin
  765. { change "mov %reg, %treg; mov %treg, y"
  766. to "mov %reg, y" }
  767. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  768. AsmL^.Remove(p);
  769. Dispose(p, Done);
  770. p := hp1;
  771. continue;
  772. End;
  773. top_ref:
  774. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  775. Begin
  776. { change "mov mem, %treg; mov %treg, %reg"
  777. to "mov mem, %reg" }
  778. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  779. AsmL^.Remove(hp1);
  780. Dispose(hp1, Done);
  781. continue;
  782. End;
  783. End
  784. Else
  785. Else
  786. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  787. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  788. penalty}
  789. If (Paicpu(p)^.oper[0].typ = top_reg) And
  790. (Paicpu(p)^.oper[1].typ = top_reg) And
  791. GetNextInstruction(p,hp1) And
  792. (Pai(hp1)^.typ = ait_instruction) And
  793. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  794. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  795. Then
  796. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  797. Begin
  798. If ((Paicpu(hp1)^.opcode = A_OR) Or
  799. (Paicpu(hp1)^.opcode = A_TEST)) And
  800. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  801. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  802. Then
  803. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  804. Begin
  805. TmpUsedRegs := UsedRegs;
  806. If GetNextInstruction(hp1, hp2) And
  807. (hp2^.typ = ait_instruction) And
  808. paicpu(hp2)^.is_jmp and
  809. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  810. Then
  811. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  812. "test %reg1, %reg1; jxx"}
  813. Begin
  814. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  815. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  816. AsmL^.Remove(p);
  817. Dispose(p, done);
  818. p := hp1;
  819. continue
  820. End
  821. Else
  822. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  823. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  824. Begin
  825. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  826. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  827. End;
  828. End
  829. { Else
  830. If (Paicpu(p^.next)^.opcode
  831. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  832. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  833. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  834. End
  835. Else
  836. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  837. x >= RetOffset) as it doesn't do anything (it writes either to a
  838. parameter or to the temporary storage room for the function
  839. result)}
  840. If GetNextInstruction(p, hp1) And
  841. (Pai(hp1)^.typ = ait_instruction)
  842. Then
  843. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  844. (Paicpu(hp1)^.opcode = A_RET)) And
  845. (Paicpu(p)^.oper[1].typ = top_ref) And
  846. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  847. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  848. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  849. (Paicpu(p)^.oper[0].typ = top_reg)
  850. Then
  851. Begin
  852. AsmL^.Remove(p);
  853. Dispose(p, done);
  854. p := hp1;
  855. End
  856. Else
  857. If (Paicpu(p)^.oper[0].typ = top_reg) And
  858. (Paicpu(p)^.oper[1].typ = top_ref) And
  859. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  860. (Paicpu(hp1)^.opcode = A_CMP) And
  861. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  862. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  863. Then
  864. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  865. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  866. { Next instruction is also a MOV ? }
  867. If GetNextInstruction(p, hp1) And
  868. (pai(hp1)^.typ = ait_instruction) and
  869. (Paicpu(hp1)^.opcode = A_MOV) and
  870. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  871. Then
  872. Begin
  873. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  874. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  875. Then
  876. {mov reg1, mem1 or mov mem1, reg1
  877. mov mem2, reg2 mov reg2, mem2}
  878. Begin
  879. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  880. {mov reg1, mem1 or mov mem1, reg1
  881. mov mem2, reg1 mov reg2, mem1}
  882. Begin
  883. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  884. { Removes the second statement from
  885. mov reg1, mem1
  886. mov mem1, reg1 }
  887. Begin
  888. AsmL^.remove(hp1);
  889. Dispose(hp1,done);
  890. End
  891. Else
  892. Begin
  893. TmpUsedRegs := UsedRegs;
  894. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  895. If (Paicpu(p)^.oper[0].typ = top_reg) And
  896. { mov reg1, mem1
  897. mov mem2, reg1 }
  898. GetNextInstruction(hp1, hp2) And
  899. (hp2^.typ = ait_instruction) And
  900. (Paicpu(hp2)^.opcode = A_CMP) And
  901. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  902. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  903. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  904. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  905. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  906. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  907. { change to
  908. mov reg1, mem1 mov reg1, mem1
  909. mov mem2, reg1 cmp reg1, mem2
  910. cmp mem1, reg1 }
  911. Begin
  912. AsmL^.Remove(hp2);
  913. Dispose(hp2, Done);
  914. Paicpu(hp1)^.opcode := A_CMP;
  915. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  916. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  917. End;
  918. End;
  919. End
  920. Else
  921. Begin
  922. If GetNextInstruction(hp1, hp2) And
  923. (Paicpu(p)^.oper[0].typ = top_ref) And
  924. (Paicpu(p)^.oper[1].typ = top_reg) And
  925. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  926. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  927. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  928. (Pai(hp2)^.typ = ait_instruction) And
  929. (Paicpu(hp2)^.opcode = A_MOV) And
  930. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  931. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  932. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  933. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^)
  934. Then
  935. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI])
  936. Then
  937. { mov mem1, %edi
  938. mov %edi, mem2
  939. mov mem2, reg2
  940. to:
  941. mov mem1, reg2
  942. mov reg2, mem2}
  943. Begin
  944. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  945. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  946. AsmL^.Remove(hp2);
  947. Dispose(hp2,Done);
  948. End
  949. Else
  950. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  951. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  952. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  953. Then
  954. { mov mem1, reg1 mov mem1, reg1
  955. mov reg1, mem2 mov reg1, mem2
  956. mov mem2, reg2 mov mem2, reg1
  957. to: to:
  958. mov mem1, reg1 mov mem1, reg1
  959. mov mem1, reg2 mov reg1, mem2
  960. mov reg1, mem2
  961. or (if mem1 depends on reg1
  962. and/or if mem2 depends on reg2)
  963. to:
  964. mov mem1, reg1
  965. mov reg1, mem2
  966. mov reg1, reg2
  967. }
  968. Begin
  969. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  970. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  971. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  972. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  973. End
  974. Else
  975. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  976. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  977. Else
  978. Begin
  979. AsmL^.Remove(hp2);
  980. Dispose(hp2, Done);
  981. End
  982. End;
  983. End
  984. Else
  985. (* {movl [mem1],reg1
  986. movl [mem1],reg2
  987. to:
  988. movl [mem1],reg1
  989. movl reg1,reg2 }
  990. If (Paicpu(p)^.oper[0].typ = top_ref) and
  991. (Paicpu(p)^.oper[1].typ = top_reg) and
  992. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  993. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  994. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  995. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  996. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  997. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  998. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  999. Else*)
  1000. { movl const1,[mem1]
  1001. movl [mem1],reg1
  1002. to:
  1003. movl const1,reg1
  1004. movl reg1,[mem1] }
  1005. If (Paicpu(p)^.oper[0].typ = top_const) and
  1006. (Paicpu(p)^.oper[1].typ = top_ref) and
  1007. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1008. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1009. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1010. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1011. Begin
  1012. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1013. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1014. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1015. End
  1016. End;
  1017. End;
  1018. A_MOVZX:
  1019. Begin
  1020. {removes superfluous And's after movzx's}
  1021. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1022. GetNextInstruction(p, hp1) And
  1023. (Pai(hp1)^.typ = ait_instruction) And
  1024. (Paicpu(hp1)^.opcode = A_AND) And
  1025. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1026. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1027. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1028. Then
  1029. Case Paicpu(p)^.opsize Of
  1030. S_BL, S_BW:
  1031. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1032. Begin
  1033. AsmL^.Remove(hp1);
  1034. Dispose(hp1, Done);
  1035. End;
  1036. S_WL:
  1037. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1038. Begin
  1039. AsmL^.Remove(hp1);
  1040. Dispose(hp1, Done);
  1041. End;
  1042. End;
  1043. {changes some movzx constructs to faster synonims (all examples
  1044. are given with eax/ax, but are also valid for other registers)}
  1045. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1046. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1047. Case Paicpu(p)^.opsize of
  1048. S_BW:
  1049. Begin
  1050. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1051. Not(CS_LittleSize In aktglobalswitches)
  1052. Then
  1053. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1054. Begin
  1055. Paicpu(p)^.opcode := A_AND;
  1056. Paicpu(p)^.changeopsize(S_W);
  1057. Paicpu(p)^.LoadConst(0,$ff);
  1058. End
  1059. Else
  1060. If GetNextInstruction(p, hp1) And
  1061. (Pai(hp1)^.typ = ait_instruction) And
  1062. (Paicpu(hp1)^.opcode = A_AND) And
  1063. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1064. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1065. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1066. Then
  1067. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1068. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1069. Begin
  1070. Paicpu(p)^.opcode := A_MOV;
  1071. Paicpu(p)^.changeopsize(S_W);
  1072. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1073. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1074. End;
  1075. End;
  1076. S_BL:
  1077. Begin
  1078. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1079. Not(CS_LittleSize in aktglobalswitches)
  1080. Then
  1081. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1082. Begin
  1083. Paicpu(p)^.opcode := A_AND;
  1084. Paicpu(p)^.changeopsize(S_L);
  1085. Paicpu(p)^.loadconst(0,$ff)
  1086. End
  1087. Else
  1088. If GetNextInstruction(p, hp1) And
  1089. (Pai(hp1)^.typ = ait_instruction) And
  1090. (Paicpu(hp1)^.opcode = A_AND) And
  1091. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1092. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1093. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1094. Then
  1095. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1096. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1097. Begin
  1098. Paicpu(p)^.opcode := A_MOV;
  1099. Paicpu(p)^.changeopsize(S_L);
  1100. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1101. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1102. End
  1103. End;
  1104. S_WL:
  1105. Begin
  1106. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1107. Not(CS_LittleSize In aktglobalswitches)
  1108. Then
  1109. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1110. Begin
  1111. Paicpu(p)^.opcode := A_AND;
  1112. Paicpu(p)^.changeopsize(S_L);
  1113. Paicpu(p)^.LoadConst(0,$ffff);
  1114. End
  1115. Else
  1116. If GetNextInstruction(p, hp1) And
  1117. (Pai(hp1)^.typ = ait_instruction) And
  1118. (Paicpu(hp1)^.opcode = A_AND) And
  1119. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1120. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1121. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1122. Then
  1123. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1124. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1125. Begin
  1126. Paicpu(p)^.opcode := A_MOV;
  1127. Paicpu(p)^.changeopsize(S_L);
  1128. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1129. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1130. End;
  1131. End;
  1132. End
  1133. Else
  1134. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1135. Begin
  1136. If GetNextInstruction(p, hp1) And
  1137. (Pai(hp1)^.typ = ait_instruction) And
  1138. (Paicpu(hp1)^.opcode = A_AND) And
  1139. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1140. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1141. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1142. Begin
  1143. Paicpu(p)^.opcode := A_MOV;
  1144. Case Paicpu(p)^.opsize Of
  1145. S_BL:
  1146. Begin
  1147. Paicpu(p)^.changeopsize(S_L);
  1148. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1149. End;
  1150. S_WL:
  1151. Begin
  1152. Paicpu(p)^.changeopsize(S_L);
  1153. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1154. End;
  1155. S_BW:
  1156. Begin
  1157. Paicpu(p)^.changeopsize(S_W);
  1158. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1159. End;
  1160. End;
  1161. End;
  1162. End;
  1163. End;
  1164. A_POP:
  1165. Begin
  1166. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1167. GetNextInstruction(p, hp1) And
  1168. (pai(hp1)^.typ=ait_instruction) and
  1169. (Paicpu(hp1)^.opcode=A_PUSH) and
  1170. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1171. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1172. { This can't be done, because the register which is popped
  1173. can still be used after the push (PFV)
  1174. If (Not(cs_regalloc in aktglobalswitches)) Then
  1175. Begin
  1176. hp2:=pai(hp1^.next);
  1177. asml^.remove(p);
  1178. asml^.remove(hp1);
  1179. dispose(p,done);
  1180. dispose(hp1,done);
  1181. p:=hp2;
  1182. continue
  1183. End
  1184. Else }
  1185. Begin
  1186. { change it to a two op operation }
  1187. Paicpu(p)^.oper[1].typ:=top_none;
  1188. Paicpu(p)^.ops:=2;
  1189. Paicpu(p)^.opcode := A_MOV;
  1190. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1191. Reset_reference(tmpref);
  1192. TmpRef.base := R_ESP;
  1193. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1194. AsmL^.Remove(hp1);
  1195. Dispose(hp1, Done)
  1196. End;
  1197. end;
  1198. A_PUSH:
  1199. Begin
  1200. If (Paicpu(p)^.opsize = S_W) And
  1201. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1202. GetNextInstruction(p, hp1) And
  1203. (Pai(hp1)^.typ = ait_instruction) And
  1204. (Paicpu(hp1)^.opcode = A_PUSH) And
  1205. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1206. (Paicpu(hp1)^.opsize = S_W) Then
  1207. Begin
  1208. Paicpu(p)^.changeopsize(S_L);
  1209. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + Paicpu(hp1)^.oper[0].val);
  1210. AsmL^.Remove(hp1);
  1211. Dispose(hp1, Done)
  1212. End;
  1213. End;
  1214. A_SHL, A_SAL:
  1215. Begin
  1216. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1217. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1218. (Paicpu(p)^.opsize = S_L) And
  1219. (Paicpu(p)^.oper[0].val <= 3)
  1220. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1221. Then
  1222. Begin
  1223. TmpBool1 := True; {should we check the next instruction?}
  1224. TmpBool2 := False; {have we found an add/sub which could be
  1225. integrated in the lea?}
  1226. Reset_reference(tmpref);
  1227. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1228. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1229. While TmpBool1 And
  1230. GetNextInstruction(p, hp1) And
  1231. (Pai(hp1)^.typ = ait_instruction) And
  1232. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1233. (Paicpu(hp1)^.opcode = A_SUB)) And
  1234. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1235. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1236. Begin
  1237. TmpBool1 := False;
  1238. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1239. Then
  1240. Begin
  1241. TmpBool1 := True;
  1242. TmpBool2 := True;
  1243. If Paicpu(hp1)^.opcode = A_ADD Then
  1244. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1245. Else
  1246. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1247. AsmL^.Remove(hp1);
  1248. Dispose(hp1, Done);
  1249. End
  1250. Else
  1251. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1252. (Paicpu(hp1)^.opcode = A_ADD) And
  1253. (TmpRef.base = R_NO) Then
  1254. Begin
  1255. TmpBool1 := True;
  1256. TmpBool2 := True;
  1257. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1258. AsmL^.Remove(hp1);
  1259. Dispose(hp1, Done);
  1260. End;
  1261. End;
  1262. If TmpBool2 Or
  1263. ((aktoptprocessor < ClassP6) And
  1264. (Paicpu(p)^.oper[0].val <= 3) And
  1265. Not(CS_LittleSize in aktglobalswitches))
  1266. Then
  1267. Begin
  1268. If Not(TmpBool2) And
  1269. (Paicpu(p)^.oper[0].val = 1)
  1270. Then
  1271. Begin
  1272. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1273. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1274. End
  1275. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1276. Paicpu(p)^.oper[1].reg));
  1277. hp1^.fileinfo := p^.fileinfo;
  1278. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1279. Dispose(p, Done);
  1280. p := hp1;
  1281. End;
  1282. End
  1283. Else
  1284. If (aktoptprocessor < ClassP6) And
  1285. (Paicpu(p)^.oper[0].typ = top_const) And
  1286. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1287. If (Paicpu(p)^.oper[0].val = 1)
  1288. Then
  1289. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1290. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1291. (unlike shl, which is only pairable in the U pipe)}
  1292. Begin
  1293. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1294. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1295. hp1^.fileinfo := p^.fileinfo;
  1296. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1297. Dispose(p, done);
  1298. p := hp1;
  1299. End
  1300. Else If (Paicpu(p)^.opsize = S_L) and
  1301. (Paicpu(p)^.oper[0].val<= 3) Then
  1302. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1303. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1304. Begin
  1305. Reset_reference(tmpref);
  1306. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1307. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1308. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1309. hp1^.fileinfo := p^.fileinfo;
  1310. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1311. Dispose(p, done);
  1312. p := hp1;
  1313. End
  1314. End;
  1315. A_SAR, A_SHR:
  1316. {changes the code sequence
  1317. shr/sar const1, x
  1318. shl const2, x
  1319. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1320. Begin
  1321. If GetNextInstruction(p, hp1) And
  1322. (pai(hp1)^.typ = ait_instruction) and
  1323. (Paicpu(hp1)^.opcode = A_SHL) and
  1324. (Paicpu(p)^.oper[0].typ = top_const) and
  1325. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1326. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1327. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1328. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1329. Then
  1330. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1331. Not(CS_LittleSize In aktglobalswitches)
  1332. Then
  1333. { shr/sar const1, %reg
  1334. shl const2, %reg
  1335. with const1 > const2 }
  1336. Begin
  1337. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1338. Paicpu(hp1)^.opcode := A_AND;
  1339. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1340. Case Paicpu(p)^.opsize Of
  1341. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1342. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1343. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1344. End;
  1345. End
  1346. Else
  1347. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1348. Not(CS_LittleSize In aktglobalswitches)
  1349. Then
  1350. { shr/sar const1, %reg
  1351. shl const2, %reg
  1352. with const1 < const2 }
  1353. Begin
  1354. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1355. Paicpu(p)^.opcode := A_AND;
  1356. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1357. Case Paicpu(p)^.opsize Of
  1358. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1359. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1360. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1361. End;
  1362. End
  1363. Else
  1364. { shr/sar const1, %reg
  1365. shl const2, %reg
  1366. with const1 = const2 }
  1367. Begin
  1368. Paicpu(p)^.opcode := A_AND;
  1369. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1370. Case Paicpu(p)^.opsize Of
  1371. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1372. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1373. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1374. End;
  1375. AsmL^.remove(hp1);
  1376. dispose(hp1, done);
  1377. End;
  1378. End;
  1379. A_SETcc :
  1380. Begin
  1381. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1382. GetNextInstruction(p, hp1) And
  1383. GetNextInstruction(hp1, hp2) And
  1384. (hp2^.typ = ait_instruction) And
  1385. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1386. (Paicpu(hp2)^.opcode = A_RET)) And
  1387. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1388. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1389. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1390. (hp1^.typ = ait_instruction) And
  1391. (Paicpu(hp1)^.opcode = A_MOV) And
  1392. (Paicpu(hp1)^.opsize = S_B) And
  1393. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1394. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1395. Begin
  1396. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1397. AsmL^.Remove(hp1);
  1398. Dispose(hp1, Done)
  1399. End
  1400. End;
  1401. A_SUB:
  1402. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1403. { * change "sub/add const1, reg" or "dec reg" followed by
  1404. "sub const2, reg" to one "sub ..., reg" }
  1405. Begin
  1406. If (Paicpu(p)^.oper[0].typ = top_const) And
  1407. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1408. If (Paicpu(p)^.oper[0].val = 2) And
  1409. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1410. Begin
  1411. hp1 := Pai(p^.next);
  1412. While Assigned(hp1) And
  1413. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1414. Not((Pai(hp1)^.typ = ait_instruction) And
  1415. ((Paicpu(hp1)^.opcode = A_CALL) or
  1416. (Paicpu(hp1)^.opcode = A_PUSH) or
  1417. ((Paicpu(hp1)^.opcode = A_MOV) And
  1418. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1419. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1420. hp1 := Pai(hp1^.next);
  1421. If Assigned(hp1) And
  1422. (Pai(hp1)^.typ = ait_instruction) And
  1423. (Paicpu(hp1)^.opcode = A_PUSH) And
  1424. (Paicpu(hp1)^.opsize = S_W)
  1425. Then
  1426. Begin
  1427. Paicpu(hp1)^.changeopsize(S_L);
  1428. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1429. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1430. hp1 := Pai(p^.next);
  1431. AsmL^.Remove(p);
  1432. Dispose(p, Done);
  1433. p := hp1;
  1434. Continue
  1435. End;
  1436. If DoSubAddOpt(p) Then continue;
  1437. End
  1438. Else If DoSubAddOpt(p) Then Continue
  1439. End;
  1440. A_TEST, A_OR:
  1441. {removes the line marked with (x) from the sequence
  1442. And/or/xor/add/sub/... $x, %y
  1443. test/or %y, %y (x)
  1444. j(n)z _Label
  1445. as the first instruction already adjusts the ZF}
  1446. Begin
  1447. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1448. If GetLastInstruction(p, hp1) And
  1449. (pai(hp1)^.typ = ait_instruction) Then
  1450. Case Paicpu(hp1)^.opcode Of
  1451. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1452. Begin
  1453. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1454. Begin
  1455. hp1 := pai(p^.next);
  1456. asml^.remove(p);
  1457. dispose(p, done);
  1458. p := pai(hp1);
  1459. continue
  1460. End;
  1461. End;
  1462. A_DEC, A_INC, A_NEG:
  1463. Begin
  1464. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1465. Begin
  1466. Case Paicpu(hp1)^.opcode Of
  1467. A_DEC, A_INC:
  1468. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1469. Begin
  1470. Case Paicpu(hp1)^.opcode Of
  1471. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1472. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1473. End;
  1474. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1475. Paicpu(hp1)^.LoadConst(0,1);
  1476. Paicpu(hp1)^.ops:=2;
  1477. End
  1478. End;
  1479. hp1 := pai(p^.next);
  1480. asml^.remove(p);
  1481. dispose(p, done);
  1482. p := pai(hp1);
  1483. continue
  1484. End;
  1485. End
  1486. End
  1487. Else
  1488. End;
  1489. A_XOR:
  1490. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1491. (Paicpu(p)^.oper[1].typ = top_reg) And
  1492. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1493. { temporarily change this to 'mov reg,0' to make it easier }
  1494. { for the CSE. Will be changed back in pass 2 }
  1495. begin
  1496. paicpu(p)^.opcode := A_MOV;
  1497. paicpu(p)^.loadconst(0,0);
  1498. end;
  1499. End;
  1500. end; { if is_jmp }
  1501. End;
  1502. { ait_label:
  1503. Begin
  1504. If Not(Pai_Label(p)^.l^.is_used)
  1505. Then
  1506. Begin
  1507. hp1 := Pai(p^.next);
  1508. AsmL^.Remove(p);
  1509. Dispose(p, Done);
  1510. p := hp1;
  1511. Continue
  1512. End;
  1513. End;}
  1514. End;
  1515. p:=pai(p^.next);
  1516. end;
  1517. end;
  1518. {$ifdef foldArithOps}
  1519. Function IsArithOp(opcode: TAsmOp): Boolean;
  1520. Begin
  1521. IsArithOp := False;
  1522. Case opcode Of
  1523. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1524. End;
  1525. End;
  1526. {$endif foldArithOps}
  1527. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1528. var
  1529. p,hp1,hp2: pai;
  1530. {$ifdef foldArithOps}
  1531. UsedRegs, TmpUsedRegs: TRegSet;
  1532. {$endif foldArithOps}
  1533. Begin
  1534. P := BlockStart;
  1535. {$ifdef foldArithOps}
  1536. UsedRegs := [];
  1537. {$endif foldArithOps}
  1538. While (P <> BlockEnd) Do
  1539. Begin
  1540. {$ifdef foldArithOps}
  1541. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1542. {$endif foldArithOps}
  1543. Case P^.Typ Of
  1544. Ait_Instruction:
  1545. Begin
  1546. Case Paicpu(p)^.opcode Of
  1547. A_CALL:
  1548. If (AktOptProcessor < ClassP6) And
  1549. GetNextInstruction(p, hp1) And
  1550. (hp1^.typ = ait_instruction) And
  1551. (paicpu(hp1)^.opcode = A_JMP) Then
  1552. Begin
  1553. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1554. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1555. hp2^.fileinfo := p^.fileinfo;
  1556. InsertLLItem(AsmL, p^.previous, p, hp2);
  1557. Paicpu(p)^.opcode := A_JMP;
  1558. AsmL^.Remove(hp1);
  1559. Dispose(hp1, Done)
  1560. End;
  1561. A_MOV:
  1562. Begin
  1563. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1564. (Paicpu(p)^.oper[1].typ = top_reg) And
  1565. GetNextInstruction(p, hp1) And
  1566. (hp1^.typ = ait_Instruction) And
  1567. ((Paicpu(hp1)^.opcode = A_MOV) or
  1568. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1569. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1570. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1571. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1572. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1573. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1574. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1575. {mov reg1, reg2
  1576. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1577. Begin
  1578. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1579. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1580. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1581. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1582. AsmL^.Remove(p);
  1583. Dispose(p, Done);
  1584. p := hp1;
  1585. Continue;
  1586. End
  1587. {$ifdef foldArithOps}
  1588. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1589. GetNextInstruction(p,hp1) And
  1590. (hp1^.typ = ait_instruction) And
  1591. IsArithOp(Paicpu(hp1)^.opcode) And
  1592. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1593. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1594. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1595. GetNextInstruction(hp1,hp2) And
  1596. (hp2^.typ = ait_instruction) And
  1597. (Paicpu(hp2)^.opcode = A_MOV) And
  1598. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1599. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1600. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1601. Begin
  1602. TmpUsedRegs := UsedRegs;
  1603. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1604. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1605. Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
  1606. hp2, TmpUsedRegs)))
  1607. Then
  1608. { change mov (ref), reg }
  1609. { add/sub/or/... reg2/$const, reg }
  1610. { mov (reg), ref }
  1611. { # relaese reg }
  1612. { to add/sub/or/... reg2/$const, (ref) }
  1613. Begin
  1614. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1615. AsmL^.Remove(p);
  1616. AsmL^.Remove(hp2);
  1617. Dispose(p,done);
  1618. Dispose(hp2,Done);
  1619. p := hp1
  1620. End;
  1621. End
  1622. {$endif foldArithOps}
  1623. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1624. (Paicpu(p)^.oper[0].val = 0) And
  1625. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1626. { change "mov $0, %reg" into "xor %reg, %reg" }
  1627. Begin
  1628. Paicpu(p)^.opcode := A_XOR;
  1629. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1630. End
  1631. End;
  1632. A_MOVZX:
  1633. Begin
  1634. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1635. If (Paicpu(p)^.oper[0].typ = top_reg)
  1636. Then
  1637. Case Paicpu(p)^.opsize of
  1638. S_BL:
  1639. Begin
  1640. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1641. Not(CS_LittleSize in aktglobalswitches) And
  1642. (aktoptprocessor = ClassP5)
  1643. Then
  1644. {Change "movzbl %reg1, %reg2" to
  1645. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1646. PentiumMMX}
  1647. Begin
  1648. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1649. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1650. hp1^.fileinfo := p^.fileinfo;
  1651. InsertLLItem(AsmL,p^.previous, p, hp1);
  1652. Paicpu(p)^.opcode := A_MOV;
  1653. Paicpu(p)^.changeopsize(S_B);
  1654. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1655. End;
  1656. End;
  1657. End
  1658. Else
  1659. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1660. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1661. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1662. Not(CS_LittleSize in aktglobalswitches) And
  1663. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1664. (aktoptprocessor = ClassP5) And
  1665. (Paicpu(p)^.opsize = S_BL)
  1666. Then
  1667. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1668. Pentium and PentiumMMX}
  1669. Begin
  1670. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1671. Paicpu(p)^.oper[1].reg));
  1672. hp1^.fileinfo := p^.fileinfo;
  1673. Paicpu(p)^.opcode := A_MOV;
  1674. Paicpu(p)^.changeopsize(S_B);
  1675. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1676. InsertLLItem(AsmL,p^.previous, p, hp1);
  1677. End;
  1678. End;
  1679. End;
  1680. End;
  1681. End;
  1682. p := Pai(p^.next)
  1683. End;
  1684. End;
  1685. End.
  1686. {
  1687. $Log$
  1688. Revision 1.78 2000-01-11 17:14:49 jonas
  1689. * fixed a serious memory leak
  1690. Revision 1.77 2000/01/09 12:35:02 jonas
  1691. * changed edi allocation to use getexplicitregister32/ungetregister
  1692. (adapted tgeni386 a bit for this) and enabled it by default
  1693. * fixed very big and stupid bug of mine in cg386mat that broke the
  1694. include() code (and make cycle :( ) if you compiled without
  1695. -dnewoptimizations
  1696. Revision 1.76 2000/01/07 01:14:30 peter
  1697. * updated copyright to 2000
  1698. Revision 1.75 1999/12/30 17:56:44 peter
  1699. * fixed and;jmp being translated into test;jmp
  1700. Revision 1.74 1999/12/05 16:48:43 jonas
  1701. * CSE of constant loading in regs works properly again
  1702. + if a constant is stored into memory using "mov const, ref" and
  1703. there is a reg that contains this const, it is changed into
  1704. "mov reg, ref"
  1705. Revision 1.73 1999/12/02 11:26:41 peter
  1706. * newoptimizations define added
  1707. Revision 1.72 1999/11/30 10:40:45 peter
  1708. + ttype, tsymlist
  1709. Revision 1.71 1999/11/27 23:47:55 jonas
  1710. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1711. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1712. Enable with -dfoldArithOps
  1713. Revision 1.70 1999/11/21 13:09:41 jonas
  1714. * fixed some missed optimizations because 8bit regs were not always
  1715. taken into account
  1716. Revision 1.69 1999/11/13 19:03:56 jonas
  1717. * don't remove align objects between JMP's and labels
  1718. Revision 1.68 1999/11/06 16:24:00 jonas
  1719. * getfinaldestination works completely again (a lot of functionality
  1720. got lost in the conversion resulting from the removal of
  1721. ait_labeled_instruction)
  1722. Revision 1.67 1999/11/06 14:34:23 peter
  1723. * truncated log to 20 revs
  1724. Revision 1.66 1999/09/27 23:44:55 peter
  1725. * procinfo is now a pointer
  1726. * support for result setting in sub procedure
  1727. Revision 1.65 1999/09/05 14:27:19 florian
  1728. + fld reg;fxxx to fxxxr reg optimization
  1729. Revision 1.64 1999/08/25 12:00:02 jonas
  1730. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1731. Revision 1.63 1999/08/23 10:20:46 jonas
  1732. * fixed pop/push optmization
  1733. Revision 1.62 1999/08/10 12:30:00 pierre
  1734. * avoid unused locals
  1735. Revision 1.61 1999/08/05 15:02:48 jonas
  1736. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1737. Revision 1.60 1999/08/04 00:23:16 florian
  1738. * renamed i386asm and i386base to cpuasm and cpubase
  1739. Revision 1.59 1999/08/03 17:13:28 jonas
  1740. * fix for sar/shr-shl optimization
  1741. Revision 1.58 1999/07/30 18:17:55 jonas
  1742. * fix so (,reg) gets optimized to (reg)
  1743. Revision 1.57 1999/07/01 18:12:16 jonas
  1744. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1745. a movzx or movsx
  1746. Revision 1.56 1999/06/23 12:33:52 jonas
  1747. * merged
  1748. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1749. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1750. Revision 1.55 1999/06/18 09:55:31 peter
  1751. * merged
  1752. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1753. * pop;push -> mov (esp),reg always instead of being removed
  1754. Revision 1.54 1999/05/27 19:44:49 peter
  1755. * removed oldasm
  1756. * plabel -> pasmlabel
  1757. * -a switches to source writing automaticly
  1758. * assembler readers OOPed
  1759. * asmsymbol automaticly external
  1760. * jumptables and other label fixes for asm readers
  1761. Revision 1.53 1999/05/12 00:19:52 peter
  1762. * removed R_DEFAULT_SEG
  1763. * uniform float names
  1764. Revision 1.52 1999/05/05 16:19:04 jonas
  1765. + remove the segment prefixes from LEA instructions
  1766. Revision 1.51 1999/05/05 10:05:54 florian
  1767. * a delphi compiled compiler recompiles ppc
  1768. Revision 1.50 1999/05/02 21:33:55 florian
  1769. * several bugs regarding -Or fixed
  1770. Revision 1.49 1999/05/02 14:26:31 peter
  1771. * fixed dec -> sub $1 opt which didn't set ops=2
  1772. }