cgcpu.pas 66 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  74. procedure a_adjust_sp(list: TAsmList; value: longint);
  75. function GetLoad(const ref : treference) : tasmop;
  76. function GetStore(const ref: treference): tasmop;
  77. protected
  78. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  79. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  80. end;
  81. tcg64favr = class(tcg64f32)
  82. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  83. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  84. end;
  85. procedure create_codegen;
  86. const
  87. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  88. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  89. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  90. implementation
  91. uses
  92. globals,verbose,systems,cutils,
  93. fmodule,
  94. symconst,symsym,symtable,
  95. tgobj,rgobj,
  96. procinfo,cpupi,
  97. paramgr;
  98. procedure tcgavr.init_register_allocators;
  99. begin
  100. inherited init_register_allocators;
  101. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  102. [RS_R8,RS_R9,
  103. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  104. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  105. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  106. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  107. [RS_R26,RS_R30],first_int_imreg,[]); }
  108. end;
  109. procedure tcgavr.done_register_allocators;
  110. begin
  111. rg[R_INTREGISTER].free;
  112. // rg[R_ADDRESSREGISTER].free;
  113. inherited done_register_allocators;
  114. end;
  115. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  116. var
  117. tmp1,tmp2,tmp3 : TRegister;
  118. begin
  119. case size of
  120. OS_8,OS_S8:
  121. Result:=inherited getintregister(list, size);
  122. OS_16,OS_S16:
  123. begin
  124. Result:=inherited getintregister(list, OS_8);
  125. { ensure that the high register can be retrieved by
  126. GetNextReg
  127. }
  128. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  129. internalerror(2011021331);
  130. end;
  131. OS_32,OS_S32:
  132. begin
  133. Result:=inherited getintregister(list, OS_8);
  134. tmp1:=inherited getintregister(list, OS_8);
  135. { ensure that the high register can be retrieved by
  136. GetNextReg
  137. }
  138. if tmp1<>GetNextReg(Result) then
  139. internalerror(2011021332);
  140. tmp2:=inherited getintregister(list, OS_8);
  141. { ensure that the upper register can be retrieved by
  142. GetNextReg
  143. }
  144. if tmp2<>GetNextReg(tmp1) then
  145. internalerror(2011021333);
  146. tmp3:=inherited getintregister(list, OS_8);
  147. { ensure that the upper register can be retrieved by
  148. GetNextReg
  149. }
  150. if tmp3<>GetNextReg(tmp2) then
  151. internalerror(2011021334);
  152. end;
  153. else
  154. internalerror(2011021330);
  155. end;
  156. end;
  157. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  158. begin
  159. Result:=getintregister(list,OS_ADDR);
  160. end;
  161. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  162. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  163. var
  164. ref : treference;
  165. begin
  166. paramanager.allocparaloc(list,paraloc);
  167. case paraloc^.loc of
  168. LOC_REGISTER,LOC_CREGISTER:
  169. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  170. LOC_REFERENCE,LOC_CREFERENCE:
  171. begin
  172. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  173. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  174. end;
  175. else
  176. internalerror(2002071004);
  177. end;
  178. end;
  179. var
  180. i, i2 : longint;
  181. hp : PCGParaLocation;
  182. begin
  183. { if use_push(cgpara) then
  184. begin
  185. if tcgsize2size[cgpara.Size] > 2 then
  186. begin
  187. if tcgsize2size[cgpara.Size] <> 4 then
  188. internalerror(2013031101);
  189. if cgpara.location^.Next = nil then
  190. begin
  191. if tcgsize2size[cgpara.location^.size] <> 4 then
  192. internalerror(2013031101);
  193. end
  194. else
  195. begin
  196. if tcgsize2size[cgpara.location^.size] <> 2 then
  197. internalerror(2013031101);
  198. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  199. internalerror(2013031101);
  200. if cgpara.location^.Next^.Next <> nil then
  201. internalerror(2013031101);
  202. end;
  203. if tcgsize2size[cgpara.size]>cgpara.alignment then
  204. pushsize:=cgpara.size
  205. else
  206. pushsize:=int_cgsize(cgpara.alignment);
  207. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  208. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  209. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  210. end
  211. else
  212. begin
  213. cgpara.check_simple_location;
  214. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  215. pushsize:=cgpara.location^.size
  216. else
  217. pushsize:=int_cgsize(cgpara.alignment);
  218. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  219. end;
  220. end
  221. else }
  222. begin
  223. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  224. internalerror(2014011101);
  225. hp:=cgpara.location;
  226. i:=0;
  227. while i<tcgsize2size[cgpara.Size] do
  228. begin
  229. if not(assigned(hp)) then
  230. internalerror(2014011102);
  231. inc(i, tcgsize2size[hp^.Size]);
  232. if hp^.Loc=LOC_REGISTER then
  233. begin
  234. load_para_loc(r,hp);
  235. hp:=hp^.Next;
  236. r:=GetNextReg(r);
  237. end
  238. else
  239. begin
  240. load_para_loc(r,hp);
  241. for i2:=1 to tcgsize2size[hp^.Size] do
  242. r:=GetNextReg(r);
  243. hp:=hp^.Next;
  244. end;
  245. end;
  246. if assigned(hp) then
  247. internalerror(2014011103);
  248. end;
  249. end;
  250. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  251. var
  252. i : longint;
  253. hp : PCGParaLocation;
  254. begin
  255. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  256. internalerror(2014011101);
  257. hp:=paraloc.location;
  258. for i:=1 to tcgsize2size[paraloc.Size] do
  259. begin
  260. if not(assigned(hp)) or
  261. (tcgsize2size[hp^.size]<>1) or
  262. (hp^.shiftval<>0) then
  263. internalerror(2014011105);
  264. case hp^.loc of
  265. LOC_REGISTER,LOC_CREGISTER:
  266. a_load_const_reg(list,hp^.size,(a shr (i-1)) and $ff,hp^.register);
  267. LOC_REFERENCE,LOC_CREFERENCE:
  268. begin
  269. list.concat(taicpu.op_const(A_PUSH,(a shr (i-1)) and $ff));
  270. end;
  271. else
  272. internalerror(2002071004);
  273. end;
  274. hp:=hp^.Next;
  275. end;
  276. if assigned(hp) then
  277. internalerror(2014011104);
  278. end;
  279. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  280. var
  281. tmpref, ref: treference;
  282. location: pcgparalocation;
  283. sizeleft: tcgint;
  284. begin
  285. location := paraloc.location;
  286. tmpref := r;
  287. sizeleft := paraloc.intsize;
  288. while assigned(location) do
  289. begin
  290. paramanager.allocparaloc(list,location);
  291. case location^.loc of
  292. LOC_REGISTER,LOC_CREGISTER:
  293. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  294. LOC_REFERENCE:
  295. begin
  296. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  297. { doubles in softemu mode have a strange order of registers and references }
  298. if location^.size=OS_32 then
  299. g_concatcopy(list,tmpref,ref,4)
  300. else
  301. begin
  302. g_concatcopy(list,tmpref,ref,sizeleft);
  303. if assigned(location^.next) then
  304. internalerror(2005010710);
  305. end;
  306. end;
  307. LOC_VOID:
  308. begin
  309. // nothing to do
  310. end;
  311. else
  312. internalerror(2002081103);
  313. end;
  314. inc(tmpref.offset,tcgsize2size[location^.size]);
  315. dec(sizeleft,tcgsize2size[location^.size]);
  316. location := location^.next;
  317. end;
  318. end;
  319. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  320. var
  321. tmpreg: tregister;
  322. begin
  323. tmpreg:=getaddressregister(list);
  324. a_loadaddr_ref_reg(list,r,tmpreg);
  325. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  326. end;
  327. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  328. begin
  329. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  330. {
  331. the compiler does not properly set this flag anymore in pass 1, and
  332. for now we only need it after pass 2 (I hope) (JM)
  333. if not(pi_do_call in current_procinfo.flags) then
  334. internalerror(2003060703);
  335. }
  336. include(current_procinfo.flags,pi_do_call);
  337. end;
  338. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  339. begin
  340. a_reg_alloc(list,NR_ZLO);
  341. a_reg_alloc(list,NR_ZHI);
  342. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  343. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  344. list.concat(taicpu.op_none(A_ICALL));
  345. a_reg_dealloc(list,NR_ZLO);
  346. a_reg_dealloc(list,NR_ZHI);
  347. include(current_procinfo.flags,pi_do_call);
  348. end;
  349. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  350. begin
  351. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  352. internalerror(2012102403);
  353. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  354. end;
  355. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  356. begin
  357. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  358. internalerror(2012102401);
  359. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  360. end;
  361. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  362. var
  363. countreg,
  364. tmpreg: tregister;
  365. i : integer;
  366. instr : taicpu;
  367. paraloc1,paraloc2,paraloc3 : TCGPara;
  368. l1,l2 : tasmlabel;
  369. pd : tprocdef;
  370. procedure NextSrcDst;
  371. begin
  372. if i=5 then
  373. begin
  374. dst:=dsthi;
  375. src:=srchi;
  376. end
  377. else
  378. begin
  379. dst:=GetNextReg(dst);
  380. src:=GetNextReg(src);
  381. end;
  382. end;
  383. { iterates TmpReg through all registers of dst }
  384. procedure NextTmp;
  385. begin
  386. if i=5 then
  387. tmpreg:=dsthi
  388. else
  389. tmpreg:=GetNextReg(tmpreg);
  390. end;
  391. begin
  392. case op of
  393. OP_ADD:
  394. begin
  395. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  396. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  397. begin
  398. for i:=2 to tcgsize2size[size] do
  399. begin
  400. NextSrcDst;
  401. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  402. end;
  403. end;
  404. end;
  405. OP_SUB:
  406. begin
  407. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  408. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  409. begin
  410. for i:=2 to tcgsize2size[size] do
  411. begin
  412. NextSrcDst;
  413. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  414. end;
  415. end;
  416. end;
  417. OP_NEG:
  418. begin
  419. if src<>dst then
  420. begin
  421. if size in [OS_S64,OS_64] then
  422. begin
  423. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  424. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  425. end
  426. else
  427. a_load_reg_reg(list,size,size,src,dst);
  428. end;
  429. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  430. begin
  431. tmpreg:=GetNextReg(dst);
  432. for i:=2 to tcgsize2size[size] do
  433. begin
  434. list.concat(taicpu.op_reg(A_COM,tmpreg));
  435. NextTmp;
  436. end;
  437. list.concat(taicpu.op_reg(A_NEG,dst));
  438. tmpreg:=GetNextReg(dst);
  439. for i:=2 to tcgsize2size[size] do
  440. begin
  441. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  442. NextTmp;
  443. end;
  444. end;
  445. end;
  446. OP_NOT:
  447. begin
  448. for i:=1 to tcgsize2size[size] do
  449. begin
  450. if src<>dst then
  451. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  452. list.concat(taicpu.op_reg(A_COM,dst));
  453. NextSrcDst;
  454. end;
  455. end;
  456. OP_MUL,OP_IMUL:
  457. begin
  458. if size in [OS_8,OS_S8] then
  459. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  460. else if size=OS_16 then
  461. begin
  462. pd:=search_system_proc('fpc_mul_word');
  463. paraloc1.init;
  464. paraloc2.init;
  465. paraloc3.init;
  466. paramanager.getintparaloc(pd,1,paraloc1);
  467. paramanager.getintparaloc(pd,2,paraloc2);
  468. paramanager.getintparaloc(pd,3,paraloc3);
  469. a_load_const_cgpara(list,OS_8,0,paraloc3);
  470. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  471. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  472. paramanager.freecgpara(list,paraloc3);
  473. paramanager.freecgpara(list,paraloc2);
  474. paramanager.freecgpara(list,paraloc1);
  475. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  476. a_call_name(list,'FPC_MUL_WORD',false);
  477. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  478. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  479. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  480. paraloc3.done;
  481. paraloc2.done;
  482. paraloc1.done;
  483. end
  484. else
  485. internalerror(2011022002);
  486. end;
  487. OP_DIV,OP_IDIV:
  488. { special stuff, needs separate handling inside code }
  489. { generator }
  490. internalerror(2011022001);
  491. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  492. begin
  493. current_asmdata.getjumplabel(l1);
  494. current_asmdata.getjumplabel(l2);
  495. countreg:=getintregister(list,OS_8);
  496. a_load_reg_reg(list,size,OS_8,src,countreg);
  497. list.concat(taicpu.op_reg_const(A_CPI,countreg,0));
  498. a_jmp_flags(list,F_EQ,l2);
  499. cg.a_label(list,l1);
  500. case op of
  501. OP_SHR:
  502. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  503. OP_SHL:
  504. list.concat(taicpu.op_reg(A_LSL,dst));
  505. OP_SAR:
  506. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  507. OP_ROR:
  508. begin
  509. { load carry? }
  510. if not(size in [OS_8,OS_S8]) then
  511. begin
  512. list.concat(taicpu.op_none(A_CLC));
  513. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  514. list.concat(taicpu.op_none(A_SEC));
  515. end;
  516. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  517. end;
  518. OP_ROL:
  519. begin
  520. { load carry? }
  521. if not(size in [OS_8,OS_S8]) then
  522. begin
  523. list.concat(taicpu.op_none(A_CLC));
  524. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  525. list.concat(taicpu.op_none(A_SEC));
  526. end;
  527. list.concat(taicpu.op_reg(A_ROL,dst))
  528. end;
  529. else
  530. internalerror(2011030901);
  531. end;
  532. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  533. begin
  534. for i:=2 to tcgsize2size[size] do
  535. begin
  536. case op of
  537. OP_ROR,
  538. OP_SHR:
  539. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  540. OP_ROL,
  541. OP_SHL:
  542. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  543. OP_SAR:
  544. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  545. else
  546. internalerror(2011030902);
  547. end;
  548. end;
  549. end;
  550. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  551. a_jmp_flags(list,F_NE,l1);
  552. // keep registers alive
  553. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  554. cg.a_label(list,l2);
  555. end;
  556. OP_AND,OP_OR,OP_XOR:
  557. begin
  558. for i:=1 to tcgsize2size[size] do
  559. begin
  560. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  561. NextSrcDst;
  562. end;
  563. end;
  564. else
  565. internalerror(2011022004);
  566. end;
  567. end;
  568. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  569. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  570. var
  571. mask : qword;
  572. shift : byte;
  573. i : byte;
  574. tmpreg : tregister;
  575. tmpreg64 : tregister64;
  576. procedure NextReg;
  577. begin
  578. if i=5 then
  579. reg:=reghi
  580. else
  581. reg:=GetNextReg(reg);
  582. end;
  583. begin
  584. mask:=$ff;
  585. shift:=0;
  586. case op of
  587. OP_OR:
  588. begin
  589. for i:=1 to tcgsize2size[size] do
  590. begin
  591. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  592. NextReg;
  593. mask:=mask shl 8;
  594. inc(shift,8);
  595. end;
  596. end;
  597. OP_AND:
  598. begin
  599. for i:=1 to tcgsize2size[size] do
  600. begin
  601. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  602. NextReg;
  603. mask:=mask shl 8;
  604. inc(shift,8);
  605. end;
  606. end;
  607. OP_SUB:
  608. begin
  609. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  610. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  611. begin
  612. for i:=2 to tcgsize2size[size] do
  613. begin
  614. NextReg;
  615. mask:=mask shl 8;
  616. inc(shift,8);
  617. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  618. end;
  619. end;
  620. end;
  621. {OP_ADD:
  622. begin
  623. list.concat(taicpu.op_reg_const(A_SUBI,reg,(-a) and mask));
  624. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  625. begin
  626. for i:=2 to tcgsize2size[size] do
  627. begin
  628. NextReg;
  629. mask:=mask shl 8;
  630. inc(shift,8);
  631. list.concat(taicpu.op_reg_const(A_ADC,reg,(a and mask) shr shift));
  632. end;
  633. end;
  634. end; }
  635. else
  636. begin
  637. if size in [OS_64,OS_S64] then
  638. begin
  639. tmpreg64.reglo:=getintregister(list,OS_32);
  640. tmpreg64.reghi:=getintregister(list,OS_32);
  641. cg64.a_load64_const_reg(list,a,tmpreg64);
  642. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  643. end
  644. else
  645. begin
  646. tmpreg:=getintregister(list,size);
  647. a_load_const_reg(list,size,a,tmpreg);
  648. a_op_reg_reg(list,op,size,tmpreg,reg);
  649. end;
  650. end;
  651. end;
  652. end;
  653. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  654. var
  655. mask : qword;
  656. shift : byte;
  657. i : byte;
  658. begin
  659. mask:=$ff;
  660. shift:=0;
  661. for i:=1 to tcgsize2size[size] do
  662. begin
  663. if ((qword(a) and mask) shr shift)=0 then
  664. emit_mov(list,reg,NR_R1)
  665. else
  666. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  667. mask:=mask shl 8;
  668. inc(shift,8);
  669. reg:=GetNextReg(reg);
  670. end;
  671. end;
  672. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  673. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  674. begin
  675. { allocate the register only, if a cpu register is passed }
  676. if getsupreg(reg)<first_int_imreg then
  677. getcpuregister(list,reg);
  678. end;
  679. var
  680. tmpref : treference;
  681. l : tasmlabel;
  682. begin
  683. Result:=ref;
  684. if ref.addressmode<>AM_UNCHANGED then
  685. internalerror(2011021701);
  686. { Be sure to have a base register }
  687. if (ref.base=NR_NO) then
  688. begin
  689. { only symbol+offset? }
  690. if ref.index=NR_NO then
  691. exit;
  692. ref.base:=ref.index;
  693. ref.index:=NR_NO;
  694. end;
  695. if assigned(ref.symbol) or (ref.offset<>0) then
  696. begin
  697. reference_reset(tmpref,0);
  698. tmpref.symbol:=ref.symbol;
  699. tmpref.offset:=ref.offset;
  700. tmpref.refaddr:=addr_lo8;
  701. maybegetcpuregister(list,tmpreg);
  702. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  703. tmpref.refaddr:=addr_hi8;
  704. maybegetcpuregister(list,GetNextReg(tmpreg));
  705. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  706. if (ref.base<>NR_NO) then
  707. begin
  708. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  709. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  710. end;
  711. if (ref.index<>NR_NO) then
  712. begin
  713. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  714. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  715. end;
  716. ref.symbol:=nil;
  717. ref.offset:=0;
  718. ref.base:=tmpreg;
  719. ref.index:=NR_NO;
  720. end
  721. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  722. begin
  723. maybegetcpuregister(list,tmpreg);
  724. emit_mov(list,tmpreg,ref.base);
  725. maybegetcpuregister(list,GetNextReg(tmpreg));
  726. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  727. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  728. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  729. ref.base:=tmpreg;
  730. ref.index:=NR_NO;
  731. end
  732. else if (ref.base<>NR_NO) then
  733. begin
  734. maybegetcpuregister(list,tmpreg);
  735. emit_mov(list,tmpreg,ref.base);
  736. maybegetcpuregister(list,GetNextReg(tmpreg));
  737. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  738. ref.base:=tmpreg;
  739. ref.index:=NR_NO;
  740. end
  741. else if (ref.index<>NR_NO) then
  742. begin
  743. maybegetcpuregister(list,tmpreg);
  744. emit_mov(list,tmpreg,ref.index);
  745. maybegetcpuregister(list,GetNextReg(tmpreg));
  746. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  747. ref.base:=tmpreg;
  748. ref.index:=NR_NO;
  749. end;
  750. Result:=ref;
  751. end;
  752. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  753. var
  754. href : treference;
  755. conv_done: boolean;
  756. tmpreg : tregister;
  757. i : integer;
  758. QuickRef : Boolean;
  759. begin
  760. QuickRef:=false;
  761. if not((Ref.addressmode=AM_UNCHANGED) and
  762. (Ref.symbol=nil) and
  763. ((Ref.base=NR_R28) or
  764. (Ref.base=NR_R29)) and
  765. (Ref.Index=NR_No) and
  766. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  767. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  768. href:=normalize_ref(list,Ref,NR_R30)
  769. else
  770. begin
  771. QuickRef:=true;
  772. href:=Ref;
  773. end;
  774. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  775. internalerror(2011021307);
  776. conv_done:=false;
  777. if tosize<>fromsize then
  778. begin
  779. conv_done:=true;
  780. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  781. fromsize:=tosize;
  782. case fromsize of
  783. OS_8:
  784. begin
  785. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  786. href.addressmode:=AM_POSTINCREMENT;
  787. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  788. for i:=2 to tcgsize2size[tosize] do
  789. begin
  790. if QuickRef then
  791. inc(href.offset);
  792. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  793. href.addressmode:=AM_POSTINCREMENT
  794. else
  795. href.addressmode:=AM_UNCHANGED;
  796. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  797. end;
  798. end;
  799. OS_S8:
  800. begin
  801. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  802. href.addressmode:=AM_POSTINCREMENT;
  803. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  804. if tcgsize2size[tosize]>1 then
  805. begin
  806. tmpreg:=getintregister(list,OS_8);
  807. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  808. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  809. list.concat(taicpu.op_reg(A_COM,tmpreg));
  810. for i:=2 to tcgsize2size[tosize] do
  811. begin
  812. if QuickRef then
  813. inc(href.offset);
  814. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  815. href.addressmode:=AM_POSTINCREMENT
  816. else
  817. href.addressmode:=AM_UNCHANGED;
  818. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  819. end;
  820. end;
  821. end;
  822. OS_16:
  823. begin
  824. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  825. href.addressmode:=AM_POSTINCREMENT;
  826. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  827. if QuickRef then
  828. inc(href.offset)
  829. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  830. href.addressmode:=AM_POSTINCREMENT
  831. else
  832. href.addressmode:=AM_UNCHANGED;
  833. reg:=GetNextReg(reg);
  834. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  835. for i:=3 to tcgsize2size[tosize] do
  836. begin
  837. if QuickRef then
  838. inc(href.offset);
  839. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  840. href.addressmode:=AM_POSTINCREMENT
  841. else
  842. href.addressmode:=AM_UNCHANGED;
  843. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  844. end;
  845. end;
  846. OS_S16:
  847. begin
  848. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  849. href.addressmode:=AM_POSTINCREMENT;
  850. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  851. if QuickRef then
  852. inc(href.offset)
  853. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  854. href.addressmode:=AM_POSTINCREMENT
  855. else
  856. href.addressmode:=AM_UNCHANGED;
  857. reg:=GetNextReg(reg);
  858. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  859. if tcgsize2size[tosize]>2 then
  860. begin
  861. tmpreg:=getintregister(list,OS_8);
  862. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  863. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  864. list.concat(taicpu.op_reg(A_COM,tmpreg));
  865. for i:=3 to tcgsize2size[tosize] do
  866. begin
  867. if QuickRef then
  868. inc(href.offset);
  869. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  870. href.addressmode:=AM_POSTINCREMENT
  871. else
  872. href.addressmode:=AM_UNCHANGED;
  873. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  874. end;
  875. end;
  876. end;
  877. else
  878. conv_done:=false;
  879. end;
  880. end;
  881. if not conv_done then
  882. begin
  883. for i:=1 to tcgsize2size[fromsize] do
  884. begin
  885. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  886. href.addressmode:=AM_POSTINCREMENT
  887. else
  888. href.addressmode:=AM_UNCHANGED;
  889. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  890. if QuickRef then
  891. inc(href.offset);
  892. reg:=GetNextReg(reg);
  893. end;
  894. end;
  895. if not(QuickRef) then
  896. begin
  897. ungetcpuregister(list,href.base);
  898. ungetcpuregister(list,GetNextReg(href.base));
  899. end;
  900. end;
  901. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  902. const Ref : treference;reg : tregister);
  903. var
  904. href : treference;
  905. conv_done: boolean;
  906. tmpreg : tregister;
  907. i : integer;
  908. QuickRef : boolean;
  909. begin
  910. QuickRef:=false;
  911. if not((Ref.addressmode=AM_UNCHANGED) and
  912. (Ref.symbol=nil) and
  913. ((Ref.base=NR_R28) or
  914. (Ref.base=NR_R29)) and
  915. (Ref.Index=NR_No) and
  916. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  917. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  918. href:=normalize_ref(list,Ref,NR_R30)
  919. else
  920. begin
  921. QuickRef:=true;
  922. href:=Ref;
  923. end;
  924. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  925. internalerror(2011021307);
  926. conv_done:=false;
  927. if tosize<>fromsize then
  928. begin
  929. conv_done:=true;
  930. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  931. fromsize:=tosize;
  932. case fromsize of
  933. OS_8:
  934. begin
  935. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  936. for i:=2 to tcgsize2size[tosize] do
  937. begin
  938. reg:=GetNextReg(reg);
  939. list.concat(taicpu.op_reg(A_CLR,reg));
  940. end;
  941. end;
  942. OS_S8:
  943. begin
  944. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  945. tmpreg:=reg;
  946. if tcgsize2size[tosize]>1 then
  947. begin
  948. reg:=GetNextReg(reg);
  949. list.concat(taicpu.op_reg(A_CLR,reg));
  950. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  951. list.concat(taicpu.op_reg(A_COM,reg));
  952. tmpreg:=reg;
  953. for i:=3 to tcgsize2size[tosize] do
  954. begin
  955. reg:=GetNextReg(reg);
  956. emit_mov(list,reg,tmpreg);
  957. end;
  958. end;
  959. end;
  960. OS_16:
  961. begin
  962. if not(QuickRef) then
  963. href.addressmode:=AM_POSTINCREMENT;
  964. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  965. if QuickRef then
  966. inc(href.offset);
  967. href.addressmode:=AM_UNCHANGED;
  968. reg:=GetNextReg(reg);
  969. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  970. for i:=3 to tcgsize2size[tosize] do
  971. begin
  972. reg:=GetNextReg(reg);
  973. list.concat(taicpu.op_reg(A_CLR,reg));
  974. end;
  975. end;
  976. OS_S16:
  977. begin
  978. if not(QuickRef) then
  979. href.addressmode:=AM_POSTINCREMENT;
  980. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  981. if QuickRef then
  982. inc(href.offset);
  983. href.addressmode:=AM_UNCHANGED;
  984. reg:=GetNextReg(reg);
  985. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  986. tmpreg:=reg;
  987. reg:=GetNextReg(reg);
  988. list.concat(taicpu.op_reg(A_CLR,reg));
  989. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  990. list.concat(taicpu.op_reg(A_COM,reg));
  991. tmpreg:=reg;
  992. for i:=4 to tcgsize2size[tosize] do
  993. begin
  994. reg:=GetNextReg(reg);
  995. emit_mov(list,reg,tmpreg);
  996. end;
  997. end;
  998. else
  999. conv_done:=false;
  1000. end;
  1001. end;
  1002. if not conv_done then
  1003. begin
  1004. for i:=1 to tcgsize2size[fromsize] do
  1005. begin
  1006. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1007. href.addressmode:=AM_POSTINCREMENT
  1008. else
  1009. href.addressmode:=AM_UNCHANGED;
  1010. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1011. if QuickRef then
  1012. inc(href.offset);
  1013. reg:=GetNextReg(reg);
  1014. end;
  1015. end;
  1016. if not(QuickRef) then
  1017. begin
  1018. ungetcpuregister(list,href.base);
  1019. ungetcpuregister(list,GetNextReg(href.base));
  1020. end;
  1021. end;
  1022. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1023. var
  1024. conv_done: boolean;
  1025. tmpreg : tregister;
  1026. i : integer;
  1027. begin
  1028. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1029. internalerror(2011021310);
  1030. conv_done:=false;
  1031. if tosize<>fromsize then
  1032. begin
  1033. conv_done:=true;
  1034. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1035. fromsize:=tosize;
  1036. case fromsize of
  1037. OS_8:
  1038. begin
  1039. emit_mov(list,reg2,reg1);
  1040. for i:=2 to tcgsize2size[tosize] do
  1041. begin
  1042. reg2:=GetNextReg(reg2);
  1043. list.concat(taicpu.op_reg(A_CLR,reg2));
  1044. end;
  1045. end;
  1046. OS_S8:
  1047. begin
  1048. emit_mov(list,reg2,reg1);
  1049. if tcgsize2size[tosize]>1 then
  1050. begin
  1051. reg2:=GetNextReg(reg2);
  1052. list.concat(taicpu.op_reg(A_CLR,reg2));
  1053. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1054. list.concat(taicpu.op_reg(A_COM,reg2));
  1055. tmpreg:=reg2;
  1056. for i:=3 to tcgsize2size[tosize] do
  1057. begin
  1058. reg2:=GetNextReg(reg2);
  1059. emit_mov(list,reg2,tmpreg);
  1060. end;
  1061. end;
  1062. end;
  1063. OS_16:
  1064. begin
  1065. emit_mov(list,reg2,reg1);
  1066. reg1:=GetNextReg(reg1);
  1067. reg2:=GetNextReg(reg2);
  1068. emit_mov(list,reg2,reg1);
  1069. for i:=3 to tcgsize2size[tosize] do
  1070. begin
  1071. reg2:=GetNextReg(reg2);
  1072. list.concat(taicpu.op_reg(A_CLR,reg2));
  1073. end;
  1074. end;
  1075. OS_S16:
  1076. begin
  1077. emit_mov(list,reg2,reg1);
  1078. reg1:=GetNextReg(reg1);
  1079. reg2:=GetNextReg(reg2);
  1080. emit_mov(list,reg2,reg1);
  1081. if tcgsize2size[tosize]>2 then
  1082. begin
  1083. reg2:=GetNextReg(reg2);
  1084. list.concat(taicpu.op_reg(A_CLR,reg2));
  1085. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1086. list.concat(taicpu.op_reg(A_COM,reg2));
  1087. tmpreg:=reg2;
  1088. for i:=4 to tcgsize2size[tosize] do
  1089. begin
  1090. reg2:=GetNextReg(reg2);
  1091. emit_mov(list,reg2,tmpreg);
  1092. end;
  1093. end;
  1094. end;
  1095. else
  1096. conv_done:=false;
  1097. end;
  1098. end;
  1099. if not conv_done and (reg1<>reg2) then
  1100. begin
  1101. for i:=1 to tcgsize2size[fromsize] do
  1102. begin
  1103. emit_mov(list,reg2,reg1);
  1104. reg1:=GetNextReg(reg1);
  1105. reg2:=GetNextReg(reg2);
  1106. end;
  1107. end;
  1108. end;
  1109. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1110. begin
  1111. internalerror(2012010702);
  1112. end;
  1113. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1114. begin
  1115. internalerror(2012010703);
  1116. end;
  1117. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1118. begin
  1119. internalerror(2012010704);
  1120. end;
  1121. { comparison operations }
  1122. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1123. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1124. var
  1125. swapped : boolean;
  1126. tmpreg : tregister;
  1127. i : byte;
  1128. begin
  1129. if a=0 then
  1130. begin
  1131. swapped:=false;
  1132. { swap parameters? }
  1133. case cmp_op of
  1134. OC_GT:
  1135. begin
  1136. swapped:=true;
  1137. cmp_op:=OC_LT;
  1138. end;
  1139. OC_LTE:
  1140. begin
  1141. swapped:=true;
  1142. cmp_op:=OC_GTE;
  1143. end;
  1144. OC_BE:
  1145. begin
  1146. swapped:=true;
  1147. cmp_op:=OC_AE;
  1148. end;
  1149. OC_A:
  1150. begin
  1151. swapped:=true;
  1152. cmp_op:=OC_B;
  1153. end;
  1154. end;
  1155. if swapped then
  1156. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1157. else
  1158. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1159. for i:=2 to tcgsize2size[size] do
  1160. begin
  1161. reg:=GetNextReg(reg);
  1162. if swapped then
  1163. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1164. else
  1165. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1166. end;
  1167. a_jmp_cond(list,cmp_op,l);
  1168. end
  1169. else
  1170. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1171. end;
  1172. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1173. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1174. var
  1175. swapped : boolean;
  1176. tmpreg : tregister;
  1177. i : byte;
  1178. begin
  1179. swapped:=false;
  1180. { swap parameters? }
  1181. case cmp_op of
  1182. OC_GT:
  1183. begin
  1184. swapped:=true;
  1185. cmp_op:=OC_LT;
  1186. end;
  1187. OC_LTE:
  1188. begin
  1189. swapped:=true;
  1190. cmp_op:=OC_GTE;
  1191. end;
  1192. OC_BE:
  1193. begin
  1194. swapped:=true;
  1195. cmp_op:=OC_AE;
  1196. end;
  1197. OC_A:
  1198. begin
  1199. swapped:=true;
  1200. cmp_op:=OC_B;
  1201. end;
  1202. end;
  1203. if swapped then
  1204. begin
  1205. tmpreg:=reg1;
  1206. reg1:=reg2;
  1207. reg2:=tmpreg;
  1208. end;
  1209. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1210. for i:=2 to tcgsize2size[size] do
  1211. begin
  1212. reg1:=GetNextReg(reg1);
  1213. reg2:=GetNextReg(reg2);
  1214. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1215. end;
  1216. a_jmp_cond(list,cmp_op,l);
  1217. end;
  1218. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1219. var
  1220. ai : taicpu;
  1221. begin
  1222. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  1223. ai.is_jmp:=true;
  1224. list.concat(ai);
  1225. end;
  1226. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1227. var
  1228. ai : taicpu;
  1229. begin
  1230. ai:=taicpu.op_sym(A_JMP,l);
  1231. ai.is_jmp:=true;
  1232. list.concat(ai);
  1233. end;
  1234. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1235. var
  1236. ai : taicpu;
  1237. begin
  1238. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1239. ai.is_jmp:=true;
  1240. list.concat(ai);
  1241. end;
  1242. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1243. var
  1244. l : TAsmLabel;
  1245. tmpflags : TResFlags;
  1246. begin
  1247. current_asmdata.getjumplabel(l);
  1248. {
  1249. if flags_to_cond(f) then
  1250. begin
  1251. tmpflags:=f;
  1252. inverse_flags(tmpflags);
  1253. list.concat(taicpu.op_reg(A_CLR,reg));
  1254. a_jmp_flags(list,tmpflags,l);
  1255. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1256. end
  1257. else
  1258. }
  1259. begin
  1260. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1261. a_jmp_flags(list,f,l);
  1262. list.concat(taicpu.op_reg(A_CLR,reg));
  1263. end;
  1264. cg.a_label(list,l);
  1265. end;
  1266. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1267. var
  1268. i : integer;
  1269. begin
  1270. case value of
  1271. 0:
  1272. ;
  1273. {-14..-1:
  1274. begin
  1275. if ((-value) mod 2)<>0 then
  1276. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1277. for i:=1 to (-value) div 2 do
  1278. list.concat(taicpu.op_const(A_RCALL,0));
  1279. end;
  1280. 1..7:
  1281. begin
  1282. for i:=1 to value do
  1283. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1284. end;}
  1285. else
  1286. begin
  1287. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1288. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1289. // get SREG
  1290. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1291. // block interrupts
  1292. list.concat(taicpu.op_none(A_CLI));
  1293. // write high SP
  1294. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1295. // release interrupts
  1296. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1297. // write low SP
  1298. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1299. end;
  1300. end;
  1301. end;
  1302. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1303. begin
  1304. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1305. result:=A_LDS
  1306. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1307. result:=A_LDD
  1308. else
  1309. result:=A_LD;
  1310. end;
  1311. function tcgavr.GetStore(const ref: treference) : tasmop;
  1312. begin
  1313. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1314. result:=A_STS
  1315. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1316. result:=A_STD
  1317. else
  1318. result:=A_ST;
  1319. end;
  1320. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1321. var
  1322. regs : tcpuregisterset;
  1323. reg : tsuperregister;
  1324. begin
  1325. if not(nostackframe) then
  1326. begin
  1327. { save int registers }
  1328. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1329. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1330. regs:=regs+[RS_R28,RS_R29];
  1331. for reg:=RS_R31 downto RS_R0 do
  1332. if reg in regs then
  1333. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1334. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1335. begin
  1336. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1337. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1338. end
  1339. else
  1340. { the framepointer cannot be omitted on avr because sp
  1341. is not a register but part of the i/o map
  1342. }
  1343. internalerror(2011021901);
  1344. a_adjust_sp(list,-localsize);
  1345. end;
  1346. end;
  1347. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1348. var
  1349. regs : tcpuregisterset;
  1350. reg : TSuperRegister;
  1351. LocalSize : longint;
  1352. begin
  1353. if not(nostackframe) then
  1354. begin
  1355. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1356. begin
  1357. LocalSize:=current_procinfo.calc_stackframe_size;
  1358. a_adjust_sp(list,LocalSize);
  1359. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1360. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1361. regs:=regs+[RS_R28,RS_R29];
  1362. for reg:=RS_R0 to RS_R31 do
  1363. if reg in regs then
  1364. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1365. end
  1366. else
  1367. { the framepointer cannot be omitted on avr because sp
  1368. is not a register but part of the i/o map
  1369. }
  1370. internalerror(2011021902);
  1371. end;
  1372. list.concat(taicpu.op_none(A_RET));
  1373. end;
  1374. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1375. var
  1376. tmpref : treference;
  1377. begin
  1378. if ref.addressmode<>AM_UNCHANGED then
  1379. internalerror(2011021701);
  1380. if assigned(ref.symbol) or (ref.offset<>0) then
  1381. begin
  1382. reference_reset(tmpref,0);
  1383. tmpref.symbol:=ref.symbol;
  1384. tmpref.offset:=ref.offset;
  1385. tmpref.refaddr:=addr_lo8;
  1386. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1387. tmpref.refaddr:=addr_hi8;
  1388. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1389. if (ref.base<>NR_NO) then
  1390. begin
  1391. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1392. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1393. end;
  1394. if (ref.index<>NR_NO) then
  1395. begin
  1396. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1397. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1398. end;
  1399. end
  1400. else if (ref.base<>NR_NO)then
  1401. begin
  1402. emit_mov(list,r,ref.base);
  1403. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1404. if (ref.index<>NR_NO) then
  1405. begin
  1406. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1407. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1408. end;
  1409. end
  1410. else if (ref.index<>NR_NO) then
  1411. begin
  1412. emit_mov(list,r,ref.index);
  1413. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1414. end;
  1415. end;
  1416. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1417. begin
  1418. internalerror(2011021320);
  1419. end;
  1420. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1421. var
  1422. paraloc1,paraloc2,paraloc3 : TCGPara;
  1423. pd : tprocdef;
  1424. begin
  1425. pd:=search_system_proc('MOVE');
  1426. paraloc1.init;
  1427. paraloc2.init;
  1428. paraloc3.init;
  1429. paramanager.getintparaloc(pd,1,paraloc1);
  1430. paramanager.getintparaloc(pd,2,paraloc2);
  1431. paramanager.getintparaloc(pd,3,paraloc3);
  1432. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1433. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1434. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1435. paramanager.freecgpara(list,paraloc3);
  1436. paramanager.freecgpara(list,paraloc2);
  1437. paramanager.freecgpara(list,paraloc1);
  1438. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1439. a_call_name_static(list,'FPC_MOVE');
  1440. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1441. paraloc3.done;
  1442. paraloc2.done;
  1443. paraloc1.done;
  1444. end;
  1445. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1446. var
  1447. countreg,tmpreg : tregister;
  1448. srcref,dstref : treference;
  1449. copysize,countregsize : tcgsize;
  1450. l : TAsmLabel;
  1451. i : longint;
  1452. SrcQuickRef, DestQuickRef : Boolean;
  1453. begin
  1454. if len>16 then
  1455. begin
  1456. current_asmdata.getjumplabel(l);
  1457. reference_reset(srcref,0);
  1458. reference_reset(dstref,0);
  1459. srcref.base:=NR_R30;
  1460. srcref.addressmode:=AM_POSTINCREMENT;
  1461. dstref.base:=NR_R26;
  1462. dstref.addressmode:=AM_POSTINCREMENT;
  1463. copysize:=OS_8;
  1464. if len<256 then
  1465. countregsize:=OS_8
  1466. else if len<65536 then
  1467. countregsize:=OS_16
  1468. else
  1469. internalerror(2011022007);
  1470. countreg:=getintregister(list,countregsize);
  1471. a_load_const_reg(list,countregsize,len,countreg);
  1472. a_loadaddr_ref_reg(list,source,NR_R30);
  1473. tmpreg:=getaddressregister(list);
  1474. a_loadaddr_ref_reg(list,dest,tmpreg);
  1475. { X is used for spilling code so we can load it
  1476. only by a push/pop sequence, this can be
  1477. optimized later on by the peephole optimizer
  1478. }
  1479. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1480. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1481. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1482. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1483. cg.a_label(list,l);
  1484. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1485. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1486. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1487. a_jmp_flags(list,F_NE,l);
  1488. // keep registers alive
  1489. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1490. end
  1491. else
  1492. begin
  1493. SrcQuickRef:=false;
  1494. DestQuickRef:=false;
  1495. if not((source.addressmode=AM_UNCHANGED) and
  1496. (source.symbol=nil) and
  1497. ((source.base=NR_R28) or
  1498. (source.base=NR_R29)) and
  1499. (source.Index=NR_NO) and
  1500. (source.Offset in [0..64-len])) and
  1501. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1502. srcref:=normalize_ref(list,source,NR_R30)
  1503. else
  1504. begin
  1505. SrcQuickRef:=true;
  1506. srcref:=source;
  1507. end;
  1508. if not((dest.addressmode=AM_UNCHANGED) and
  1509. (dest.symbol=nil) and
  1510. ((dest.base=NR_R28) or
  1511. (dest.base=NR_R29)) and
  1512. (dest.Index=NR_No) and
  1513. (dest.Offset in [0..64-len])) and
  1514. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1515. begin
  1516. if not(SrcQuickRef) then
  1517. begin
  1518. tmpreg:=getaddressregister(list);
  1519. dstref:=normalize_ref(list,dest,tmpreg);
  1520. { X is used for spilling code so we can load it
  1521. only by a push/pop sequence, this can be
  1522. optimized later on by the peephole optimizer
  1523. }
  1524. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1525. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1526. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1527. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1528. dstref.base:=NR_R26;
  1529. end
  1530. else
  1531. dstref:=normalize_ref(list,dest,NR_R30);
  1532. end
  1533. else
  1534. begin
  1535. DestQuickRef:=true;
  1536. dstref:=dest;
  1537. end;
  1538. for i:=1 to len do
  1539. begin
  1540. if not(SrcQuickRef) and (i<len) then
  1541. srcref.addressmode:=AM_POSTINCREMENT
  1542. else
  1543. srcref.addressmode:=AM_UNCHANGED;
  1544. if not(DestQuickRef) and (i<len) then
  1545. dstref.addressmode:=AM_POSTINCREMENT
  1546. else
  1547. dstref.addressmode:=AM_UNCHANGED;
  1548. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1549. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1550. if SrcQuickRef then
  1551. inc(srcref.offset);
  1552. if DestQuickRef then
  1553. inc(dstref.offset);
  1554. end;
  1555. if not(SrcQuickRef) then
  1556. begin
  1557. ungetcpuregister(list,srcref.base);
  1558. ungetcpuregister(list,GetNextReg(srcref.base));
  1559. end;
  1560. end;
  1561. end;
  1562. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1563. var
  1564. hl : tasmlabel;
  1565. ai : taicpu;
  1566. cond : TAsmCond;
  1567. begin
  1568. if not(cs_check_overflow in current_settings.localswitches) then
  1569. exit;
  1570. current_asmdata.getjumplabel(hl);
  1571. if not ((def.typ=pointerdef) or
  1572. ((def.typ=orddef) and
  1573. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1574. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1575. cond:=C_VC
  1576. else
  1577. cond:=C_CC;
  1578. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1579. ai.SetCondition(cond);
  1580. ai.is_jmp:=true;
  1581. list.concat(ai);
  1582. a_call_name(list,'FPC_OVERFLOW',false);
  1583. a_label(list,hl);
  1584. end;
  1585. procedure tcgavr.g_save_registers(list: TAsmList);
  1586. begin
  1587. { this is done by the entry code }
  1588. end;
  1589. procedure tcgavr.g_restore_registers(list: TAsmList);
  1590. begin
  1591. { this is done by the exit code }
  1592. end;
  1593. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1594. var
  1595. ai1,ai2 : taicpu;
  1596. hl : TAsmLabel;
  1597. begin
  1598. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1599. ai1.is_jmp:=true;
  1600. hl:=nil;
  1601. case cond of
  1602. OC_EQ:
  1603. ai1.SetCondition(C_EQ);
  1604. OC_GT:
  1605. begin
  1606. { emulate GT }
  1607. current_asmdata.getjumplabel(hl);
  1608. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1609. ai2.SetCondition(C_EQ);
  1610. ai2.is_jmp:=true;
  1611. list.concat(ai2);
  1612. ai1.SetCondition(C_GE);
  1613. end;
  1614. OC_LT:
  1615. ai1.SetCondition(C_LT);
  1616. OC_GTE:
  1617. ai1.SetCondition(C_GE);
  1618. OC_LTE:
  1619. begin
  1620. { emulate LTE }
  1621. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1622. ai2.SetCondition(C_EQ);
  1623. ai2.is_jmp:=true;
  1624. list.concat(ai2);
  1625. ai1.SetCondition(C_LT);
  1626. end;
  1627. OC_NE:
  1628. ai1.SetCondition(C_NE);
  1629. OC_BE:
  1630. begin
  1631. { emulate BE }
  1632. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1633. ai2.SetCondition(C_EQ);
  1634. ai2.is_jmp:=true;
  1635. list.concat(ai2);
  1636. ai1.SetCondition(C_LO);
  1637. end;
  1638. OC_B:
  1639. ai1.SetCondition(C_LO);
  1640. OC_AE:
  1641. ai1.SetCondition(C_SH);
  1642. OC_A:
  1643. begin
  1644. { emulate A (unsigned GT) }
  1645. current_asmdata.getjumplabel(hl);
  1646. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1647. ai2.SetCondition(C_EQ);
  1648. ai2.is_jmp:=true;
  1649. list.concat(ai2);
  1650. ai1.SetCondition(C_SH);
  1651. end;
  1652. else
  1653. internalerror(2011082501);
  1654. end;
  1655. list.concat(ai1);
  1656. if assigned(hl) then
  1657. a_label(list,hl);
  1658. end;
  1659. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1660. var
  1661. instr: taicpu;
  1662. begin
  1663. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1664. list.Concat(instr);
  1665. { Notify the register allocator that we have written a move instruction so
  1666. it can try to eliminate it. }
  1667. add_move_instruction(instr);
  1668. end;
  1669. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1670. begin
  1671. if not(size in [OS_S64,OS_64]) then
  1672. internalerror(2012102402);
  1673. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1674. end;
  1675. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1676. begin
  1677. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1678. end;
  1679. procedure create_codegen;
  1680. begin
  1681. cg:=tcgavr.create;
  1682. cg64:=tcg64favr.create;
  1683. end;
  1684. end.