aoptcpu.pas 47 KB

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  1. {
  2. Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
  3. Development Team
  4. This unit implements the ARM optimizer object
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. { $define DEBUG_AOPTCPU}
  21. Interface
  22. uses cpubase,cgbase,aasmtai,aopt,AoptObj,aoptcpub;
  23. Type
  24. TCpuAsmOptimizer = class(TAsmOptimizer)
  25. { outputs a debug message into the assembler file }
  26. procedure DebugMsg(const s: string; p: tai);
  27. Function GetNextInstructionUsingReg(Current: tai; Var Next: tai;reg : TRegister): Boolean;
  28. function RegInInstruction(Reg: TRegister; p1: tai): Boolean; override;
  29. function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
  30. function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
  31. function InvertSkipInstruction(var p: tai): boolean;
  32. { uses the same constructor as TAopObj }
  33. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  34. procedure PeepHoleOptPass2;override;
  35. End;
  36. Implementation
  37. uses
  38. cutils,
  39. verbose,
  40. cpuinfo,
  41. aasmbase,aasmcpu,aasmdata,
  42. aoptutils,
  43. globals,globtype,
  44. cgutils;
  45. type
  46. TAsmOpSet = set of TAsmOp;
  47. function CanBeCond(p : tai) : boolean;
  48. begin
  49. result:=(p.typ=ait_instruction) and (taicpu(p).condition=C_None);
  50. end;
  51. function RefsEqual(const r1, r2: treference): boolean;
  52. begin
  53. refsequal :=
  54. (r1.offset = r2.offset) and
  55. (r1.base = r2.base) and
  56. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  57. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  58. (r1.relsymbol = r2.relsymbol) and
  59. (r1.addressmode = r2.addressmode);
  60. end;
  61. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
  62. begin
  63. result:=oper1.typ=oper2.typ;
  64. if result then
  65. case oper1.typ of
  66. top_const:
  67. Result:=oper1.val = oper2.val;
  68. top_reg:
  69. Result:=oper1.reg = oper2.reg;
  70. top_ref:
  71. Result:=RefsEqual(oper1.ref^, oper2.ref^);
  72. else Result:=false;
  73. end
  74. end;
  75. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  76. begin
  77. result := (oper.typ = top_reg) and (oper.reg = reg);
  78. end;
  79. function MatchInstruction(const instr: tai; const op: TAsmOp): boolean;
  80. begin
  81. result :=
  82. (instr.typ = ait_instruction) and
  83. (taicpu(instr).opcode = op);
  84. end;
  85. function MatchInstruction(const instr: tai; const ops: TAsmOpSet): boolean;
  86. begin
  87. result :=
  88. (instr.typ = ait_instruction) and
  89. (taicpu(instr).opcode in ops);
  90. end;
  91. function MatchInstruction(const instr: tai; const ops: TAsmOpSet;opcount : byte): boolean;
  92. begin
  93. result :=
  94. (instr.typ = ait_instruction) and
  95. (taicpu(instr).opcode in ops) and
  96. (taicpu(instr).ops=opcount);
  97. end;
  98. {$ifdef DEBUG_AOPTCPU}
  99. procedure TCpuAsmOptimizer.DebugMsg(const s: string;p : tai);
  100. begin
  101. asml.insertbefore(tai_comment.Create(strpnew(s)), p);
  102. end;
  103. {$else DEBUG_AOPTCPU}
  104. procedure TCpuAsmOptimizer.DebugMsg(const s: string;p : tai);inline;
  105. begin
  106. end;
  107. {$endif DEBUG_AOPTCPU}
  108. function TCpuAsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
  109. begin
  110. If (p1.typ = ait_instruction) and (taicpu(p1).opcode in [A_MUL,A_MULS,A_FMUL,A_FMULS,A_FMULSU]) and
  111. ((getsupreg(reg)=RS_R0) or (getsupreg(reg)=RS_R1)) then
  112. Result:=true
  113. else if (p1.typ = ait_instruction) and (taicpu(p1).opcode=A_MOVW) and
  114. ((TRegister(ord(taicpu(p1).oper[0]^.reg)+1)=reg) or (TRegister(ord(taicpu(p1).oper[1]^.reg)+1)=reg) or
  115. (taicpu(p1).oper[0]^.reg=reg) or (taicpu(p1).oper[1]^.reg=reg)) then
  116. Result:=true
  117. else
  118. Result:=inherited RegInInstruction(Reg, p1);
  119. end;
  120. function TCpuAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
  121. var Next: tai; reg: TRegister): Boolean;
  122. begin
  123. Next:=Current;
  124. repeat
  125. Result:=GetNextInstruction(Next,Next);
  126. until not(cs_opt_level3 in current_settings.optimizerswitches) or not(Result) or (Next.typ<>ait_instruction) or (RegInInstruction(reg,Next)) or
  127. (is_calljmp(taicpu(Next).opcode));
  128. end;
  129. function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  130. var
  131. p: taicpu;
  132. begin
  133. if not assigned(hp) or
  134. (hp.typ <> ait_instruction) then
  135. begin
  136. Result := false;
  137. exit;
  138. end;
  139. p := taicpu(hp);
  140. Result := ((p.opcode in [A_LDI,A_MOV,A_LDS]) and (reg=p.oper[0]^.reg) and ((p.oper[1]^.typ<>top_reg) or (reg<>p.oper[1]^.reg))) or
  141. ((p.opcode in [A_LD,A_LDD,A_LPM]) and (reg=p.oper[0]^.reg) and not(RegInRef(reg,p.oper[1]^.ref^))) or
  142. ((p.opcode in [A_MOVW]) and ((reg=p.oper[0]^.reg) or (TRegister(ord(reg)+1)=p.oper[0]^.reg)) and not(reg=p.oper[1]^.reg) and not(TRegister(ord(reg)+1)=p.oper[1]^.reg)) or
  143. ((p.opcode in [A_POP]) and (reg=p.oper[0]^.reg));
  144. end;
  145. function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
  146. var
  147. p: taicpu;
  148. i: longint;
  149. begin
  150. Result := false;
  151. if not (assigned(hp) and (hp.typ = ait_instruction)) then
  152. exit;
  153. p:=taicpu(hp);
  154. i:=0;
  155. { we do not care about the stack pointer }
  156. if p.opcode in [A_POP] then
  157. exit;
  158. { first operand only written?
  159. then skip it }
  160. if p.opcode in [A_MOV,A_LD,A_LDD,A_LDS,A_LPM,A_LDI,A_MOVW] then
  161. i:=1;
  162. while i<p.ops do
  163. begin
  164. case p.oper[i]^.typ of
  165. top_reg:
  166. Result := (p.oper[i]^.reg = reg) or
  167. { MOVW }
  168. ((i=1) and (p.opcode=A_MOVW) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg)));
  169. top_ref:
  170. Result :=
  171. (p.oper[i]^.ref^.base = reg) or
  172. (p.oper[i]^.ref^.index = reg);
  173. end;
  174. { Bailout if we found something }
  175. if Result then
  176. exit;
  177. Inc(i);
  178. end;
  179. end;
  180. {
  181. Turns
  182. sbis ?
  183. jmp .Lx
  184. op
  185. .Lx:
  186. Into
  187. sbic ?
  188. op
  189. For all types of skip instructions
  190. }
  191. function TCpuAsmOptimizer.InvertSkipInstruction(var p: tai): boolean;
  192. function GetNextInstructionWithoutLabel(p: tai; var next: tai): boolean;
  193. begin
  194. repeat
  195. result:=GetNextInstruction(p,next);
  196. p:=next;
  197. until
  198. (not result) or
  199. (not assigned(next)) or
  200. (next.typ in [ait_instruction]);
  201. result:=assigned(next) and (next.typ in [ait_instruction]);
  202. end;
  203. var
  204. hp1, hp2, hp3: tai;
  205. s: string;
  206. begin
  207. result:=false;
  208. if GetNextInstruction(taicpu(p),hp1) and
  209. (hp1.typ=ait_instruction) and
  210. (taicpu(hp1).opcode in [A_RJMP,A_JMP]) and
  211. (taicpu(hp1).ops=1) and
  212. (taicpu(hp1).oper[0]^.typ=top_ref) and
  213. (taicpu(hp1).oper[0]^.ref^.offset=0) and
  214. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  215. GetNextInstructionWithoutLabel(hp1,hp2) and
  216. (hp2.typ=ait_instruction) and
  217. (not taicpu(hp2).is_jmp) and
  218. GetNextInstruction(hp2,hp3) and
  219. FindLabel(TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol),hp3) then
  220. begin
  221. DebugMsg('SkipJump2InvertedSkip', p);
  222. case taicpu(p).opcode of
  223. A_SBIS: taicpu(p).opcode:=A_SBIC;
  224. A_SBIC: taicpu(p).opcode:=A_SBIS;
  225. A_SBRS: taicpu(p).opcode:=A_SBRC;
  226. A_SBRC: taicpu(p).opcode:=A_SBRS;
  227. end;
  228. TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol).decrefs;
  229. asml.remove(hp1);
  230. hp1.free;
  231. end;
  232. end;
  233. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  234. var
  235. hp1,hp2,hp3,hp4,hp5: tai;
  236. alloc, dealloc: tai_regalloc;
  237. i: integer;
  238. l: TAsmLabel;
  239. TmpUsedRegs : TAllUsedRegs;
  240. begin
  241. result := false;
  242. case p.typ of
  243. ait_instruction:
  244. begin
  245. {
  246. change
  247. <op> reg,x,y
  248. cp reg,r1
  249. into
  250. <op>s reg,x,y
  251. }
  252. { this optimization can applied only to the currently enabled operations because
  253. the other operations do not update all flags and FPC does not track flag usage }
  254. if MatchInstruction(p, [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_DEC,A_EOR,
  255. A_INC,A_LSL,A_LSR,
  256. A_OR,A_ORI,A_ROL,A_ROR,A_SBC,A_SBCI,A_SUB,A_SUBI]) and
  257. GetNextInstruction(p, hp1) and
  258. ((MatchInstruction(hp1, A_CP) and
  259. (((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  260. (taicpu(hp1).oper[1]^.reg = GetDefaultZeroReg)) or
  261. ((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  262. (taicpu(hp1).oper[0]^.reg = GetDefaultZeroReg) and
  263. (taicpu(p).opcode in [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_EOR,
  264. A_LSL,A_LSR,
  265. A_OR,A_ORI,A_ROL,A_ROR,A_SUB,A_SBI])))) or
  266. (MatchInstruction(hp1, A_CPI) and
  267. (taicpu(p).opcode = A_ANDI) and
  268. (taicpu(p).oper[1]^.typ=top_const) and
  269. (taicpu(hp1).oper[1]^.typ=top_const) and
  270. (taicpu(p).oper[1]^.val=taicpu(hp1).oper[1]^.val))) and
  271. GetNextInstruction(hp1, hp2) and
  272. { be careful here, following instructions could use other flags
  273. however after a jump fpc never depends on the value of flags }
  274. { All above instructions set Z and N according to the following
  275. Z := result = 0;
  276. N := result[31];
  277. EQ = Z=1; NE = Z=0;
  278. MI = N=1; PL = N=0; }
  279. MatchInstruction(hp2, A_BRxx) and
  280. ((taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL]) or
  281. { sub/sbc set all flags }
  282. (taicpu(p).opcode in [A_SUB,A_SBI])){ and
  283. no flag allocation tracking implemented yet on avr
  284. assigned(FindRegDealloc(NR_DEFAULTFLAGS,tai(hp2.Next)))} then
  285. begin
  286. { move flag allocation if possible }
  287. { no flag allocation tracking implemented yet on avr
  288. GetLastInstruction(hp1, hp2);
  289. hp2:=FindRegAlloc(NR_DEFAULTFLAGS,tai(hp2.Next));
  290. if assigned(hp2) then
  291. begin
  292. asml.Remove(hp2);
  293. asml.insertbefore(hp2, p);
  294. end;
  295. }
  296. // If we compare to the same value we are masking then invert the comparison
  297. if (taicpu(hp1).opcode=A_CPI) or
  298. { sub/sbc with reverted? }
  299. ((taicpu(hp1).oper[0]^.reg = GetDefaultZeroReg) and (taicpu(p).opcode in [A_SUB,A_SBI])) then
  300. taicpu(hp2).condition:=inverse_cond(taicpu(hp2).condition);
  301. asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
  302. asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,hp2), hp2);
  303. IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
  304. DebugMsg('Peephole OpCp2Op performed', p);
  305. asml.remove(hp1);
  306. hp1.free;
  307. Result:=true;
  308. end
  309. else
  310. case taicpu(p).opcode of
  311. A_LDI:
  312. begin
  313. { turn
  314. ldi reg0, imm
  315. cp/mov reg1, reg0
  316. dealloc reg0
  317. into
  318. cpi/ldi reg1, imm
  319. }
  320. if MatchOpType(taicpu(p),top_reg,top_const) and
  321. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  322. MatchInstruction(hp1,[A_CP,A_MOV],2) and
  323. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  324. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  325. (getsupreg(taicpu(hp1).oper[0]^.reg) in [16..31]) and
  326. (taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
  327. not(MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^)) then
  328. begin
  329. CopyUsedRegs(TmpUsedRegs);
  330. if not(RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, hp1, TmpUsedRegs)) then
  331. begin
  332. case taicpu(hp1).opcode of
  333. A_CP:
  334. taicpu(hp1).opcode:=A_CPI;
  335. A_MOV:
  336. taicpu(hp1).opcode:=A_LDI;
  337. else
  338. internalerror(2016111901);
  339. end;
  340. taicpu(hp1).loadconst(1, taicpu(p).oper[1]^.val);
  341. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  342. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  343. if assigned(alloc) and assigned(dealloc) then
  344. begin
  345. asml.Remove(alloc);
  346. alloc.Free;
  347. asml.Remove(dealloc);
  348. dealloc.Free;
  349. end;
  350. DebugMsg('Peephole LdiMov/Cp2Ldi/Cpi performed', p);
  351. RemoveCurrentP(p);
  352. end;
  353. ReleaseUsedRegs(TmpUsedRegs);
  354. end;
  355. end;
  356. A_STS:
  357. if (taicpu(p).oper[0]^.ref^.symbol=nil) and
  358. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  359. (getsupreg(taicpu(p).oper[0]^.ref^.base)=RS_NO) and
  360. (getsupreg(taicpu(p).oper[0]^.ref^.index)=RS_NO) and
  361. (taicpu(p).oper[0]^.ref^.addressmode=AM_UNCHANGED) and
  362. // avrxmega3 doesn't map registers into data space so no offset to subtract
  363. (((current_settings.cputype = cpu_avrxmega3) and
  364. (taicpu(p).oper[0]^.ref^.offset>=0) and
  365. (taicpu(p).oper[0]^.ref^.offset<=63)) or
  366. ((current_settings.cputype <> cpu_avrxmega3) and
  367. (taicpu(p).oper[0]^.ref^.offset>=32) and
  368. (taicpu(p).oper[0]^.ref^.offset<=95))) then
  369. begin
  370. DebugMsg('Peephole Sts2Out performed', p);
  371. taicpu(p).opcode:=A_OUT;
  372. if current_settings.cputype = cpu_avrxmega3 then
  373. taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset)
  374. else
  375. taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32);
  376. end;
  377. A_LDS:
  378. if (taicpu(p).oper[1]^.ref^.symbol=nil) and
  379. (taicpu(p).oper[1]^.ref^.relsymbol=nil) and
  380. (getsupreg(taicpu(p).oper[1]^.ref^.base)=RS_NO) and
  381. (getsupreg(taicpu(p).oper[1]^.ref^.index)=RS_NO) and
  382. (taicpu(p).oper[1]^.ref^.addressmode=AM_UNCHANGED) and
  383. // avrxmega3 doesn't map registers into data space so no offset to subtract
  384. (((current_settings.cputype = cpu_avrxmega3) and
  385. (taicpu(p).oper[1]^.ref^.offset>=0) and
  386. (taicpu(p).oper[1]^.ref^.offset<=63)) or
  387. ((current_settings.cputype <> cpu_avrxmega3) and
  388. (taicpu(p).oper[1]^.ref^.offset>=32) and
  389. (taicpu(p).oper[1]^.ref^.offset<=95))) then
  390. begin
  391. DebugMsg('Peephole Lds2In performed', p);
  392. taicpu(p).opcode:=A_IN;
  393. if current_settings.cputype = cpu_avrxmega3 then
  394. taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset)
  395. else
  396. taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32);
  397. end;
  398. A_IN:
  399. if GetNextInstruction(p,hp1) then
  400. begin
  401. {
  402. in rX,Y
  403. ori rX,n
  404. out Y,rX
  405. into
  406. sbi rX,lg(n)
  407. }
  408. if (taicpu(p).oper[1]^.val<=31) and
  409. MatchInstruction(hp1,A_ORI) and
  410. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  411. (PopCnt(byte(taicpu(hp1).oper[1]^.val))=1) and
  412. GetNextInstruction(hp1,hp2) and
  413. MatchInstruction(hp2,A_OUT) and
  414. MatchOperand(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  415. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) then
  416. begin
  417. DebugMsg('Peephole InOriOut2Sbi performed', p);
  418. taicpu(p).opcode:=A_SBI;
  419. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  420. taicpu(p).loadconst(1,BsrByte(taicpu(hp1).oper[1]^.val));
  421. asml.Remove(hp1);
  422. hp1.Free;
  423. asml.Remove(hp2);
  424. hp2.Free;
  425. result:=true;
  426. end
  427. {
  428. in rX,Y
  429. andi rX,not(n)
  430. out Y,rX
  431. into
  432. cbi rX,lg(n)
  433. }
  434. else if (taicpu(p).oper[1]^.val<=31) and
  435. MatchInstruction(hp1,A_ANDI) and
  436. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  437. (PopCnt(byte(not(taicpu(hp1).oper[1]^.val)))=1) and
  438. GetNextInstruction(hp1,hp2) and
  439. MatchInstruction(hp2,A_OUT) and
  440. MatchOperand(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  441. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) then
  442. begin
  443. DebugMsg('Peephole InAndiOut2Cbi performed', p);
  444. taicpu(p).opcode:=A_CBI;
  445. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  446. taicpu(p).loadconst(1,BsrByte(not(taicpu(hp1).oper[1]^.val)));
  447. asml.Remove(hp1);
  448. hp1.Free;
  449. asml.Remove(hp2);
  450. hp2.Free;
  451. result:=true;
  452. end
  453. {
  454. in rX,Y
  455. andi rX,n
  456. breq/brne L1
  457. into
  458. sbis/sbic Y,lg(n)
  459. jmp L1
  460. .Ltemp:
  461. }
  462. else if (taicpu(p).oper[1]^.val<=31) and
  463. MatchInstruction(hp1,A_ANDI) and
  464. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  465. (PopCnt(byte(taicpu(hp1).oper[1]^.val))=1) and
  466. GetNextInstruction(hp1,hp2) and
  467. MatchInstruction(hp2,A_BRxx) and
  468. (taicpu(hp2).condition in [C_EQ,C_NE]) then
  469. begin
  470. if taicpu(hp2).condition=C_EQ then
  471. taicpu(p).opcode:=A_SBIS
  472. else
  473. taicpu(p).opcode:=A_SBIC;
  474. DebugMsg('Peephole InAndiBrx2SbixJmp performed', p);
  475. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  476. taicpu(p).loadconst(1,BsrByte(taicpu(hp1).oper[1]^.val));
  477. asml.Remove(hp1);
  478. hp1.Free;
  479. taicpu(hp2).condition:=C_None;
  480. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  481. taicpu(hp2).opcode:=A_JMP
  482. else
  483. taicpu(hp2).opcode:=A_RJMP;
  484. current_asmdata.getjumplabel(l);
  485. l.increfs;
  486. asml.InsertAfter(tai_label.create(l), hp2);
  487. result:=true;
  488. end;
  489. end;
  490. A_SBRS,
  491. A_SBRC:
  492. begin
  493. {
  494. Turn
  495. in rx, y
  496. sbr* rx, z
  497. Into
  498. sbi* y, z
  499. }
  500. if (taicpu(p).ops=2) and
  501. (taicpu(p).oper[0]^.typ=top_reg) and
  502. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  503. GetLastInstruction(p,hp1) and
  504. (hp1.typ=ait_instruction) and
  505. (taicpu(hp1).opcode=A_IN) and
  506. (taicpu(hp1).ops=2) and
  507. (taicpu(hp1).oper[1]^.typ=top_const) and
  508. (taicpu(hp1).oper[1]^.val in [0..31]) and
  509. MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^.reg) and
  510. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, hp1, p)) then
  511. begin
  512. if taicpu(p).opcode=A_SBRS then
  513. taicpu(p).opcode:=A_SBIS
  514. else
  515. taicpu(p).opcode:=A_SBIC;
  516. taicpu(p).loadconst(0, taicpu(hp1).oper[1]^.val);
  517. DebugMsg('Peephole InSbrx2Sbix performed', p);
  518. asml.Remove(hp1);
  519. hp1.free;
  520. result:=true;
  521. end;
  522. if InvertSkipInstruction(p) then
  523. result:=true;
  524. end;
  525. A_ANDI:
  526. begin
  527. {
  528. Turn
  529. andi rx, #pow2
  530. brne l
  531. <op>
  532. l:
  533. Into
  534. sbrs rx, #(1 shl imm)
  535. <op>
  536. l:
  537. }
  538. if (taicpu(p).ops=2) and
  539. (taicpu(p).oper[1]^.typ=top_const) and
  540. ispowerof2(taicpu(p).oper[1]^.val,i) and
  541. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  542. GetNextInstruction(p,hp1) and
  543. (hp1.typ=ait_instruction) and
  544. (taicpu(hp1).opcode=A_BRxx) and
  545. (taicpu(hp1).condition in [C_EQ,C_NE]) and
  546. (taicpu(hp1).ops>0) and
  547. (taicpu(hp1).oper[0]^.typ = top_ref) and
  548. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  549. GetNextInstruction(hp1,hp2) and
  550. (hp2.typ=ait_instruction) and
  551. GetNextInstruction(hp2,hp3) and
  552. (hp3.typ=ait_label) and
  553. (taicpu(hp1).oper[0]^.ref^.symbol=tai_label(hp3).labsym) then
  554. begin
  555. DebugMsg('Peephole AndiBr2Sbr performed', p);
  556. taicpu(p).oper[1]^.val:=i;
  557. if taicpu(hp1).condition=C_NE then
  558. taicpu(p).opcode:=A_SBRS
  559. else
  560. taicpu(p).opcode:=A_SBRC;
  561. asml.Remove(hp1);
  562. hp1.free;
  563. result:=true;
  564. end
  565. {
  566. Remove
  567. andi rx, #y
  568. dealloc rx
  569. }
  570. else if (taicpu(p).ops=2) and
  571. (taicpu(p).oper[0]^.typ=top_reg) and
  572. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  573. (assigned(FindRegDeAlloc(NR_DEFAULTFLAGS,tai(p.Next))) or
  574. (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs))) then
  575. begin
  576. DebugMsg('Redundant Andi removed', p);
  577. result:=RemoveCurrentP(p);
  578. end;
  579. end;
  580. A_ADD:
  581. begin
  582. if (taicpu(p).oper[1]^.reg=GetDefaultZeroReg) and
  583. GetNextInstruction(p, hp1) and
  584. MatchInstruction(hp1,A_ADC) then
  585. begin
  586. DebugMsg('Peephole AddAdc2Add performed', p);
  587. result:=RemoveCurrentP(p);
  588. end;
  589. end;
  590. A_SUB:
  591. begin
  592. if (taicpu(p).oper[1]^.reg=GetDefaultZeroReg) and
  593. GetNextInstruction(p, hp1) and
  594. MatchInstruction(hp1,A_SBC) then
  595. begin
  596. DebugMsg('Peephole SubSbc2Sub performed', p);
  597. taicpu(hp1).opcode:=A_SUB;
  598. result:=RemoveCurrentP(p);
  599. end;
  600. end;
  601. A_CLR:
  602. begin
  603. { turn the common
  604. clr rX
  605. mov/ld rX, rY
  606. into
  607. mov/ld rX, rY
  608. }
  609. if (taicpu(p).ops=1) and
  610. (taicpu(p).oper[0]^.typ=top_reg) and
  611. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  612. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  613. (hp1.typ=ait_instruction) and
  614. (taicpu(hp1).opcode in [A_MOV,A_LD]) and
  615. (taicpu(hp1).ops>0) and
  616. (taicpu(hp1).oper[0]^.typ=top_reg) and
  617. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) then
  618. begin
  619. DebugMsg('Peephole ClrMov2Mov performed', p);
  620. result:=RemoveCurrentP(p);
  621. end
  622. { turn
  623. clr rX
  624. ...
  625. adc rY, rX
  626. into
  627. ...
  628. adc rY, r1
  629. }
  630. else if (taicpu(p).ops=1) and
  631. (taicpu(p).oper[0]^.typ=top_reg) and
  632. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  633. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  634. (hp1.typ=ait_instruction) and
  635. (taicpu(hp1).opcode in [A_ADC,A_SBC]) and
  636. (taicpu(hp1).ops=2) and
  637. (taicpu(hp1).oper[1]^.typ=top_reg) and
  638. (taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
  639. (taicpu(hp1).oper[0]^.reg<>taicpu(p).oper[0]^.reg) and
  640. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
  641. begin
  642. DebugMsg('Peephole ClrAdc2Adc performed', p);
  643. taicpu(hp1).oper[1]^.reg:=GetDefaultZeroReg;
  644. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  645. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  646. if assigned(alloc) and assigned(dealloc) then
  647. begin
  648. asml.Remove(alloc);
  649. alloc.Free;
  650. asml.Remove(dealloc);
  651. dealloc.Free;
  652. end;
  653. result:=RemoveCurrentP(p);
  654. end;
  655. end;
  656. A_PUSH:
  657. begin
  658. { turn
  659. push reg0
  660. push reg1
  661. pop reg3
  662. pop reg2
  663. into
  664. movw reg2,reg0
  665. or
  666. mov reg3,reg1
  667. mov reg2,reg0
  668. }
  669. if GetNextInstruction(p,hp1) and
  670. MatchInstruction(hp1,A_PUSH) and
  671. GetNextInstruction(hp1,hp2) and
  672. MatchInstruction(hp2,A_POP) and
  673. GetNextInstruction(hp2,hp3) and
  674. MatchInstruction(hp3,A_POP) then
  675. begin
  676. if (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
  677. ((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
  678. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp3).oper[0]^.reg)+1) and
  679. ((getsupreg(taicpu(hp3).oper[0]^.reg) mod 2)=0) then
  680. begin
  681. DebugMsg('Peephole PushPushPopPop2Movw performed', p);
  682. taicpu(hp3).ops:=2;
  683. taicpu(hp3).opcode:=A_MOVW;
  684. taicpu(hp3).loadreg(1, taicpu(p).oper[0]^.reg);
  685. RemoveCurrentP(p);
  686. RemoveCurrentP(p);
  687. result:=RemoveCurrentP(p);
  688. end
  689. else
  690. begin
  691. DebugMsg('Peephole PushPushPopPop2MovMov performed', p);
  692. taicpu(p).ops:=2;
  693. taicpu(p).opcode:=A_MOV;
  694. taicpu(hp1).ops:=2;
  695. taicpu(hp1).opcode:=A_MOV;
  696. taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
  697. taicpu(p).loadreg(0, taicpu(hp3).oper[0]^.reg);
  698. taicpu(hp1).loadreg(1, taicpu(hp1).oper[0]^.reg);
  699. taicpu(hp1).loadreg(0, taicpu(hp2).oper[0]^.reg);
  700. { life range of reg2 and reg3 is increased, fix register allocation entries }
  701. CopyUsedRegs(TmpUsedRegs);
  702. UpdateUsedRegs(TmpUsedRegs,tai(p.Next));
  703. AllocRegBetween(taicpu(hp2).oper[0]^.reg,hp1,hp2,TmpUsedRegs);
  704. ReleaseUsedRegs(TmpUsedRegs);
  705. CopyUsedRegs(TmpUsedRegs);
  706. AllocRegBetween(taicpu(hp3).oper[0]^.reg,p,hp3,TmpUsedRegs);
  707. ReleaseUsedRegs(TmpUsedRegs);
  708. IncludeRegInUsedRegs(taicpu(hp3).oper[0]^.reg,UsedRegs);
  709. UpdateUsedRegs(tai(p.Next));
  710. asml.Remove(hp2);
  711. hp2.Free;
  712. asml.Remove(hp3);
  713. hp3.Free;
  714. result:=true;
  715. end
  716. end;
  717. end;
  718. A_CALL:
  719. if (cs_opt_level4 in current_settings.optimizerswitches) and
  720. GetNextInstruction(p,hp1) and
  721. MatchInstruction(hp1,A_RET) then
  722. begin
  723. DebugMsg('Peephole CallReg2Jmp performed', p);
  724. taicpu(p).opcode:=A_JMP;
  725. asml.Remove(hp1);
  726. hp1.Free;
  727. result:=true;
  728. end;
  729. A_RCALL:
  730. if (cs_opt_level4 in current_settings.optimizerswitches) and
  731. GetNextInstruction(p,hp1) and
  732. MatchInstruction(hp1,A_RET) then
  733. begin
  734. DebugMsg('Peephole RCallReg2RJmp performed', p);
  735. taicpu(p).opcode:=A_RJMP;
  736. asml.Remove(hp1);
  737. hp1.Free;
  738. result:=true;
  739. end;
  740. A_MOV:
  741. begin
  742. { change
  743. mov reg0, reg1
  744. dealloc reg0
  745. into
  746. dealloc reg0
  747. }
  748. if MatchOpType(taicpu(p),top_reg,top_reg) then
  749. begin
  750. CopyUsedRegs(TmpUsedRegs);
  751. UpdateUsedRegs(TmpUsedRegs,tai(p.Next));
  752. if not(RegInUsedRegs(taicpu(p).oper[0]^.reg,TmpUsedRegs)) and
  753. { reg. allocation information before calls is not perfect, so don't do this before
  754. calls/icalls }
  755. GetNextInstruction(p,hp1) and
  756. not(MatchInstruction(hp1,[A_CALL,A_RCALL])) then
  757. begin
  758. DebugMsg('Peephole Mov2Nop performed', p);
  759. result:=RemoveCurrentP(p);
  760. ReleaseUsedRegs(TmpUsedRegs);
  761. exit;
  762. end;
  763. ReleaseUsedRegs(TmpUsedRegs);
  764. end;
  765. { turn
  766. mov reg0, reg1
  767. <op> reg2,reg0
  768. dealloc reg0
  769. into
  770. <op> reg2,reg1
  771. }
  772. if MatchOpType(taicpu(p),top_reg,top_reg) and
  773. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  774. (not RegModifiedBetween(taicpu(p).oper[1]^.reg, p, hp1)) and
  775. (MatchInstruction(hp1,[A_PUSH,A_MOV,A_CP,A_CPC,A_ADD,A_SUB,A_ADC,A_SBC,A_EOR,A_AND,A_OR,
  776. A_OUT,A_IN]) or
  777. { the reference register of ST/STD cannot be replaced }
  778. (MatchInstruction(hp1,[A_STD,A_ST,A_STS]) and (MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^)))) and
  779. (not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1)) and
  780. {(taicpu(hp1).ops=1) and
  781. (taicpu(hp1).oper[0]^.typ = top_reg) and
  782. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and }
  783. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
  784. begin
  785. DebugMsg('Peephole MovOp2Op performed', p);
  786. for i := 0 to taicpu(hp1).ops-1 do
  787. if taicpu(hp1).oper[i]^.typ=top_reg then
  788. if taicpu(hp1).oper[i]^.reg=taicpu(p).oper[0]^.reg then
  789. taicpu(hp1).oper[i]^.reg:=taicpu(p).oper[1]^.reg;
  790. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  791. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  792. if assigned(alloc) and assigned(dealloc) then
  793. begin
  794. asml.Remove(alloc);
  795. alloc.Free;
  796. asml.Remove(dealloc);
  797. dealloc.Free;
  798. end;
  799. { life range of reg1 is increased }
  800. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,usedregs);
  801. { p will be removed, update used register as we continue
  802. with the next instruction after p }
  803. result:=RemoveCurrentP(p);
  804. end
  805. { remove
  806. mov reg0,reg0
  807. }
  808. else if (taicpu(p).ops=2) and
  809. (taicpu(p).oper[0]^.typ = top_reg) and
  810. (taicpu(p).oper[1]^.typ = top_reg) and
  811. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  812. begin
  813. DebugMsg('Peephole RedundantMov performed', p);
  814. result:=RemoveCurrentP(p);
  815. end
  816. {
  817. Turn
  818. mov rx,ry
  819. op rx,rz
  820. mov ry, rx
  821. Into
  822. op ry,rz
  823. }
  824. else if (taicpu(p).ops=2) and
  825. MatchOpType(taicpu(p),top_reg,top_reg) and
  826. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  827. (hp1.typ=ait_instruction) and
  828. (taicpu(hp1).ops >= 1) and
  829. (taicpu(hp1).oper[0]^.typ = top_reg) and
  830. GetNextInstructionUsingReg(hp1,hp2,taicpu(hp1).oper[0]^.reg) and
  831. MatchInstruction(hp2,A_MOV) and
  832. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  833. (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  834. (taicpu(hp2).oper[1]^.reg = taicpu(hp1).oper[0]^.reg) and
  835. (taicpu(hp2).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
  836. (not RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp2)) and
  837. (taicpu(hp1).opcode in [A_ADD,A_ADC,A_SUB,A_SBC,A_AND,A_OR,A_EOR,
  838. A_INC,A_DEC,
  839. A_LSL,A_LSR,A_ASR,A_ROR,A_ROL]) and
  840. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg, tai(hp2.Next))) then
  841. begin
  842. DebugMsg('Peephole MovOpMov2Op performed', p);
  843. if (taicpu(hp1).ops=2) and
  844. (taicpu(hp1).oper[1]^.typ=top_reg) and
  845. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  846. taicpu(hp1).oper[1]^.reg:=taicpu(p).oper[1]^.reg;
  847. taicpu(hp1).oper[0]^.reg:=taicpu(p).oper[1]^.reg;
  848. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  849. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp2.Next));
  850. if assigned(alloc) and assigned(dealloc) then
  851. begin
  852. asml.Remove(alloc);
  853. alloc.Free;
  854. asml.Remove(dealloc);
  855. dealloc.Free;
  856. end;
  857. asml.remove(hp2);
  858. hp2.free;
  859. result:=RemoveCurrentP(p);
  860. end
  861. {
  862. Turn
  863. mov rx,ry
  864. op rx,rw
  865. mov rw,rx
  866. Into
  867. op rw,ry
  868. }
  869. else if (taicpu(p).ops=2) and
  870. MatchOpType(taicpu(p),top_reg,top_reg) and
  871. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  872. (hp1.typ=ait_instruction) and
  873. (taicpu(hp1).ops = 2) and
  874. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  875. GetNextInstructionUsingReg(hp1,hp2,taicpu(hp1).oper[0]^.reg) and
  876. (hp2.typ=ait_instruction) and
  877. (taicpu(hp2).opcode=A_MOV) and
  878. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  879. (taicpu(hp2).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  880. (taicpu(hp2).oper[1]^.reg = taicpu(hp1).oper[0]^.reg) and
  881. (taicpu(hp2).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
  882. (not RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) and
  883. (taicpu(hp1).opcode in [A_ADD,A_ADC,A_AND,A_OR,A_EOR]) and
  884. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg, tai(hp2.Next))) then
  885. begin
  886. DebugMsg('Peephole MovOpMov2Op2 performed', p);
  887. taicpu(hp1).oper[0]^.reg:=taicpu(hp2).oper[0]^.reg;
  888. taicpu(hp1).oper[1]^.reg:=taicpu(p).oper[1]^.reg;
  889. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  890. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp2.Next));
  891. if assigned(alloc) and assigned(dealloc) then
  892. begin
  893. asml.Remove(alloc);
  894. alloc.Free;
  895. asml.Remove(dealloc);
  896. dealloc.Free;
  897. end;
  898. result:=RemoveCurrentP(p);
  899. asml.remove(hp2);
  900. hp2.free;
  901. end
  902. { fold
  903. mov reg2,reg0
  904. mov reg3,reg1
  905. to
  906. movw reg2,reg0
  907. }
  908. else if (CPUAVR_HAS_MOVW in cpu_capabilities[current_settings.cputype]) and
  909. (taicpu(p).ops=2) and
  910. (taicpu(p).oper[0]^.typ = top_reg) and
  911. (taicpu(p).oper[1]^.typ = top_reg) and
  912. getnextinstruction(p,hp1) and
  913. (hp1.typ = ait_instruction) and
  914. (taicpu(hp1).opcode = A_MOV) and
  915. (taicpu(hp1).ops=2) and
  916. (taicpu(hp1).oper[0]^.typ = top_reg) and
  917. (taicpu(hp1).oper[1]^.typ = top_reg) and
  918. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
  919. ((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
  920. ((getsupreg(taicpu(p).oper[1]^.reg) mod 2)=0) and
  921. (getsupreg(taicpu(hp1).oper[1]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)+1) then
  922. begin
  923. DebugMsg('Peephole MovMov2Movw performed', p);
  924. alloc:=FindRegAllocBackward(taicpu(hp1).oper[0]^.reg,tai(hp1.Previous));
  925. if assigned(alloc) then
  926. begin
  927. asml.Remove(alloc);
  928. asml.InsertBefore(alloc,p);
  929. { proper book keeping of currently used registers }
  930. IncludeRegInUsedRegs(taicpu(hp1).oper[0]^.reg,UsedRegs);
  931. end;
  932. taicpu(p).opcode:=A_MOVW;
  933. asml.remove(hp1);
  934. hp1.free;
  935. result:=true;
  936. end
  937. {
  938. This removes the first mov from
  939. mov rX,...
  940. mov rX,...
  941. }
  942. else if GetNextInstruction(p,hp1) and MatchInstruction(hp1,A_MOV) then
  943. while MatchInstruction(hp1,A_MOV) and
  944. MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) and
  945. { don't remove the first mov if the second is a mov rX,rX }
  946. not(MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^)) do
  947. begin
  948. DebugMsg('Peephole MovMov2Mov performed', p);
  949. result:=RemoveCurrentP(p);
  950. GetNextInstruction(hp1,hp1);
  951. if not assigned(hp1) then
  952. break;
  953. end;
  954. end;
  955. A_SBIC,
  956. A_SBIS:
  957. begin
  958. {
  959. Turn
  960. sbic/sbis X, y
  961. jmp .L1
  962. op
  963. .L1:
  964. into
  965. sbis/sbic X,y
  966. op
  967. .L1:
  968. }
  969. if InvertSkipInstruction(p) then
  970. result:=true
  971. {
  972. Turn
  973. sbiX X, y
  974. jmp .L1
  975. jmp .L2
  976. .L1:
  977. op
  978. .L2:
  979. into
  980. sbiX X,y
  981. .L1:
  982. op
  983. .L2:
  984. }
  985. else if GetNextInstruction(p, hp1) and
  986. (hp1.typ=ait_instruction) and
  987. (taicpu(hp1).opcode in [A_JMP,A_RJMP]) and
  988. (taicpu(hp1).ops>0) and
  989. (taicpu(hp1).oper[0]^.typ = top_ref) and
  990. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  991. GetNextInstruction(hp1, hp2) and
  992. (hp2.typ=ait_instruction) and
  993. (taicpu(hp2).opcode in [A_JMP,A_RJMP]) and
  994. (taicpu(hp2).ops>0) and
  995. (taicpu(hp2).oper[0]^.typ = top_ref) and
  996. (taicpu(hp2).oper[0]^.ref^.symbol is TAsmLabel) and
  997. GetNextInstruction(hp2, hp3) and
  998. (hp3.typ=ait_label) and
  999. (taicpu(hp1).oper[0]^.ref^.symbol=tai_label(hp3).labsym) and
  1000. GetNextInstruction(hp3, hp4) and
  1001. (hp4.typ=ait_instruction) and
  1002. GetNextInstruction(hp4, hp5) and
  1003. (hp3.typ=ait_label) and
  1004. (taicpu(hp2).oper[0]^.ref^.symbol=tai_label(hp5).labsym) then
  1005. begin
  1006. DebugMsg('Peephole SbiJmpJmp2Sbi performed',p);
  1007. tai_label(hp3).labsym.decrefs;
  1008. tai_label(hp5).labsym.decrefs;
  1009. AsmL.remove(hp1);
  1010. taicpu(hp1).Free;
  1011. AsmL.remove(hp2);
  1012. taicpu(hp2).Free;
  1013. result:=true;
  1014. end;
  1015. end;
  1016. end;
  1017. end;
  1018. end;
  1019. end;
  1020. procedure TCpuAsmOptimizer.PeepHoleOptPass2;
  1021. begin
  1022. end;
  1023. begin
  1024. casmoptimizer:=TCpuAsmOptimizer;
  1025. End.