aoptcpu.pas 12 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer for i386
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aoptcpu;
  18. {$i fpcdefs.inc}
  19. { $define DEBUG_AOPTCPU}
  20. Interface
  21. uses
  22. cgbase,
  23. cpubase, aopt, aoptx86,
  24. Aasmbase,aasmtai,aasmdata;
  25. Type
  26. TCpuAsmOptimizer = class(TX86AsmOptimizer)
  27. function PrePeepHoleOptsCpu(var p: tai): boolean; override;
  28. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  29. function PeepHoleOptPass2Cpu(var p: tai): boolean; override;
  30. function PostPeepHoleOptsCpu(var p : tai) : boolean; override;
  31. end;
  32. Var
  33. AsmOptimizer : TCpuAsmOptimizer;
  34. Implementation
  35. uses
  36. verbose,globtype,globals,
  37. cpuinfo,
  38. aasmcpu,
  39. aoptutils,
  40. aasmcfi,
  41. procinfo,
  42. cgutils,
  43. { units we should get rid off: }
  44. symsym,symconst;
  45. { Checks if the register is a 32 bit general purpose register }
  46. function isgp32reg(reg: TRegister): boolean;
  47. begin
  48. {$push}{$warnings off}
  49. isgp32reg:=(getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)>=RS_EAX) and (getsupreg(reg)<=RS_EBX);
  50. {$pop}
  51. end;
  52. { returns true if p contains a memory operand with a segment set }
  53. function InsContainsSegRef(p: taicpu): boolean;
  54. var
  55. i: longint;
  56. begin
  57. result:=true;
  58. for i:=0 to p.opercnt-1 do
  59. if (p.oper[i]^.typ=top_ref) and
  60. (p.oper[i]^.ref^.segment<>NR_NO) then
  61. exit;
  62. result:=false;
  63. end;
  64. function TCPUAsmOPtimizer.PrePeepHoleOptsCpu(var p: tai): boolean;
  65. begin
  66. repeat
  67. Result:=False;
  68. case p.typ of
  69. ait_instruction:
  70. begin
  71. if InsContainsSegRef(taicpu(p)) then
  72. begin
  73. p := tai(p.next);
  74. { Nothing's actually changed, so no need to set Result to True,
  75. but try again to see if an instruction immediately follows }
  76. Continue;
  77. end;
  78. case taicpu(p).opcode Of
  79. A_IMUL:
  80. Result:=PrePeepholeOptIMUL(p);
  81. A_SAR,A_SHR:
  82. Result:=PrePeepholeOptSxx(p);
  83. A_XOR:
  84. begin
  85. if (taicpu(p).oper[0]^.typ = top_reg) and
  86. (taicpu(p).oper[1]^.typ = top_reg) and
  87. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  88. { temporarily change this to 'mov reg,0' to make it easier }
  89. { for the CSE. Will be changed back in pass 2 }
  90. begin
  91. taicpu(p).opcode := A_MOV;
  92. taicpu(p).loadConst(0,0);
  93. Result:=true;
  94. end;
  95. end;
  96. else
  97. { Do nothing };
  98. end;
  99. end;
  100. else
  101. { Do nothing };
  102. end;
  103. Break;
  104. until False;
  105. end;
  106. function TCPUAsmOPtimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  107. var
  108. hp1 : tai;
  109. begin
  110. result:=False;
  111. case p.Typ Of
  112. ait_instruction:
  113. begin
  114. current_filepos:=taicpu(p).fileinfo;
  115. if InsContainsSegRef(taicpu(p)) then
  116. exit;
  117. case taicpu(p).opcode Of
  118. A_AND:
  119. Result:=OptPass1And(p);
  120. A_IMUL:
  121. Result:=OptPass1Imul(p);
  122. A_CMP:
  123. Result:=OptPass1Cmp(p);
  124. A_VPXOR:
  125. Result:=OptPass1VPXor(p);
  126. A_PXOR:
  127. Result:=OptPass1PXor(p);
  128. A_FLD:
  129. Result:=OptPass1FLD(p);
  130. A_FSTP,A_FISTP:
  131. Result:=OptPass1FSTP(p);
  132. A_LEA:
  133. Result:=OptPass1LEA(p);
  134. A_MOV:
  135. Result:=OptPass1MOV(p);
  136. A_MOVSX,
  137. A_MOVZX :
  138. Result:=OptPass1Movx(p);
  139. A_PUSH:
  140. begin
  141. if (taicpu(p).opsize = S_W) and
  142. (taicpu(p).oper[0]^.typ = Top_Const) and
  143. GetNextInstruction(p, hp1) and
  144. (tai(hp1).typ = ait_instruction) and
  145. (taicpu(hp1).opcode = A_PUSH) and
  146. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  147. (taicpu(hp1).opsize = S_W) then
  148. begin
  149. taicpu(p).changeopsize(S_L);
  150. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val shl 16 + word(taicpu(hp1).oper[0]^.val));
  151. asml.remove(hp1);
  152. hp1.free;
  153. Result:=true;
  154. end;
  155. end;
  156. A_SHL, A_SAL:
  157. Result:=OptPass1SHLSAL(p);
  158. A_SUB:
  159. Result:=OptPass1Sub(p);
  160. A_MOVAPD,
  161. A_MOVAPS,
  162. A_MOVUPD,
  163. A_MOVUPS,
  164. A_VMOVAPS,
  165. A_VMOVAPD,
  166. A_VMOVUPS,
  167. A_VMOVUPD:
  168. Result:=OptPass1_V_MOVAP(p);
  169. A_VDIVSD,
  170. A_VDIVSS,
  171. A_VSUBSD,
  172. A_VSUBSS,
  173. A_VMULSD,
  174. A_VMULSS,
  175. A_VADDSD,
  176. A_VADDSS,
  177. A_VANDPD,
  178. A_VANDPS,
  179. A_VORPD,
  180. A_VORPS,
  181. A_VXORPD,
  182. A_VXORPS:
  183. Result:=OptPass1VOP(p);
  184. A_MULSD,
  185. A_MULSS,
  186. A_ADDSD,
  187. A_ADDSS:
  188. Result:=OptPass1OP(p);
  189. A_VMOVSD,
  190. A_VMOVSS,
  191. A_MOVSD,
  192. A_MOVSS:
  193. Result:=OptPass1MOVXX(p);
  194. A_SETcc:
  195. Result:=OptPass1SETcc(p);
  196. else
  197. ;
  198. end;
  199. end;
  200. else
  201. ;
  202. end;
  203. end;
  204. function TCPUAsmOptimizer.PeepHoleOptPass2Cpu(var p: tai): boolean;
  205. begin
  206. Result:=false;
  207. case p.Typ Of
  208. Ait_Instruction:
  209. begin
  210. if InsContainsSegRef(taicpu(p)) then
  211. exit;
  212. case taicpu(p).opcode Of
  213. A_Jcc:
  214. Result:=OptPass2Jcc(p);
  215. A_Lea:
  216. Result:=OptPass2Lea(p);
  217. A_FSTP,A_FISTP:
  218. Result:=OptPass1FSTP(p);
  219. A_IMUL:
  220. Result:=OptPass2Imul(p);
  221. A_JMP:
  222. Result:=OptPass2Jmp(p);
  223. A_MOV:
  224. Result:=OptPass2MOV(p);
  225. A_SUB:
  226. Result:=OptPass2SUB(p);
  227. else
  228. ;
  229. end;
  230. end;
  231. else
  232. ;
  233. end;
  234. end;
  235. function TCPUAsmOptimizer.PostPeepHoleOptsCpu(var p : tai) : boolean;
  236. var
  237. hp1: tai;
  238. begin
  239. Result:=false;
  240. case p.Typ Of
  241. Ait_Instruction:
  242. begin
  243. if InsContainsSegRef(taicpu(p)) then
  244. Exit;
  245. case taicpu(p).opcode Of
  246. A_CALL:
  247. Result:=PostPeepHoleOptCall(p);
  248. A_LEA:
  249. Result:=PostPeepholeOptLea(p);
  250. A_CMP:
  251. Result:=PostPeepholeOptCmp(p);
  252. A_MOV:
  253. Result:=PostPeepholeOptMov(p);
  254. A_MOVZX:
  255. { if register vars are on, it's possible there is code like }
  256. { "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx" }
  257. { so we can't safely replace the movzx then with xor/mov, }
  258. { since that would change the flags (JM) }
  259. if not(cs_opt_regvar in current_settings.optimizerswitches) then
  260. begin
  261. if (taicpu(p).oper[1]^.typ = top_reg) then
  262. if (taicpu(p).oper[0]^.typ = top_reg)
  263. then
  264. case taicpu(p).opsize of
  265. S_BL:
  266. begin
  267. if IsGP32Reg(taicpu(p).oper[1]^.reg) and
  268. not(cs_opt_size in current_settings.optimizerswitches) and
  269. (current_settings.optimizecputype = cpu_Pentium) then
  270. {Change "movzbl %reg1, %reg2" to
  271. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  272. PentiumMMX}
  273. begin
  274. hp1 := taicpu.op_reg_reg(A_XOR, S_L,
  275. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  276. InsertLLItem(p.previous, p, hp1);
  277. taicpu(p).opcode := A_MOV;
  278. taicpu(p).changeopsize(S_B);
  279. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  280. Result := True;
  281. end;
  282. end;
  283. else
  284. ;
  285. end
  286. else if (taicpu(p).oper[0]^.typ = top_ref) and
  287. (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  288. (taicpu(p).oper[0]^.ref^.index <> taicpu(p).oper[1]^.reg) and
  289. not(cs_opt_size in current_settings.optimizerswitches) and
  290. IsGP32Reg(taicpu(p).oper[1]^.reg) and
  291. (current_settings.optimizecputype = cpu_Pentium) and
  292. (taicpu(p).opsize = S_BL) then
  293. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  294. Pentium and PentiumMMX}
  295. begin
  296. hp1 := taicpu.Op_reg_reg(A_XOR, S_L, taicpu(p).oper[1]^.reg,
  297. taicpu(p).oper[1]^.reg);
  298. taicpu(p).opcode := A_MOV;
  299. taicpu(p).changeopsize(S_B);
  300. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  301. InsertLLItem(p.previous, p, hp1);
  302. Result := True;
  303. end;
  304. end;
  305. A_TEST, A_OR:
  306. Result:=PostPeepholeOptTestOr(p);
  307. A_MOVSX:
  308. Result:=PostPeepholeOptMOVSX(p);
  309. else
  310. ;
  311. end;
  312. { Optimise any reference-type operands (if Result is True, the
  313. instruction will be checked on the next iteration) }
  314. if not Result then
  315. OptimizeRefs(taicpu(p));
  316. end;
  317. else
  318. ;
  319. end;
  320. end;
  321. begin
  322. casmoptimizer:=TCpuAsmOptimizer;
  323. end.