samd51p19a.pp 98 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093
  1. unit samd51p19a;
  2. (*
  3. Copyright (c) 2020 Microchip Technology Inc.
  4. Licensed under the Apache License, Version 2.0 (the "License");
  5. you may not use this file except in compliance with the License.
  6. You may obtain a copy of the Licence at
  7. http://www.apache.org/licenses/LICENSE-2.0
  8. Unless required by applicable law or agreed to in writing, software
  9. distributed under the License is distributed on an "AS IS" BASIS,
  10. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. See the License for the specific language governing permissions and
  12. limitations under the License.
  13. *)
  14. interface
  15. {$PACKRECORDS C}
  16. {$GOTO ON}
  17. {$SCOPEDENUMS ON}
  18. {$DEFINE INTERFACE}
  19. {$UNDEF IMPLEMENTATION}
  20. {$DEFINE __CORTEXM4}
  21. {$DEFINE __NVIC_PRIO_BITS3 }
  22. const
  23. __FPU_PRESENT=1;
  24. __MPU_PRESENT=1;
  25. __NVIC_PRIO_BITS=3;
  26. type
  27. TIRQn_Enum = (
  28. NonMaskableInt_IRQn = -14,
  29. HardFault_IRQn = -13,
  30. MemoryManagement_IRQn = -12,
  31. BusFault_IRQn = -11,
  32. UsageFault_IRQn = -10,
  33. SVCall_IRQn = -5,
  34. DebugMonitor_IRQn = -4,
  35. PendSV_IRQn = -2,
  36. SysTick_IRQn = -1,
  37. PM_IRQn = 0,
  38. MCLK_IRQn = 1,
  39. OSCCTRL_0_IRQn = 2,
  40. OSCCTRL_1_IRQn = 3,
  41. OSCCTRL_2_IRQn = 4,
  42. OSCCTRL_3_IRQn = 5,
  43. OSCCTRL_4_IRQn = 6,
  44. OSC32KCTRL_IRQn = 7,
  45. SUPC_0_IRQn = 8,
  46. SUPC_1_IRQn = 9,
  47. WDT_IRQn = 10,
  48. RTC_IRQn = 11,
  49. EIC_0_IRQn = 12,
  50. EIC_1_IRQn = 13,
  51. EIC_2_IRQn = 14,
  52. EIC_3_IRQn = 15,
  53. EIC_4_IRQn = 16,
  54. EIC_5_IRQn = 17,
  55. EIC_6_IRQn = 18,
  56. EIC_7_IRQn = 19,
  57. EIC_8_IRQn = 20,
  58. EIC_9_IRQn = 21,
  59. EIC_10_IRQn = 22,
  60. EIC_11_IRQn = 23,
  61. EIC_12_IRQn = 24,
  62. EIC_13_IRQn = 25,
  63. EIC_14_IRQn = 26,
  64. EIC_15_IRQn = 27,
  65. FREQM_IRQn = 28,
  66. NVMCTRL_0_IRQn = 29,
  67. NVMCTRL_1_IRQn = 30,
  68. DMAC_0_IRQn = 31,
  69. DMAC_1_IRQn = 32,
  70. DMAC_2_IRQn = 33,
  71. DMAC_3_IRQn = 34,
  72. DMAC_4_IRQn = 35,
  73. EVSYS_0_IRQn = 36,
  74. EVSYS_1_IRQn = 37,
  75. EVSYS_2_IRQn = 38,
  76. EVSYS_3_IRQn = 39,
  77. EVSYS_4_IRQn = 40,
  78. PAC_IRQn = 41,
  79. RAMECC_IRQn = 45,
  80. SERCOM0_0_IRQn = 46,
  81. SERCOM0_1_IRQn = 47,
  82. SERCOM0_2_IRQn = 48,
  83. SERCOM0_3_IRQn = 49,
  84. SERCOM1_0_IRQn = 50,
  85. SERCOM1_1_IRQn = 51,
  86. SERCOM1_2_IRQn = 52,
  87. SERCOM1_3_IRQn = 53,
  88. SERCOM2_0_IRQn = 54,
  89. SERCOM2_1_IRQn = 55,
  90. SERCOM2_2_IRQn = 56,
  91. SERCOM2_3_IRQn = 57,
  92. SERCOM3_0_IRQn = 58,
  93. SERCOM3_1_IRQn = 59,
  94. SERCOM3_2_IRQn = 60,
  95. SERCOM3_3_IRQn = 61,
  96. SERCOM4_0_IRQn = 62,
  97. SERCOM4_1_IRQn = 63,
  98. SERCOM4_2_IRQn = 64,
  99. SERCOM4_3_IRQn = 65,
  100. SERCOM5_0_IRQn = 66,
  101. SERCOM5_1_IRQn = 67,
  102. SERCOM5_2_IRQn = 68,
  103. SERCOM5_3_IRQn = 69,
  104. SERCOM6_0_IRQn = 70,
  105. SERCOM6_1_IRQn = 71,
  106. SERCOM6_2_IRQn = 72,
  107. SERCOM6_3_IRQn = 73,
  108. SERCOM7_0_IRQn = 74,
  109. SERCOM7_1_IRQn = 75,
  110. SERCOM7_2_IRQn = 76,
  111. SERCOM7_3_IRQn = 77,
  112. USB_0_IRQn = 80,
  113. USB_1_IRQn = 81,
  114. USB_2_IRQn = 82,
  115. USB_3_IRQn = 83,
  116. TCC0_0_IRQn = 85,
  117. TCC0_1_IRQn = 86,
  118. TCC0_2_IRQn = 87,
  119. TCC0_3_IRQn = 88,
  120. TCC0_4_IRQn = 89,
  121. TCC0_5_IRQn = 90,
  122. TCC0_6_IRQn = 91,
  123. TCC1_0_IRQn = 92,
  124. TCC1_1_IRQn = 93,
  125. TCC1_2_IRQn = 94,
  126. TCC1_3_IRQn = 95,
  127. TCC1_4_IRQn = 96,
  128. TCC2_0_IRQn = 97,
  129. TCC2_1_IRQn = 98,
  130. TCC2_2_IRQn = 99,
  131. TCC2_3_IRQn = 100,
  132. TCC3_0_IRQn = 101,
  133. TCC3_1_IRQn = 102,
  134. TCC3_2_IRQn = 103,
  135. TCC4_0_IRQn = 104,
  136. TCC4_1_IRQn = 105,
  137. TCC4_2_IRQn = 106,
  138. TC0_IRQn = 107,
  139. TC1_IRQn = 108,
  140. TC2_IRQn = 109,
  141. TC3_IRQn = 110,
  142. TC4_IRQn = 111,
  143. TC5_IRQn = 112,
  144. TC6_IRQn = 113,
  145. TC7_IRQn = 114,
  146. PDEC_0_IRQn = 115,
  147. PDEC_1_IRQn = 116,
  148. PDEC_2_IRQn = 117,
  149. ADC0_0_IRQn = 118,
  150. ADC0_1_IRQn = 119,
  151. ADC1_0_IRQn = 120,
  152. ADC1_1_IRQn = 121,
  153. AC_IRQn = 122,
  154. DAC_0_IRQn = 123,
  155. DAC_1_IRQn = 124,
  156. DAC_2_IRQn = 125,
  157. DAC_3_IRQn = 126,
  158. DAC_4_IRQn = 127,
  159. I2S_IRQn = 128,
  160. PCC_IRQn = 129,
  161. AES_IRQn = 130,
  162. TRNG_IRQn = 131,
  163. ICM_IRQn = 132,
  164. PUKCC_IRQn = 133,
  165. QSPI_IRQn = 134,
  166. SDHC0_IRQn = 135,
  167. SDHC1_IRQn = 136
  168. );
  169. TAC_Registers = record
  170. CTRLA : byte; //0000 Control A
  171. CTRLB : byte; //0001 Control B
  172. EVCTRL : word; //0002 Event Control
  173. INTENCLR : byte; //0004 Interrupt Enable Clear
  174. INTENSET : byte; //0005 Interrupt Enable Set
  175. INTFLAG : byte; //0006 Interrupt Flag Status and Clear
  176. STATUSA : byte; //0007 Status A
  177. STATUSB : byte; //0008 Status B
  178. DBGCTRL : byte; //0009 Debug Control
  179. WINCTRL : byte; //000A Window Control
  180. RESERVED0 : byte;
  181. SCALER : array[0..1] of byte; //000C Scaler n
  182. RESERVED1 : word;
  183. COMPCTRL : array[0..1] of longWord; //0010 Comparator Control n
  184. RESERVED2 : array[1..8] of byte;
  185. SYNCBUSY : longWord; //0020 Synchronization Busy
  186. CALIB : word; //0024 Calibration
  187. end;
  188. TADC_Registers = record
  189. CTRLA : word; //0000 Control A
  190. EVCTRL : byte; //0002 Event Control
  191. DBGCTRL : byte; //0003 Debug Control
  192. INPUTCTRL : word; //0004 Input Control
  193. CTRLB : word; //0006 Control B
  194. REFCTRL : byte; //0008 Reference Control
  195. RESERVED0 : byte;
  196. AVGCTRL : byte; //000A Average Control
  197. SAMPCTRL : byte; //000B Sample Time Control
  198. WINLT : word; //000C Window Monitor Lower Threshold
  199. WINUT : word; //000E Window Monitor Upper Threshold
  200. GAINCORR : word; //0010 Gain Correction
  201. OFFSETCORR : word; //0012 Offset Correction
  202. SWTRIG : byte; //0014 Software Trigger
  203. RESERVED1 : array[1..23] of byte;
  204. INTENCLR : byte; //002C Interrupt Enable Clear
  205. INTENSET : byte; //002D Interrupt Enable Set
  206. INTFLAG : byte; //002E Interrupt Flag Status and Clear
  207. STATUS : byte; //002F Status
  208. SYNCBUSY : longWord; //0030 Synchronization Busy
  209. DSEQDATA : longWord; //0034 DMA Sequencial Data
  210. DSEQCTRL : longWord; //0038 DMA Sequential Control
  211. DSEQSTAT : longWord; //003C DMA Sequencial Status
  212. RESULT : word; //0040 Result Conversion Value
  213. RESERVED2 : word;
  214. RESS : word; //0044 Last Sample Result
  215. RESERVED3 : word;
  216. CALIB : word; //0048 Calibration
  217. end;
  218. TAES_Registers = record
  219. CTRLA : longWord; //0000 Control A
  220. CTRLB : byte; //0004 Control B
  221. INTENCLR : byte; //0005 Interrupt Enable Clear
  222. INTENSET : byte; //0006 Interrupt Enable Set
  223. INTFLAG : byte; //0007 Interrupt Flag Status
  224. DATABUFPTR : byte; //0008 Data buffer pointer
  225. DBGCTRL : byte; //0009 Debug control
  226. RESERVED0 : word;
  227. KEYWORD : array[0..7] of longWord; //000C Keyword n
  228. RESERVED1 : array[1..12] of byte;
  229. INDATA : longWord; //0038 Indata
  230. INTVECTV : array[0..3] of longWord; //003C Initialisation Vector n
  231. RESERVED2 : array[1..16] of byte;
  232. HASHKEY : array[0..3] of longWord; //005C Hash key n
  233. GHASH : array[0..3] of longWord; //006C Galois Hash n
  234. RESERVED3 : longWord;
  235. CIPLEN : longWord; //0080 Cipher Length
  236. RANDSEED : longWord; //0084 Random Seed
  237. end;
  238. TCCL_Registers = record
  239. CTRL : byte; //0000 Control
  240. RESERVED0 : array[1..3] of byte;
  241. SEQCTRL : array[0..1] of byte; //0004 SEQ Control x
  242. RESERVED1 : word;
  243. LUTCTRL : array[0..3] of longWord; //0008 LUT Control x
  244. end;
  245. TCMCC_Registers = record
  246. &TYPE : longWord; //0000 Cache Type Register
  247. CFG : longWord; //0004 Cache Configuration Register
  248. CTRL : longWord; //0008 Cache Control Register
  249. SR : longWord; //000C Cache Status Register
  250. LCKWAY : longWord; //0010 Cache Lock per Way Register
  251. RESERVED0 : array[1..12] of byte;
  252. MAINT0 : longWord; //0020 Cache Maintenance Register 0
  253. MAINT1 : longWord; //0024 Cache Maintenance Register 1
  254. MCFG : longWord; //0028 Cache Monitor Configuration Register
  255. MEN : longWord; //002C Cache Monitor Enable Register
  256. MCTRL : longWord; //0030 Cache Monitor Control Register
  257. MSR : longWord; //0034 Cache Monitor Status Register
  258. end;
  259. TDAC_Registers = record
  260. CTRLA : byte; //0000 Control A
  261. CTRLB : byte; //0001 Control B
  262. EVCTRL : byte; //0002 Event Control
  263. RESERVED0 : byte;
  264. INTENCLR : byte; //0004 Interrupt Enable Clear
  265. INTENSET : byte; //0005 Interrupt Enable Set
  266. INTFLAG : byte; //0006 Interrupt Flag Status and Clear
  267. STATUS : byte; //0007 Status
  268. SYNCBUSY : longWord; //0008 Synchronization Busy
  269. DACCTRL : array[0..1] of word; //000C DAC n Control
  270. DATA : array[0..1] of word; //0010 DAC n Data
  271. DATABUF : array[0..1] of word; //0014 DAC n Data Buffer
  272. DBGCTRL : byte; //0018 Debug Control
  273. RESERVED1 : array[1..3] of byte;
  274. RESULT : array[0..1] of word; //001C Filter Result
  275. end;
  276. TDMAC_CHANNEL_Registers = record
  277. CHCTRLA : longWord; //0000 Channel n Control A
  278. CHCTRLB : byte; //0004 Channel n Control B
  279. CHPRILVL : byte; //0005 Channel n Priority Level
  280. CHEVCTRL : byte; //0006 Channel n Event Control
  281. RESERVED0 : array[1..5] of byte;
  282. CHINTENCLR : byte; //000C Channel n Interrupt Enable Clear
  283. CHINTENSET : byte; //000D Channel n Interrupt Enable Set
  284. CHINTFLAG : byte; //000E Channel n Interrupt Flag Status and Clear
  285. CHSTATUS : byte; //000F Channel n Status
  286. end;
  287. TDMAC_Registers = record
  288. CTRL : word; //0000 Control
  289. CRCCTRL : word; //0002 CRC Control
  290. CRCDATAIN : longWord; //0004 CRC Data Input
  291. CRCCHKSUM : longWord; //0008 CRC Checksum
  292. CRCSTATUS : byte; //000C CRC Status
  293. DBGCTRL : byte; //000D Debug Control
  294. RESERVED0 : word;
  295. SWTRIGCTRL : longWord; //0010 Software Trigger Control
  296. PRICTRL0 : longWord; //0014 Priority Control 0
  297. RESERVED1 : array[1..8] of byte;
  298. INTPEND : word; //0020 Interrupt Pending
  299. RESERVED2 : word;
  300. INTSTATUS : longWord; //0024 Interrupt Status
  301. BUSYCH : longWord; //0028 Busy Channels
  302. PENDCH : longWord; //002C Pending Channels
  303. ACTIVE : longWord; //0030 Active Channel and Levels
  304. BASEADDR : longWord; //0034 Descriptor Memory Section Base Address
  305. WRBADDR : longWord; //0038 Write-Back Memory Section Base Address
  306. RESERVED3 : longWord;
  307. CHANNEL : array[0..31] of TDMAC_CHANNEL_Registers; //0040
  308. end;
  309. TDMAC_DESCRIPTOR_Registers = record
  310. BTCTRL : word; //0000 Block Transfer Control
  311. BTCNT : word; //0002 Block Transfer Count
  312. SRCADDR : longWord; //0004 Block Transfer Source Address
  313. DSTADDR : longWord; //0008 Block Transfer Destination Address
  314. DESCADDR : longWord; //000C Next Descriptor Address
  315. end;
  316. TDSU_Registers = record
  317. CTRL : byte; //0000 Control
  318. STATUSA : byte; //0001 Status A
  319. STATUSB : byte; //0002 Status B
  320. RESERVED0 : byte;
  321. ADDR : longWord; //0004 Address
  322. LENGTH : longWord; //0008 Length
  323. DATA : longWord; //000C Data
  324. DCC : array[0..1] of longWord; //0010 Debug Communication Channel n
  325. DID : longWord; //0018 Device Identification
  326. CFG : longWord; //001C Configuration
  327. RESERVED1 : array[1..208] of byte;
  328. DCFG : array[0..1] of longWord; //00F0 Device Configuration
  329. RESERVED2 : array[1..3848] of byte;
  330. ENTRY0 : longWord; //1000 CoreSight ROM Table Entry 0
  331. ENTRY1 : longWord; //1004 CoreSight ROM Table Entry 1
  332. &END : longWord; //1008 CoreSight ROM Table End
  333. RESERVED3 : array[1..4032] of byte;
  334. MEMTYPE : longWord; //1FCC CoreSight ROM Table Memory Type
  335. PID4 : longWord; //1FD0 Peripheral Identification 4
  336. PID5 : longWord; //1FD4 Peripheral Identification 5
  337. PID6 : longWord; //1FD8 Peripheral Identification 6
  338. PID7 : longWord; //1FDC Peripheral Identification 7
  339. PID0 : longWord; //1FE0 Peripheral Identification 0
  340. PID1 : longWord; //1FE4 Peripheral Identification 1
  341. PID2 : longWord; //1FE8 Peripheral Identification 2
  342. PID3 : longWord; //1FEC Peripheral Identification 3
  343. CID0 : longWord; //1FF0 Component Identification 0
  344. CID1 : longWord; //1FF4 Component Identification 1
  345. CID2 : longWord; //1FF8 Component Identification 2
  346. CID3 : longWord; //1FFC Component Identification 3
  347. end;
  348. TEIC_Registers = record
  349. CTRLA : byte; //0000 Control A
  350. NMICTRL : byte; //0001 Non-Maskable Interrupt Control
  351. NMIFLAG : word; //0002 Non-Maskable Interrupt Flag Status and Clear
  352. SYNCBUSY : longWord; //0004 Synchronization Busy
  353. EVCTRL : longWord; //0008 Event Control
  354. INTENCLR : longWord; //000C Interrupt Enable Clear
  355. INTENSET : longWord; //0010 Interrupt Enable Set
  356. INTFLAG : longWord; //0014 Interrupt Flag Status and Clear
  357. ASYNCH : longWord; //0018 External Interrupt Asynchronous Mode
  358. CONFIG : array[0..1] of longWord; //001C External Interrupt Sense Configuration
  359. RESERVED0 : array[1..12] of byte;
  360. DEBOUNCEN : longWord; //0030 Debouncer Enable
  361. DPRESCALER : longWord; //0034 Debouncer Prescaler
  362. PINSTATE : longWord; //0038 Pin State
  363. end;
  364. TEVSYS_CHANNEL_Registers = record
  365. CHANNEL : longWord; //0000 Channel n Control
  366. CHINTENCLR : byte; //0004 Channel n Interrupt Enable Clear
  367. CHINTENSET : byte; //0005 Channel n Interrupt Enable Set
  368. CHINTFLAG : byte; //0006 Channel n Interrupt Flag Status and Clear
  369. CHSTATUS : byte; //0007 Channel n Status
  370. end;
  371. TEVSYS_Registers = record
  372. CTRLA : byte; //0000 Control
  373. RESERVED0 : array[1..3] of byte;
  374. SWEVT : longWord; //0004 Software Event
  375. PRICTRL : byte; //0008 Priority Control
  376. RESERVED1 : array[1..7] of byte;
  377. INTPEND : word; //0010 Channel Pending Interrupt
  378. RESERVED2 : word;
  379. INTSTATUS : longWord; //0014 Interrupt Status
  380. BUSYCH : longWord; //0018 Busy Channels
  381. READYUSR : longWord; //001C Ready Users
  382. CHANNEL : array[0..31] of TEVSYS_CHANNEL_Registers; //0020
  383. USER : array[0..66] of longWord; //0120 User Multiplexer n
  384. end;
  385. TFREQM_Registers = record
  386. CTRLA : byte; //0000 Control A Register
  387. CTRLB : byte; //0001 Control B Register
  388. CFGA : word; //0002 Config A register
  389. RESERVED0 : longWord;
  390. INTENCLR : byte; //0008 Interrupt Enable Clear Register
  391. INTENSET : byte; //0009 Interrupt Enable Set Register
  392. INTFLAG : byte; //000A Interrupt Flag Register
  393. STATUS : byte; //000B Status Register
  394. SYNCBUSY : longWord; //000C Synchronization Busy Register
  395. VALUE : longWord; //0010 Count Value Register
  396. end;
  397. TGCLK_Registers = record
  398. CTRLA : byte; //0000 Control
  399. RESERVED0 : array[1..3] of byte;
  400. SYNCBUSY : longWord; //0004 Synchronization Busy
  401. RESERVED1 : array[1..24] of byte;
  402. GENCTRL : array[0..11] of longWord; //0020 Generic Clock Generator Control
  403. RESERVED2 : array[1..48] of byte;
  404. PCHCTRL : array[0..47] of longWord; //0080 Peripheral Clock Control
  405. end;
  406. THMATRIXB_PRS_Registers = record
  407. PRAS : longWord; //0000 Priority A for Slave
  408. PRBS : longWord; //0004 Priority B for Slave
  409. end;
  410. THMATRIXB_Registers = record
  411. PRS : array[0..15] of THMATRIXB_PRS_Registers; //0080
  412. end;
  413. TICM_Registers = record
  414. CFG : longWord; //0000 Configuration
  415. CTRL : longWord; //0004 Control
  416. SR : longWord; //0008 Status
  417. RESERVED0 : longWord;
  418. IER : longWord; //0010 Interrupt Enable
  419. IDR : longWord; //0014 Interrupt Disable
  420. IMR : longWord; //0018 Interrupt Mask
  421. ISR : longWord; //001C Interrupt Status
  422. UASR : longWord; //0020 Undefined Access Status
  423. RESERVED1 : array[1..12] of byte;
  424. DSCR : longWord; //0030 Region Descriptor Area Start Address
  425. HASH : longWord; //0034 Region Hash Area Start Address
  426. UIHVAL : array[0..7] of longWord; //0038 User Initial Hash Value n
  427. end;
  428. TICM_DESCRIPTOR_Registers = record
  429. RADDR : longWord; //0000 Region Start Address
  430. RCFG : longWord; //0004 Region Configuration
  431. RCTRL : longWord; //0008 Region Control
  432. RNEXT : longWord; //000C Region Next Address
  433. end;
  434. TI2S_Registers = record
  435. CTRLA : byte; //0000 Control A
  436. RESERVED0 : array[1..3] of byte;
  437. CLKCTRL : array[0..1] of longWord; //0004 Clock Unit n Control
  438. INTENCLR : word; //000C Interrupt Enable Clear
  439. RESERVED1 : word;
  440. INTENSET : word; //0010 Interrupt Enable Set
  441. RESERVED2 : word;
  442. INTFLAG : word; //0014 Interrupt Flag Status and Clear
  443. RESERVED3 : word;
  444. SYNCBUSY : word; //0018 Synchronization Status
  445. RESERVED4 : array[1..6] of byte;
  446. TXCTRL : longWord; //0020 Tx Serializer Control
  447. RXCTRL : longWord; //0024 Rx Serializer Control
  448. RESERVED5 : array[1..8] of byte;
  449. TXDATA : longWord; //0030 Tx Data
  450. RXDATA : longWord; //0034 Rx Data
  451. end;
  452. TMCLK_Registers = record
  453. INTENCLR : byte; //0001 Interrupt Enable Clear
  454. INTENSET : byte; //0002 Interrupt Enable Set
  455. INTFLAG : byte; //0003 Interrupt Flag Status and Clear
  456. HSDIV : byte; //0004 HS Clock Division
  457. CPUDIV : byte; //0005 CPU Clock Division
  458. RESERVED0 : array[1..10] of byte;
  459. AHBMASK : longWord; //0010 AHB Mask
  460. APBAMASK : longWord; //0014 APBA Mask
  461. APBBMASK : longWord; //0018 APBB Mask
  462. APBCMASK : longWord; //001C APBC Mask
  463. APBDMASK : longWord; //0020 APBD Mask
  464. end;
  465. TNVMCTRL_Registers = record
  466. CTRLA : word; //0000 Control A
  467. RESERVED0 : word;
  468. CTRLB : word; //0004 Control B
  469. RESERVED1 : word;
  470. PARAM : longWord; //0008 NVM Parameter
  471. INTENCLR : word; //000C Interrupt Enable Clear
  472. INTENSET : word; //000E Interrupt Enable Set
  473. INTFLAG : word; //0010 Interrupt Flag Status and Clear
  474. STATUS : word; //0012 Status
  475. ADDR : longWord; //0014 Address
  476. RUNLOCK : longWord; //0018 Lock Section
  477. PBLDATA : array[0..1] of longWord; //001C Page Buffer Load Data x
  478. ECCERR : longWord; //0024 ECC Error Status Register
  479. DBGCTRL : byte; //0028 Debug Control
  480. RESERVED2 : byte;
  481. SEECFG : byte; //002A SmartEEPROM Configuration Register
  482. RESERVED3 : byte;
  483. SEESTAT : longWord; //002C SmartEEPROM Status Register
  484. end;
  485. TSW0_FUSES_Registers = record
  486. SW0_WORD_0 : longWord; //0000 SW0 Page Word 0
  487. SW0_WORD_1 : longWord; //0004 SW0 Page Word 1
  488. end;
  489. TTEMP_LOG_FUSES_Registers = record
  490. TEMP_LOG_WORD_0 : longWord; //0000 TEMP_LOG Page Word 0
  491. TEMP_LOG_WORD_1 : longWord; //0004 TEMP_LOG Page Word 1
  492. TEMP_LOG_WORD_2 : longWord; //0008 TEMP_LOG Page Word 2
  493. end;
  494. TUSER_FUSES_Registers = record
  495. USER_WORD_0 : longWord; //0000 USER Page Word 0
  496. USER_WORD_1 : longWord; //0004 USER Page Word 1
  497. USER_WORD_2 : longWord; //0008 USER Page Word 2
  498. end;
  499. TOSCCTRL_DPLL_Registers = record
  500. DPLLCTRLA : byte; //0000 DPLL Control A
  501. RESERVED0 : array[1..3] of byte;
  502. DPLLRATIO : longWord; //0004 DPLL Ratio Control
  503. DPLLCTRLB : longWord; //0008 DPLL Control B
  504. DPLLSYNCBUSY : longWord; //000C DPLL Synchronization Busy
  505. DPLLSTATUS : longWord; //0010 DPLL Status
  506. end;
  507. TOSCCTRL_Registers = record
  508. EVCTRL : byte; //0000 Event Control
  509. RESERVED0 : array[1..3] of byte;
  510. INTENCLR : longWord; //0004 Interrupt Enable Clear
  511. INTENSET : longWord; //0008 Interrupt Enable Set
  512. INTFLAG : longWord; //000C Interrupt Flag Status and Clear
  513. STATUS : longWord; //0010 Status
  514. XOSCCTRL : array[0..1] of longWord; //0014 External Multipurpose Crystal Oscillator Control
  515. DFLLCTRLA : byte; //001C DFLL48M Control A
  516. RESERVED1 : array[1..3] of byte;
  517. DFLLCTRLB : byte; //0020 DFLL48M Control B
  518. RESERVED2 : array[1..3] of byte;
  519. DFLLVAL : longWord; //0024 DFLL48M Value
  520. DFLLMUL : longWord; //0028 DFLL48M Multiplier
  521. DFLLSYNC : byte; //002C DFLL48M Synchronization
  522. RESERVED3 : array[1..3] of byte;
  523. DPLL : array[0..1] of TOSCCTRL_DPLL_Registers; //0030
  524. end;
  525. TOSC32KCTRL_Registers = record
  526. INTENCLR : longWord; //0000 Interrupt Enable Clear
  527. INTENSET : longWord; //0004 Interrupt Enable Set
  528. INTFLAG : longWord; //0008 Interrupt Flag Status and Clear
  529. STATUS : longWord; //000C Power and Clocks Status
  530. RTCCTRL : byte; //0010 RTC Clock Selection
  531. RESERVED0 : array[1..3] of byte;
  532. XOSC32K : word; //0014 32kHz External Crystal Oscillator (XOSC32K) Control
  533. CFDCTRL : byte; //0016 Clock Failure Detector Control
  534. EVCTRL : byte; //0017 Event Control
  535. RESERVED1 : longWord;
  536. OSCULP32K : longWord; //001C 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
  537. end;
  538. TPAC_Registers = record
  539. WRCTRL : longWord; //0000 Write control
  540. EVCTRL : byte; //0004 Event control
  541. RESERVED0 : array[1..3] of byte;
  542. INTENCLR : byte; //0008 Interrupt enable clear
  543. INTENSET : byte; //0009 Interrupt enable set
  544. RESERVED1 : array[1..6] of byte;
  545. INTFLAGAHB : longWord; //0010 Bridge interrupt flag status
  546. INTFLAGA : longWord; //0014 Peripheral interrupt flag status - Bridge A
  547. INTFLAGB : longWord; //0018 Peripheral interrupt flag status - Bridge B
  548. INTFLAGC : longWord; //001C Peripheral interrupt flag status - Bridge C
  549. INTFLAGD : longWord; //0020 Peripheral interrupt flag status - Bridge D
  550. RESERVED2 : array[1..16] of byte;
  551. STATUSA : longWord; //0034 Peripheral write protection status - Bridge A
  552. STATUSB : longWord; //0038 Peripheral write protection status - Bridge B
  553. STATUSC : longWord; //003C Peripheral write protection status - Bridge C
  554. STATUSD : longWord; //0040 Peripheral write protection status - Bridge D
  555. end;
  556. TPCC_Registers = record
  557. MR : longWord; //0000 Mode Register
  558. IER : longWord; //0004 Interrupt Enable Register
  559. IDR : longWord; //0008 Interrupt Disable Register
  560. IMR : longWord; //000C Interrupt Mask Register
  561. ISR : longWord; //0010 Interrupt Status Register
  562. RHR : longWord; //0014 Reception Holding Register
  563. RESERVED0 : array[1..200] of byte;
  564. WPMR : longWord; //00E0 Write Protection Mode Register
  565. WPSR : longWord; //00E4 Write Protection Status Register
  566. end;
  567. TPDEC_Registers = record
  568. CTRLA : longWord; //0000 Control A
  569. CTRLBCLR : byte; //0004 Control B Clear
  570. CTRLBSET : byte; //0005 Control B Set
  571. EVCTRL : word; //0006 Event Control
  572. INTENCLR : byte; //0008 Interrupt Enable Clear
  573. INTENSET : byte; //0009 Interrupt Enable Set
  574. INTFLAG : byte; //000A Interrupt Flag Status and Clear
  575. RESERVED0 : byte;
  576. STATUS : word; //000C Status
  577. RESERVED1 : byte;
  578. DBGCTRL : byte; //000F Debug Control
  579. SYNCBUSY : longWord; //0010 Synchronization Status
  580. PRESC : byte; //0014 Prescaler Value
  581. FILTER : byte; //0015 Filter Value
  582. RESERVED2 : word;
  583. PRESCBUF : byte; //0018 Prescaler Buffer Value
  584. FILTERBUF : byte; //0019 Filter Buffer Value
  585. RESERVED3 : word;
  586. COUNT : longWord; //001C Counter Value
  587. CC : array[0..1] of longWord; //0020 Channel n Compare Value
  588. RESERVED4 : array[1..8] of byte;
  589. CCBUF : array[0..1] of longWord; //0030 Channel Compare Buffer Value
  590. end;
  591. TPM_Registers = record
  592. CTRLA : byte; //0000 Control A
  593. SLEEPCFG : byte; //0001 Sleep Configuration
  594. RESERVED0 : word;
  595. INTENCLR : byte; //0004 Interrupt Enable Clear
  596. INTENSET : byte; //0005 Interrupt Enable Set
  597. INTFLAG : byte; //0006 Interrupt Flag Status and Clear
  598. RESERVED1 : byte;
  599. STDBYCFG : byte; //0008 Standby Configuration
  600. HIBCFG : byte; //0009 Hibernate Configuration
  601. BKUPCFG : byte; //000A Backup Configuration
  602. RESERVED2 : array[1..7] of byte;
  603. PWSAKDLY : byte; //0012 Power Switch Acknowledge Delay
  604. end;
  605. TPORT_GROUP_Registers = record
  606. DIR : longWord; //0000 Data Direction
  607. DIRCLR : longWord; //0004 Data Direction Clear
  608. DIRSET : longWord; //0008 Data Direction Set
  609. DIRTGL : longWord; //000C Data Direction Toggle
  610. &OUT : longWord; //0010 Data Output Value
  611. OUTCLR : longWord; //0014 Data Output Value Clear
  612. OUTSET : longWord; //0018 Data Output Value Set
  613. OUTTGL : longWord; //001C Data Output Value Toggle
  614. &IN : longWord; //0020 Data Input Value
  615. CTRL : longWord; //0024 Control
  616. WRCONFIG : longWord; //0028 Write Configuration
  617. EVCTRL : longWord; //002C Event Input Control
  618. PMUX : array[0..15] of byte; //0030 Peripheral Multiplexing
  619. PINCFG : array[0..31] of byte; //0040 Pin Configuration
  620. Res : array[$60..$7F] of byte;
  621. end;
  622. TPORT_Registers = record
  623. GROUP : array[0..3] of TPORT_GROUP_Registers; //0000
  624. end;
  625. TPUKCC_Registers = record
  626. end;
  627. TQSPI_Registers = record
  628. CTRLA : longWord; //0000 Control A
  629. CTRLB : longWord; //0004 Control B
  630. BAUD : longWord; //0008 Baud Rate
  631. RXDATA : longWord; //000C Receive Data
  632. TXDATA : longWord; //0010 Transmit Data
  633. INTENCLR : longWord; //0014 Interrupt Enable Clear
  634. INTENSET : longWord; //0018 Interrupt Enable Set
  635. INTFLAG : longWord; //001C Interrupt Flag Status and Clear
  636. STATUS : longWord; //0020 Status Register
  637. RESERVED0 : array[1..12] of byte;
  638. INSTRADDR : longWord; //0030 Instruction Address
  639. INSTRCTRL : longWord; //0034 Instruction Code
  640. INSTRFRAME : longWord; //0038 Instruction Frame
  641. RESERVED1 : longWord;
  642. SCRAMBCTRL : longWord; //0040 Scrambling Mode
  643. SCRAMBKEY : longWord; //0044 Scrambling Key
  644. end;
  645. TRAMECC_Registers = record
  646. INTENCLR : byte; //0000 Interrupt Enable Clear
  647. INTENSET : byte; //0001 Interrupt Enable Set
  648. INTFLAG : byte; //0002 Interrupt Flag
  649. STATUS : byte; //0003 Status
  650. ERRADDR : longWord; //0004 Error Address
  651. RESERVED0 : array[1..7] of byte;
  652. DBGCTRL : byte; //000F Debug Control
  653. end;
  654. TRSTC_Registers = record
  655. RCAUSE : byte; //0000 Reset Cause
  656. RESERVED0 : byte;
  657. BKUPEXIT : byte; //0002 Backup Exit Source
  658. end;
  659. TRTCMODE0_Registers = record
  660. CTRLA : word; //0000 MODE0 Control A
  661. CTRLB : word; //0002 MODE0 Control B
  662. EVCTRL : longWord; //0004 MODE0 Event Control
  663. INTENCLR : word; //0008 MODE0 Interrupt Enable Clear
  664. INTENSET : word; //000A MODE0 Interrupt Enable Set
  665. INTFLAG : word; //000C MODE0 Interrupt Flag Status and Clear
  666. DBGCTRL : byte; //000E Debug Control
  667. RESERVED0 : byte;
  668. SYNCBUSY : longWord; //0010 MODE0 Synchronization Busy Status
  669. FREQCORR : byte; //0014 Frequency Correction
  670. RESERVED1 : array[1..3] of byte;
  671. COUNT : longWord; //0018 MODE0 Counter Value
  672. RESERVED2 : longWord;
  673. COMP : array[0..1] of longWord; //0020 MODE0 Compare n Value
  674. RESERVED3 : array[1..24] of byte;
  675. GP : array[0..3] of longWord; //0040 General Purpose
  676. RESERVED4 : array[1..16] of byte;
  677. TAMPCTRL : longWord; //0060 Tamper Control
  678. TIMESTAMP : longWord; //0064 MODE0 Timestamp
  679. TAMPID : longWord; //0068 Tamper ID
  680. RESERVED5 : array[1..20] of byte;
  681. BKUP : array[0..7] of longWord; //0080 Backup
  682. end;
  683. TRTCMODE1_Registers = record
  684. CTRLA : word; //0000 MODE1 Control A
  685. CTRLB : word; //0002 MODE1 Control B
  686. EVCTRL : longWord; //0004 MODE1 Event Control
  687. INTENCLR : word; //0008 MODE1 Interrupt Enable Clear
  688. INTENSET : word; //000A MODE1 Interrupt Enable Set
  689. INTFLAG : word; //000C MODE1 Interrupt Flag Status and Clear
  690. DBGCTRL : byte; //000E Debug Control
  691. RESERVED0 : byte;
  692. SYNCBUSY : longWord; //0010 MODE1 Synchronization Busy Status
  693. FREQCORR : byte; //0014 Frequency Correction
  694. RESERVED1 : array[1..3] of byte;
  695. COUNT : word; //0018 MODE1 Counter Value
  696. RESERVED2 : word;
  697. PER : word; //001C MODE1 Counter Period
  698. RESERVED3 : word;
  699. COMP : array[0..3] of word; //0020 MODE1 Compare n Value
  700. RESERVED4 : array[1..24] of byte;
  701. GP : array[0..3] of longWord; //0040 General Purpose
  702. RESERVED5 : array[1..16] of byte;
  703. TAMPCTRL : longWord; //0060 Tamper Control
  704. TIMESTAMP : longWord; //0064 MODE1 Timestamp
  705. TAMPID : longWord; //0068 Tamper ID
  706. RESERVED6 : array[1..20] of byte;
  707. BKUP : array[0..7] of longWord; //0080 Backup
  708. end;
  709. TRTCMODE2_Registers = record
  710. CTRLA : word; //0000 MODE2 Control A
  711. CTRLB : word; //0002 MODE2 Control B
  712. EVCTRL : longWord; //0004 MODE2 Event Control
  713. INTENCLR : word; //0008 MODE2 Interrupt Enable Clear
  714. INTENSET : word; //000A MODE2 Interrupt Enable Set
  715. INTFLAG : word; //000C MODE2 Interrupt Flag Status and Clear
  716. DBGCTRL : byte; //000E Debug Control
  717. RESERVED0 : byte;
  718. SYNCBUSY : longWord; //0010 MODE2 Synchronization Busy Status
  719. FREQCORR : byte; //0014 Frequency Correction
  720. RESERVED1 : array[1..3] of byte;
  721. CLOCK : longWord; //0018 MODE2 Clock Value
  722. RESERVED2 : longWord;
  723. ALARM0 : longWord; //0020 MODE2_ALARM Alarm n Value
  724. MASK0 : byte; //0024 MODE2_ALARM Alarm n Mask
  725. RESERVED3 : array[1..3] of byte;
  726. ALARM1 : longWord; //0028 MODE2_ALARM Alarm n Value
  727. MASK1 : byte; //002C MODE2_ALARM Alarm n Mask
  728. RESERVED4 : array[1..19] of byte;
  729. GP : array[0..3] of longWord; //0040 General Purpose
  730. RESERVED5 : array[1..16] of byte;
  731. TAMPCTRL : longWord; //0060 Tamper Control
  732. TIMESTAMP : longWord; //0064 MODE2 Timestamp
  733. TAMPID : longWord; //0068 Tamper ID
  734. RESERVED6 : array[1..20] of byte;
  735. BKUP : array[0..7] of longWord; //0080 Backup
  736. end;
  737. TSDHC_Registers = record
  738. SSAR : longWord; //0000 SDMA System Address / Argument 2
  739. BSR : word; //0004 Block Size
  740. BCR : word; //0006 Block Count
  741. ARG1R : longWord; //0008 Argument 1
  742. TMR : word; //000C Transfer Mode
  743. CR : word; //000E Command
  744. RR : array[0..3] of longWord; //0010 Response
  745. BDPR : longWord; //0020 Buffer Data Port
  746. PSR : longWord; //0024 Present State
  747. HC1R : byte; //0028 Host Control 1
  748. PCR : byte; //0029 Power Control
  749. BGCR : byte; //002A Block Gap Control
  750. WCR : byte; //002B Wakeup Control
  751. CCR : word; //002C Clock Control
  752. TCR : byte; //002E Timeout Control
  753. SRR : byte; //002F Software Reset
  754. NISTR : word; //0030 Normal Interrupt Status
  755. EISTR : word; //0032 Error Interrupt Status
  756. NISTER : word; //0034 Normal Interrupt Status Enable
  757. EISTER : word; //0036 Error Interrupt Status Enable
  758. NISIER : word; //0038 Normal Interrupt Signal Enable
  759. EISIER : word; //003A Error Interrupt Signal Enable
  760. ACESR : word; //003C Auto CMD Error Status
  761. HC2R : word; //003E Host Control 2
  762. CA0R : longWord; //0040 Capabilities 0
  763. CA1R : longWord; //0044 Capabilities 1
  764. MCCAR : longWord; //0048 Maximum Current Capabilities
  765. RESERVED0 : longWord;
  766. FERACES : word; //0050 Force Event for Auto CMD Error Status
  767. FEREIS : word; //0052 Force Event for Error Interrupt Status
  768. AESR : byte; //0054 ADMA Error Status
  769. RESERVED1 : array[1..3] of byte;
  770. ASAR : longWord; //0058 ADMA System Address n
  771. RESERVED2 : longWord;
  772. PVR : array[0..7] of word; //0060 Preset Value n
  773. RESERVED3 : array[1..140] of byte;
  774. SISR : word; //00FC Slot Interrupt Status
  775. HCVR : word; //00FE Host Controller Version
  776. RESERVED4 : array[1..260] of byte;
  777. MC1R : byte; //0204 MMC Control 1
  778. MC2R : byte; //0205 MMC Control 2
  779. RESERVED5 : word;
  780. ACR : longWord; //0208 AHB Control
  781. CC2R : longWord; //020C Clock Control 2
  782. RESERVED6 : array[1..32] of byte;
  783. CACR : longWord; //0230 Capabilities Control
  784. DBGR : byte; //0234 Debug
  785. end;
  786. TSERCOMI2CM_Registers = record
  787. CTRLA : longWord; //0000 I2CM Control A
  788. CTRLB : longWord; //0004 I2CM Control B
  789. CTRLC : longWord; //0008 I2CM Control C
  790. BAUD : longWord; //000C I2CM Baud Rate
  791. RESERVED0 : longWord;
  792. INTENCLR : byte; //0014 I2CM Interrupt Enable Clear
  793. RESERVED1 : byte;
  794. INTENSET : byte; //0016 I2CM Interrupt Enable Set
  795. RESERVED2 : byte;
  796. INTFLAG : byte; //0018 I2CM Interrupt Flag Status and Clear
  797. RESERVED3 : byte;
  798. STATUS : word; //001A I2CM Status
  799. SYNCBUSY : longWord; //001C I2CM Synchronization Busy
  800. RESERVED4 : longWord;
  801. ADDR : longWord; //0024 I2CM Address
  802. DATA : longWord; //0028 I2CM Data
  803. RESERVED5 : longWord;
  804. DBGCTRL : byte; //0030 I2CM Debug Control
  805. end;
  806. TSERCOMI2CS_Registers = record
  807. CTRLA : longWord; //0000 I2CS Control A
  808. CTRLB : longWord; //0004 I2CS Control B
  809. CTRLC : longWord; //0008 I2CS Control C
  810. RESERVED0 : array[1..8] of byte;
  811. INTENCLR : byte; //0014 I2CS Interrupt Enable Clear
  812. RESERVED1 : byte;
  813. INTENSET : byte; //0016 I2CS Interrupt Enable Set
  814. RESERVED2 : byte;
  815. INTFLAG : byte; //0018 I2CS Interrupt Flag Status and Clear
  816. RESERVED3 : byte;
  817. STATUS : word; //001A I2CS Status
  818. SYNCBUSY : longWord; //001C I2CS Synchronization Busy
  819. RESERVED4 : word;
  820. LENGTH : word; //0022 I2CS Length
  821. ADDR : longWord; //0024 I2CS Address
  822. DATA : longWord; //0028 I2CS Data
  823. end;
  824. TSERCOMSPIS_Registers = record
  825. CTRLA : longWord; //0000 SPIS Control A
  826. CTRLB : longWord; //0004 SPIS Control B
  827. CTRLC : longWord; //0008 SPIS Control C
  828. BAUD : byte; //000C SPIS Baud Rate
  829. RESERVED0 : array[1..7] of byte;
  830. INTENCLR : byte; //0014 SPIS Interrupt Enable Clear
  831. RESERVED1 : byte;
  832. INTENSET : byte; //0016 SPIS Interrupt Enable Set
  833. RESERVED2 : byte;
  834. INTFLAG : byte; //0018 SPIS Interrupt Flag Status and Clear
  835. RESERVED3 : byte;
  836. STATUS : word; //001A SPIS Status
  837. SYNCBUSY : longWord; //001C SPIS Synchronization Busy
  838. RESERVED4 : word;
  839. LENGTH : word; //0022 SPIS Length
  840. ADDR : longWord; //0024 SPIS Address
  841. DATA : longWord; //0028 SPIS Data
  842. RESERVED5 : longWord;
  843. DBGCTRL : byte; //0030 SPIS Debug Control
  844. end;
  845. TSERCOMSPIM_Registers = record
  846. CTRLA : longWord; //0000 SPIM Control A
  847. CTRLB : longWord; //0004 SPIM Control B
  848. CTRLC : longWord; //0008 SPIM Control C
  849. BAUD : byte; //000C SPIM Baud Rate
  850. RESERVED0 : array[1..7] of byte;
  851. INTENCLR : byte; //0014 SPIM Interrupt Enable Clear
  852. RESERVED1 : byte;
  853. INTENSET : byte; //0016 SPIM Interrupt Enable Set
  854. RESERVED2 : byte;
  855. INTFLAG : byte; //0018 SPIM Interrupt Flag Status and Clear
  856. RESERVED3 : byte;
  857. STATUS : word; //001A SPIM Status
  858. SYNCBUSY : longWord; //001C SPIM Synchronization Busy
  859. RESERVED4 : word;
  860. LENGTH : word; //0022 SPIM Length
  861. ADDR : longWord; //0024 SPIM Address
  862. DATA : longWord; //0028 SPIM Data
  863. RESERVED5 : longWord;
  864. DBGCTRL : byte; //0030 SPIM Debug Control
  865. end;
  866. TSERCOMUSART_EXT_Registers = record
  867. CTRLA : longWord; //0000 USART_EXT Control A
  868. CTRLB : longWord; //0004 USART_EXT Control B
  869. CTRLC : longWord; //0008 USART_EXT Control C
  870. BAUD : word; //000C USART_EXT Baud Rate
  871. RXPL : byte; //000E USART_EXT Receive Pulse Length
  872. RESERVED0 : array[1..5] of byte;
  873. INTENCLR : byte; //0014 USART_EXT Interrupt Enable Clear
  874. RESERVED1 : byte;
  875. INTENSET : byte; //0016 USART_EXT Interrupt Enable Set
  876. RESERVED2 : byte;
  877. INTFLAG : byte; //0018 USART_EXT Interrupt Flag Status and Clear
  878. RESERVED3 : byte;
  879. STATUS : word; //001A USART_EXT Status
  880. SYNCBUSY : longWord; //001C USART_EXT Synchronization Busy
  881. RXERRCNT : byte; //0020 USART_EXT Receive Error Count
  882. RESERVED4 : byte;
  883. LENGTH : word; //0022 USART_EXT Length
  884. RESERVED5 : longWord;
  885. DATA : longWord; //0028 USART_EXT Data
  886. RESERVED6 : longWord;
  887. DBGCTRL : byte; //0030 USART_EXT Debug Control
  888. end;
  889. TSERCOMUSART_INT_Registers = record
  890. CTRLA : longWord; //0000 USART_INT Control A
  891. CTRLB : longWord; //0004 USART_INT Control B
  892. CTRLC : longWord; //0008 USART_INT Control C
  893. BAUD : word; //000C USART_INT Baud Rate
  894. RXPL : byte; //000E USART_INT Receive Pulse Length
  895. RESERVED0 : array[1..5] of byte;
  896. INTENCLR : byte; //0014 USART_INT Interrupt Enable Clear
  897. RESERVED1 : byte;
  898. INTENSET : byte; //0016 USART_INT Interrupt Enable Set
  899. RESERVED2 : byte;
  900. INTFLAG : byte; //0018 USART_INT Interrupt Flag Status and Clear
  901. RESERVED3 : byte;
  902. STATUS : word; //001A USART_INT Status
  903. SYNCBUSY : longWord; //001C USART_INT Synchronization Busy
  904. RXERRCNT : byte; //0020 USART_INT Receive Error Count
  905. RESERVED4 : byte;
  906. LENGTH : word; //0022 USART_INT Length
  907. RESERVED5 : longWord;
  908. DATA : longWord; //0028 USART_INT Data
  909. RESERVED6 : longWord;
  910. DBGCTRL : byte; //0030 USART_INT Debug Control
  911. end;
  912. TSUPC_Registers = record
  913. INTENCLR : longWord; //0000 Interrupt Enable Clear
  914. INTENSET : longWord; //0004 Interrupt Enable Set
  915. INTFLAG : longWord; //0008 Interrupt Flag Status and Clear
  916. STATUS : longWord; //000C Power and Clocks Status
  917. BOD33 : longWord; //0010 BOD33 Control
  918. RESERVED0 : longWord;
  919. VREG : longWord; //0018 VREG Control
  920. VREF : longWord; //001C VREF Control
  921. BBPS : longWord; //0020 Battery Backup Power Switch
  922. BKOUT : longWord; //0024 Backup Output Control
  923. BKIN : longWord; //0028 Backup Input Control
  924. end;
  925. TTCCOUNT8_Registers = record
  926. CTRLA : longWord; //0000 Control A
  927. CTRLBCLR : byte; //0004 Control B Clear
  928. CTRLBSET : byte; //0005 Control B Set
  929. EVCTRL : word; //0006 Event Control
  930. INTENCLR : byte; //0008 Interrupt Enable Clear
  931. INTENSET : byte; //0009 Interrupt Enable Set
  932. INTFLAG : byte; //000A Interrupt Flag Status and Clear
  933. STATUS : byte; //000B Status
  934. WAVE : byte; //000C Waveform Generation Control
  935. DRVCTRL : byte; //000D Control C
  936. RESERVED0 : byte;
  937. DBGCTRL : byte; //000F Debug Control
  938. SYNCBUSY : longWord; //0010 Synchronization Status
  939. COUNT : byte; //0014 COUNT8 Count
  940. RESERVED1 : array[1..6] of byte;
  941. PER : byte; //001B COUNT8 Period
  942. CC : array[0..1] of byte; //001C COUNT8 Compare and Capture
  943. RESERVED2 : array[1..17] of byte;
  944. PERBUF : byte; //002F COUNT8 Period Buffer
  945. CCBUF : array[0..1] of byte; //0030 COUNT8 Compare and Capture Buffer
  946. end;
  947. TTCCOUNT16_Registers = record
  948. CTRLA : longWord; //0000 Control A
  949. CTRLBCLR : byte; //0004 Control B Clear
  950. CTRLBSET : byte; //0005 Control B Set
  951. EVCTRL : word; //0006 Event Control
  952. INTENCLR : byte; //0008 Interrupt Enable Clear
  953. INTENSET : byte; //0009 Interrupt Enable Set
  954. INTFLAG : byte; //000A Interrupt Flag Status and Clear
  955. STATUS : byte; //000B Status
  956. WAVE : byte; //000C Waveform Generation Control
  957. DRVCTRL : byte; //000D Control C
  958. RESERVED0 : byte;
  959. DBGCTRL : byte; //000F Debug Control
  960. SYNCBUSY : longWord; //0010 Synchronization Status
  961. COUNT : word; //0014 COUNT16 Count
  962. RESERVED1 : array[1..6] of byte;
  963. CC : array[0..1] of word; //001C COUNT16 Compare and Capture
  964. RESERVED2 : array[1..16] of byte;
  965. CCBUF : array[0..1] of word; //0030 COUNT16 Compare and Capture Buffer
  966. end;
  967. TTCCOUNT32_Registers = record
  968. CTRLA : longWord; //0000 Control A
  969. CTRLBCLR : byte; //0004 Control B Clear
  970. CTRLBSET : byte; //0005 Control B Set
  971. EVCTRL : word; //0006 Event Control
  972. INTENCLR : byte; //0008 Interrupt Enable Clear
  973. INTENSET : byte; //0009 Interrupt Enable Set
  974. INTFLAG : byte; //000A Interrupt Flag Status and Clear
  975. STATUS : byte; //000B Status
  976. WAVE : byte; //000C Waveform Generation Control
  977. DRVCTRL : byte; //000D Control C
  978. RESERVED0 : byte;
  979. DBGCTRL : byte; //000F Debug Control
  980. SYNCBUSY : longWord; //0010 Synchronization Status
  981. COUNT : longWord; //0014 COUNT32 Count
  982. RESERVED1 : longWord;
  983. CC : array[0..1] of longWord; //001C COUNT32 Compare and Capture
  984. RESERVED2 : array[1..12] of byte;
  985. CCBUF : array[0..1] of longWord; //0030 COUNT32 Compare and Capture Buffer
  986. end;
  987. TTCC_Registers = record
  988. CTRLA : longWord; //0000 Control A
  989. CTRLBCLR : byte; //0004 Control B Clear
  990. CTRLBSET : byte; //0005 Control B Set
  991. RESERVED0 : word;
  992. SYNCBUSY : longWord; //0008 Synchronization Busy
  993. FCTRLA : longWord; //000C Recoverable Fault A Configuration
  994. FCTRLB : longWord; //0010 Recoverable Fault B Configuration
  995. WEXCTRL : longWord; //0014 Waveform Extension Configuration
  996. DRVCTRL : longWord; //0018 Driver Control
  997. RESERVED1 : word;
  998. DBGCTRL : byte; //001E Debug Control
  999. RESERVED2 : byte;
  1000. EVCTRL : longWord; //0020 Event Control
  1001. INTENCLR : longWord; //0024 Interrupt Enable Clear
  1002. INTENSET : longWord; //0028 Interrupt Enable Set
  1003. INTFLAG : longWord; //002C Interrupt Flag Status and Clear
  1004. STATUS : longWord; //0030 Status
  1005. COUNT : longWord; //0034 Count
  1006. PATT : word; //0038 Pattern
  1007. RESERVED3 : word;
  1008. WAVE : longWord; //003C Waveform Control
  1009. PER : longWord; //0040 Period
  1010. CC : array[0..5] of longWord; //0044 Compare and Capture
  1011. RESERVED4 : array[1..8] of byte;
  1012. PATTBUF : word; //0064 Pattern Buffer
  1013. RESERVED5 : array[1..6] of byte;
  1014. PERBUF : longWord; //006C Period Buffer
  1015. CCBUF : array[0..5] of longWord; //0070 Compare and Capture Buffer
  1016. end;
  1017. TTRNG_Registers = record
  1018. CTRLA : byte; //0000 Control A
  1019. RESERVED0 : array[1..3] of byte;
  1020. EVCTRL : byte; //0004 Event Control
  1021. RESERVED1 : array[1..3] of byte;
  1022. INTENCLR : byte; //0008 Interrupt Enable Clear
  1023. INTENSET : byte; //0009 Interrupt Enable Set
  1024. INTFLAG : byte; //000A Interrupt Flag Status and Clear
  1025. RESERVED2 : array[1..21] of byte;
  1026. DATA : longWord; //0020 Output Data
  1027. end;
  1028. TUSB_DEVICE_DESC_BANK_Registers = record
  1029. ADDR : longWord; //0000 DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer
  1030. PCKSIZE : longWord; //0004 DEVICE_DESC_BANK Endpoint Bank, Packet Size
  1031. EXTREG : word; //0008 DEVICE_DESC_BANK Endpoint Bank, Extended
  1032. STATUS_BK : byte; //000A DEVICE_DESC_BANK Enpoint Bank, Status of Bank
  1033. end;
  1034. TUSB_HOST_DESC_BANK_Registers = record
  1035. ADDR : longWord; //0000 HOST_DESC_BANK Host Bank, Adress of Data Buffer
  1036. PCKSIZE : longWord; //0004 HOST_DESC_BANK Host Bank, Packet Size
  1037. EXTREG : word; //0008 HOST_DESC_BANK Host Bank, Extended
  1038. STATUS_BK : byte; //000A HOST_DESC_BANK Host Bank, Status of Bank
  1039. RESERVED0 : byte;
  1040. CTRL_PIPE : word; //000C HOST_DESC_BANK Host Bank, Host Control Pipe
  1041. STATUS_PIPE : word; //000E HOST_DESC_BANK Host Bank, Host Status Pipe
  1042. end;
  1043. TUSB_DEVICE_ENDPOINT_Registers = record
  1044. EPCFG : byte; //0000 DEVICE_ENDPOINT End Point Configuration
  1045. RESERVED0 : array[1..3] of byte;
  1046. EPSTATUSCLR : byte; //0004 DEVICE_ENDPOINT End Point Pipe Status Clear
  1047. EPSTATUSSET : byte; //0005 DEVICE_ENDPOINT End Point Pipe Status Set
  1048. EPSTATUS : byte; //0006 DEVICE_ENDPOINT End Point Pipe Status
  1049. EPINTFLAG : byte; //0007 DEVICE_ENDPOINT End Point Interrupt Flag
  1050. EPINTENCLR : byte; //0008 DEVICE_ENDPOINT End Point Interrupt Clear Flag
  1051. EPINTENSET : byte; //0009 DEVICE_ENDPOINT End Point Interrupt Set Flag
  1052. end;
  1053. TUSB_HOST_PIPE_Registers = record
  1054. PCFG : byte; //0000 HOST_PIPE End Point Configuration
  1055. RESERVED0 : word;
  1056. BINTERVAL : byte; //0003 HOST_PIPE Bus Access Period of Pipe
  1057. PSTATUSCLR : byte; //0004 HOST_PIPE End Point Pipe Status Clear
  1058. PSTATUSSET : byte; //0005 HOST_PIPE End Point Pipe Status Set
  1059. PSTATUS : byte; //0006 HOST_PIPE End Point Pipe Status
  1060. PINTFLAG : byte; //0007 HOST_PIPE Pipe Interrupt Flag
  1061. PINTENCLR : byte; //0008 HOST_PIPE Pipe Interrupt Flag Clear
  1062. PINTENSET : byte; //0009 HOST_PIPE Pipe Interrupt Flag Set
  1063. end;
  1064. TUSBDEVICE_Registers = record
  1065. CTRLA : byte; //0000 Control A
  1066. RESERVED0 : byte;
  1067. SYNCBUSY : byte; //0002 Synchronization Busy
  1068. QOSCTRL : byte; //0003 USB Quality Of Service
  1069. RESERVED1 : longWord;
  1070. CTRLB : word; //0008 DEVICE Control B
  1071. DADD : byte; //000A DEVICE Device Address
  1072. RESERVED2 : byte;
  1073. STATUS : byte; //000C DEVICE Status
  1074. FSMSTATUS : byte; //000D Finite State Machine Status
  1075. RESERVED3 : word;
  1076. FNUM : word; //0010 DEVICE Device Frame Number
  1077. RESERVED4 : word;
  1078. INTENCLR : word; //0014 DEVICE Device Interrupt Enable Clear
  1079. RESERVED5 : word;
  1080. INTENSET : word; //0018 DEVICE Device Interrupt Enable Set
  1081. RESERVED6 : word;
  1082. INTFLAG : word; //001C DEVICE Device Interrupt Flag
  1083. RESERVED7 : word;
  1084. EPINTSMRY : word; //0020 DEVICE End Point Interrupt Summary
  1085. RESERVED8 : word;
  1086. DESCADD : longWord; //0024 Descriptor Address
  1087. PADCAL : word; //0028 USB PAD Calibration
  1088. RESERVED9 : array[1..214] of byte;
  1089. HOST_PIPE : array[0..7] of TUSB_HOST_PIPE_Registers; //0100
  1090. end;
  1091. TUSBHOST_Registers = record
  1092. CTRLA : byte; //0000 Control A
  1093. RESERVED0 : byte;
  1094. SYNCBUSY : byte; //0002 Synchronization Busy
  1095. QOSCTRL : byte; //0003 USB Quality Of Service
  1096. RESERVED1 : longWord;
  1097. CTRLB : word; //0008 HOST Control B
  1098. HSOFC : byte; //000A HOST Host Start Of Frame Control
  1099. RESERVED2 : byte;
  1100. STATUS : byte; //000C HOST Status
  1101. FSMSTATUS : byte; //000D Finite State Machine Status
  1102. RESERVED3 : word;
  1103. FNUM : word; //0010 HOST Host Frame Number
  1104. FLENHIGH : byte; //0012 HOST Host Frame Length
  1105. RESERVED4 : byte;
  1106. INTENCLR : word; //0014 HOST Host Interrupt Enable Clear
  1107. RESERVED5 : word;
  1108. INTENSET : word; //0018 HOST Host Interrupt Enable Set
  1109. RESERVED6 : word;
  1110. INTFLAG : word; //001C HOST Host Interrupt Flag
  1111. RESERVED7 : word;
  1112. PINTSMRY : word; //0020 HOST Pipe Interrupt Summary
  1113. RESERVED8 : word;
  1114. DESCADD : longWord; //0024 Descriptor Address
  1115. PADCAL : word; //0028 USB PAD Calibration
  1116. RESERVED9 : array[1..214] of byte;
  1117. HOST_PIPE : array[0..7] of TUSB_HOST_PIPE_Registers; //0100
  1118. end;
  1119. TUSB_DESCRIPTORDEVICE_Registers = record
  1120. HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers; //0000
  1121. end;
  1122. TUSB_DESCRIPTORHOST_Registers = record
  1123. HOST_DESC_BANK : array[0..1] of TUSB_HOST_DESC_BANK_Registers; //0000
  1124. end;
  1125. TWDT_Registers = record
  1126. CTRLA : byte; //0000 Control
  1127. CONFIG : byte; //0001 Configuration
  1128. EWCTRL : byte; //0002 Early Warning Interrupt Control
  1129. RESERVED0 : byte;
  1130. INTENCLR : byte; //0004 Interrupt Enable Clear
  1131. INTENSET : byte; //0005 Interrupt Enable Set
  1132. INTFLAG : byte; //0006 Interrupt Flag Status and Clear
  1133. RESERVED1 : byte;
  1134. SYNCBUSY : longWord; //0008 Synchronization Busy
  1135. CLEAR : byte; //000C Clear
  1136. end;
  1137. TETM_Registers = record
  1138. CR : longWord; //0000 ETM Main Control Register
  1139. CCR : longWord; //0004 ETM Configuration Code Register
  1140. TRIGGER : longWord; //0008 ETM Trigger Event Register
  1141. RESERVED0 : longWord;
  1142. SR : longWord; //0010 ETM Status Register
  1143. SCR : longWord; //0014 ETM System Configuration Register
  1144. RESERVED1 : array[1..8] of byte;
  1145. TEEVR : longWord; //0020 ETM TraceEnable Event Register
  1146. TECR1 : longWord; //0024 ETM TraceEnable Control 1 Register
  1147. FFLR : longWord; //0028 ETM FIFO Full Level Register
  1148. RESERVED2 : array[1..276] of byte;
  1149. CNTRLDVR1 : longWord; //0140 ETM Free-running Counter Reload Value
  1150. RESERVED3 : array[1..156] of byte;
  1151. SYNCFR : longWord; //01E0 ETM Synchronization Frequency Register
  1152. IDR : longWord; //01E4 ETM ID Register
  1153. CCER : longWord; //01E8 ETM Configuration Code Extension Register
  1154. RESERVED4 : longWord;
  1155. TESSEICR : longWord; //01F0 ETM TraceEnable Start/Stop EmbeddedICE Control Register
  1156. RESERVED5 : longWord;
  1157. TSEVT : longWord; //01F8 ETM TimeStamp Event Register
  1158. RESERVED6 : longWord;
  1159. TRACEIDR : longWord; //0200 ETM CoreSight Trace ID Register
  1160. RESERVED7 : longWord;
  1161. IDR2 : longWord; //0208 ETM ID Register 2
  1162. RESERVED8 : array[1..264] of byte;
  1163. PDSR : longWord; //0314 ETM Device Power-Down Status Register
  1164. RESERVED9 : array[1..3016] of byte;
  1165. ITMISCIN : longWord; //0EE0 ETM Integration Test Miscellaneous Inputs
  1166. RESERVED10 : longWord;
  1167. ITTRIGOUT : longWord; //0EE8 ETM Integration Test Trigger Out
  1168. RESERVED11 : longWord;
  1169. ITATBCTR2 : longWord; //0EF0 ETM Integration Test ATB Control 2
  1170. RESERVED12 : longWord;
  1171. ITATBCTR0 : longWord; //0EF8 ETM Integration Test ATB Control 0
  1172. RESERVED13 : longWord;
  1173. ITCTRL : longWord; //0F00 ETM Integration Mode Control Register
  1174. RESERVED14 : array[1..156] of byte;
  1175. CLAIMSET : longWord; //0FA0 ETM Claim Tag Set Register
  1176. CLAIMCLR : longWord; //0FA4 ETM Claim Tag Clear Register
  1177. RESERVED15 : array[1..8] of byte;
  1178. LAR : longWord; //0FB0 ETM Lock Access Register
  1179. LSR : longWord; //0FB4 ETM Lock Status Register
  1180. AUTHSTATUS : longWord; //0FB8 ETM Authentication Status Register
  1181. RESERVED16 : array[1..16] of byte;
  1182. DEVTYPE : longWord; //0FCC ETM CoreSight Device Type Register
  1183. PIDR4 : longWord; //0FD0 ETM Peripheral Identification Register #4
  1184. PIDR5 : longWord; //0FD4 ETM Peripheral Identification Register #5
  1185. PIDR6 : longWord; //0FD8 ETM Peripheral Identification Register #6
  1186. PIDR7 : longWord; //0FDC ETM Peripheral Identification Register #7
  1187. PIDR0 : longWord; //0FE0 ETM Peripheral Identification Register #0
  1188. PIDR1 : longWord; //0FE4 ETM Peripheral Identification Register #1
  1189. PIDR2 : longWord; //0FE8 ETM Peripheral Identification Register #2
  1190. PIDR3 : longWord; //0FEC ETM Peripheral Identification Register #3
  1191. CIDR0 : longWord; //0FF0 ETM Component Identification Register #0
  1192. CIDR1 : longWord; //0FF4 ETM Component Identification Register #1
  1193. CIDR2 : longWord; //0FF8 ETM Component Identification Register #2
  1194. CIDR3 : longWord; //0FFC ETM Component Identification Register #3
  1195. end;
  1196. TMPU_Registers = record
  1197. &TYPE : longWord; //0000 MPU Type Register
  1198. CTRL : longWord; //0004 MPU Control Register
  1199. RNR : longWord; //0008 MPU Region Number Register
  1200. RBAR : longWord; //000C MPU Region Base Address Register
  1201. RASR : longWord; //0010 MPU Region Attribute and Size Register
  1202. RBAR_A1 : longWord; //0014 MPU Alias 1 Region Base Address Register
  1203. RASR_A1 : longWord; //0018 MPU Alias 1 Region Attribute and Size Register
  1204. RBAR_A2 : longWord; //001C MPU Alias 2 Region Base Address Register
  1205. RASR_A2 : longWord; //0020 MPU Alias 2 Region Attribute and Size Register
  1206. RBAR_A3 : longWord; //0024 MPU Alias 3 Region Base Address Register
  1207. RASR_A3 : longWord; //0028 MPU Alias 3 Region Attribute and Size Register
  1208. end;
  1209. TSystemControl_Registers = record
  1210. ICTR : longWord; //0004 Interrupt Controller Type Register
  1211. ACTLR : longWord; //0008 Auxiliary Control Register
  1212. RESERVED0 : array[1..3316] of byte;
  1213. CPUID : longWord; //0D00 CPUID Base Register
  1214. ICSR : longWord; //0D04 Interrupt Control and State Register
  1215. VTOR : longWord; //0D08 Vector Table Offset Register
  1216. AIRCR : longWord; //0D0C Application Interrupt and Reset Control Register
  1217. SCR : longWord; //0D10 System Control Register
  1218. CCR : longWord; //0D14 Configuration and Control Register
  1219. SHPR1 : longWord; //0D18 System Handler Priority Register 1
  1220. SHPR2 : longWord; //0D1C System Handler Priority Register 2
  1221. SHPR3 : longWord; //0D20 System Handler Priority Register 3
  1222. SHCSR : longWord; //0D24 System Handler Control and State Register
  1223. CFSR : longWord; //0D28 Configurable Fault Status Register
  1224. HFSR : longWord; //0D2C HardFault Status Register
  1225. DFSR : longWord; //0D30 Debug Fault Status Register
  1226. MMFAR : longWord; //0D34 MemManage Fault Address Register
  1227. BFAR : longWord; //0D38 BusFault Address Register
  1228. AFSR : longWord; //0D3C Auxiliary Fault Status Register
  1229. PFR : array[0..1] of longWord; //0D40 Processor Feature Register
  1230. DFR : longWord; //0D48 Debug Feature Register
  1231. ADR : longWord; //0D4C Auxiliary Feature Register
  1232. MMFR : array[0..3] of longWord; //0D50 Memory Model Feature Register
  1233. ISAR : array[0..4] of longWord; //0D60 Instruction Set Attributes Register
  1234. RESERVED1 : array[1..20] of byte;
  1235. CPACR : longWord; //0D88 Coprocessor Access Control Register
  1236. end;
  1237. TTPIU_Registers = record
  1238. SSPSR : longWord; //0000 Supported Parallel Port Size Register
  1239. CSPSR : longWord; //0004 Current Parallel Port Size Register
  1240. RESERVED0 : array[1..8] of byte;
  1241. ACPR : longWord; //0010 Asynchronous Clock Prescaler Register
  1242. RESERVED1 : array[1..220] of byte;
  1243. SPPR : longWord; //00F0 Selected Pin Protocol Register
  1244. RESERVED2 : array[1..524] of byte;
  1245. FFSR : longWord; //0300 Formatter and Flush Status Register
  1246. FFCR : longWord; //0304 Formatter and Flush Control Register
  1247. FSCR : longWord; //0308 Formatter Synchronization Counter Register
  1248. RESERVED3 : array[1..3036] of byte;
  1249. TRIGGER : longWord; //0EE8 TRIGGER
  1250. FIFO0 : longWord; //0EEC Integration ETM Data
  1251. ITATBCTR2 : longWord; //0EF0 ITATBCTR2
  1252. RESERVED4 : longWord;
  1253. ITATBCTR0 : longWord; //0EF8 ITATBCTR0
  1254. FIFO1 : longWord; //0EFC Integration ITM Data
  1255. ITCTRL : longWord; //0F00 Integration Mode Control
  1256. RESERVED5 : array[1..156] of byte;
  1257. CLAIMSET : longWord; //0FA0 Claim tag set
  1258. CLAIMCLR : longWord; //0FA4 Claim tag clear
  1259. RESERVED6 : array[1..32] of byte;
  1260. DEVID : longWord; //0FC8 TPIU_DEVID
  1261. DEVTYPE : longWord; //0FCC TPIU_DEVTYPE
  1262. end;
  1263. TRTC_Registers = record
  1264. case byte of
  1265. 0: ( MODE0 : TRTCMODE0_Registers );
  1266. 1: ( MODE1 : TRTCMODE1_Registers );
  1267. 2: ( MODE2 : TRTCMODE2_Registers );
  1268. end;
  1269. TSERCOM_Registers = record
  1270. case byte of
  1271. 0: ( I2CM : TSERCOMI2CM_Registers );
  1272. 1: ( I2CS : TSERCOMI2CS_Registers );
  1273. 2: ( SPIS : TSERCOMSPIS_Registers );
  1274. 3: ( SPIM : TSERCOMSPIM_Registers );
  1275. 4: ( USART_EXT : TSERCOMUSART_EXT_Registers );
  1276. 5: ( USART_INT : TSERCOMUSART_INT_Registers );
  1277. end;
  1278. TTC_Registers = record
  1279. case byte of
  1280. 0: ( COUNT8 : TTCCOUNT8_Registers );
  1281. 1: ( COUNT16 : TTCCOUNT16_Registers );
  1282. 2: ( COUNT32 : TTCCOUNT32_Registers );
  1283. end;
  1284. TUSB_Registers = record
  1285. case byte of
  1286. 0: ( DEVICE : TUSBDEVICE_Registers );
  1287. 1: ( HOST : TUSBHOST_Registers );
  1288. end;
  1289. TUSB_DESCRIPTOR_Registers = record
  1290. case byte of
  1291. 0: ( DEVICE : TUSB_DESCRIPTORDEVICE_Registers );
  1292. 1: ( HOST : TUSB_DESCRIPTORHOST_Registers );
  1293. end;
  1294. const
  1295. AC_BASE = $42002000;
  1296. ADC0_BASE = $43001c00;
  1297. ADC1_BASE = $43002000;
  1298. AES_BASE = $42002400;
  1299. CCL_BASE = $42003800;
  1300. CMCC_BASE = $41006000;
  1301. DAC_BASE = $43002400;
  1302. DMAC_BASE = $4100a000;
  1303. DSU_BASE = $41002000;
  1304. EIC_BASE = $40002800;
  1305. ETM_BASE = $e0041000;
  1306. EVSYS_BASE = $4100e000;
  1307. FREQM_BASE = $40002c00;
  1308. GCLK_BASE = $40001c00;
  1309. HMATRIX_BASE = $4100c000;
  1310. I2S_BASE = $43002800;
  1311. ICM_BASE = $42002c00;
  1312. MCLK_BASE = $40000800;
  1313. MPU_BASE = $e000ed90;
  1314. NVMCTRL_BASE = $41004000;
  1315. OSC32KCTRL_BASE = $40001400;
  1316. OSCCTRL_BASE = $40001000;
  1317. PAC_BASE = $40000000;
  1318. PCC_BASE = $43002c00;
  1319. PDEC_BASE = $42001c00;
  1320. PM_BASE = $40000400;
  1321. PORT_BASE = $41008000;
  1322. QSPI_BASE = $42003400;
  1323. RAMECC_BASE = $41020000;
  1324. RSTC_BASE = $40000c00;
  1325. RTC_BASE = $40002400;
  1326. SDHC0_BASE = $45000000;
  1327. SDHC1_BASE = $46000000;
  1328. SERCOM0_BASE = $40003000;
  1329. SERCOM1_BASE = $40003400;
  1330. SERCOM2_BASE = $41012000;
  1331. SERCOM3_BASE = $41014000;
  1332. SERCOM4_BASE = $43000000;
  1333. SERCOM5_BASE = $43000400;
  1334. SERCOM6_BASE = $43000800;
  1335. SERCOM7_BASE = $43000c00;
  1336. SUPC_BASE = $40001800;
  1337. SW0_FUSES_BASE = $00800080;
  1338. SystemControl_BASE = $e000e000;
  1339. TC0_BASE = $40003800;
  1340. TC1_BASE = $40003c00;
  1341. TC2_BASE = $4101a000;
  1342. TC3_BASE = $4101c000;
  1343. TC4_BASE = $42001400;
  1344. TC5_BASE = $42001800;
  1345. TC6_BASE = $43001400;
  1346. TC7_BASE = $43001800;
  1347. TCC0_BASE = $41016000;
  1348. TCC1_BASE = $41018000;
  1349. TCC2_BASE = $42000c00;
  1350. TCC3_BASE = $42001000;
  1351. TCC4_BASE = $43001000;
  1352. TEMP_LOG_FUSES_BASE = $00800100;
  1353. TPIU_BASE = $e0040000;
  1354. TRNG_BASE = $42002800;
  1355. USB_BASE = $41000000;
  1356. USER_FUSES_BASE = $00804000;
  1357. WDT_BASE = $40002000;
  1358. var
  1359. AC : TAC_Registers absolute AC_BASE;
  1360. ADC0 : TADC_Registers absolute ADC0_BASE;
  1361. ADC1 : TADC_Registers absolute ADC1_BASE;
  1362. AES : TAES_Registers absolute AES_BASE;
  1363. CCL : TCCL_Registers absolute CCL_BASE;
  1364. CMCC : TCMCC_Registers absolute CMCC_BASE;
  1365. DAC : TDAC_Registers absolute DAC_BASE;
  1366. DMAC : TDMAC_Registers absolute DMAC_BASE;
  1367. DSU : TDSU_Registers absolute DSU_BASE;
  1368. EIC : TEIC_Registers absolute EIC_BASE;
  1369. ETM : TETM_Registers absolute ETM_BASE;
  1370. EVSYS : TEVSYS_Registers absolute EVSYS_BASE;
  1371. FREQM : TFREQM_Registers absolute FREQM_BASE;
  1372. GCLK : TGCLK_Registers absolute GCLK_BASE;
  1373. HMATRIX : THMATRIXB_Registers absolute HMATRIX_BASE;
  1374. I2S : TI2S_Registers absolute I2S_BASE;
  1375. ICM : TICM_Registers absolute ICM_BASE;
  1376. MCLK : TMCLK_Registers absolute MCLK_BASE;
  1377. MPU : TMPU_Registers absolute MPU_BASE;
  1378. NVMCTRL : TNVMCTRL_Registers absolute NVMCTRL_BASE;
  1379. OSC32KCTRL : TOSC32KCTRL_Registers absolute OSC32KCTRL_BASE;
  1380. OSCCTRL : TOSCCTRL_Registers absolute OSCCTRL_BASE;
  1381. PAC : TPAC_Registers absolute PAC_BASE;
  1382. PCC : TPCC_Registers absolute PCC_BASE;
  1383. PDEC : TPDEC_Registers absolute PDEC_BASE;
  1384. PM : TPM_Registers absolute PM_BASE;
  1385. PORT : TPORT_Registers absolute PORT_BASE;
  1386. QSPI : TQSPI_Registers absolute QSPI_BASE;
  1387. RAMECC : TRAMECC_Registers absolute RAMECC_BASE;
  1388. RSTC : TRSTC_Registers absolute RSTC_BASE;
  1389. RTC : TRTC_Registers absolute RTC_BASE;
  1390. SDHC0 : TSDHC_Registers absolute SDHC0_BASE;
  1391. SDHC1 : TSDHC_Registers absolute SDHC1_BASE;
  1392. SERCOM0 : TSERCOM_Registers absolute SERCOM0_BASE;
  1393. SERCOM1 : TSERCOM_Registers absolute SERCOM1_BASE;
  1394. SERCOM2 : TSERCOM_Registers absolute SERCOM2_BASE;
  1395. SERCOM3 : TSERCOM_Registers absolute SERCOM3_BASE;
  1396. SERCOM4 : TSERCOM_Registers absolute SERCOM4_BASE;
  1397. SERCOM5 : TSERCOM_Registers absolute SERCOM5_BASE;
  1398. SERCOM6 : TSERCOM_Registers absolute SERCOM6_BASE;
  1399. SERCOM7 : TSERCOM_Registers absolute SERCOM7_BASE;
  1400. SUPC : TSUPC_Registers absolute SUPC_BASE;
  1401. SW0_FUSES : TSW0_FUSES_Registers absolute SW0_FUSES_BASE;
  1402. SystemControl : TSystemControl_Registers absolute SystemControl_BASE;
  1403. TC0 : TTC_Registers absolute TC0_BASE;
  1404. TC1 : TTC_Registers absolute TC1_BASE;
  1405. TC2 : TTC_Registers absolute TC2_BASE;
  1406. TC3 : TTC_Registers absolute TC3_BASE;
  1407. TC4 : TTC_Registers absolute TC4_BASE;
  1408. TC5 : TTC_Registers absolute TC5_BASE;
  1409. TC6 : TTC_Registers absolute TC6_BASE;
  1410. TC7 : TTC_Registers absolute TC7_BASE;
  1411. TCC0 : TTCC_Registers absolute TCC0_BASE;
  1412. TCC1 : TTCC_Registers absolute TCC1_BASE;
  1413. TCC2 : TTCC_Registers absolute TCC2_BASE;
  1414. TCC3 : TTCC_Registers absolute TCC3_BASE;
  1415. TCC4 : TTCC_Registers absolute TCC4_BASE;
  1416. TEMP_LOG_FUSES : TTEMP_LOG_FUSES_Registers absolute TEMP_LOG_FUSES_BASE;
  1417. TPIU : TTPIU_Registers absolute TPIU_BASE;
  1418. TRNG : TTRNG_Registers absolute TRNG_BASE;
  1419. USB : TUSB_Registers absolute USB_BASE;
  1420. USER_FUSES : TUSER_FUSES_Registers absolute USER_FUSES_BASE;
  1421. WDT : TWDT_Registers absolute WDT_BASE;
  1422. implementation
  1423. {$DEFINE IMPLEMENTATION}
  1424. {$UNDEF INTERFACE}
  1425. procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
  1426. procedure HardFault_interrupt; external name 'HardFault_interrupt';
  1427. procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
  1428. procedure BusFault_interrupt; external name 'BusFault_interrupt';
  1429. procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
  1430. procedure SVCall_interrupt; external name 'SVCall_interrupt';
  1431. procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
  1432. procedure PendSV_interrupt; external name 'PendSV_interrupt';
  1433. procedure SysTick_interrupt; external name 'SysTick_interrupt';
  1434. procedure PM_interrupt; external name 'PM_interrupt';
  1435. procedure MCLK_interrupt; external name 'MCLK_interrupt';
  1436. procedure OSCCTRL_0_interrupt; external name 'OSCCTRL_0_interrupt';
  1437. procedure OSCCTRL_1_interrupt; external name 'OSCCTRL_1_interrupt';
  1438. procedure OSCCTRL_2_interrupt; external name 'OSCCTRL_2_interrupt';
  1439. procedure OSCCTRL_3_interrupt; external name 'OSCCTRL_3_interrupt';
  1440. procedure OSCCTRL_4_interrupt; external name 'OSCCTRL_4_interrupt';
  1441. procedure OSC32KCTRL_interrupt; external name 'OSC32KCTRL_interrupt';
  1442. procedure SUPC_0_interrupt; external name 'SUPC_0_interrupt';
  1443. procedure SUPC_1_interrupt; external name 'SUPC_1_interrupt';
  1444. procedure WDT_interrupt; external name 'WDT_interrupt';
  1445. procedure RTC_interrupt; external name 'RTC_interrupt';
  1446. procedure EIC_0_interrupt; external name 'EIC_0_interrupt';
  1447. procedure EIC_1_interrupt; external name 'EIC_1_interrupt';
  1448. procedure EIC_2_interrupt; external name 'EIC_2_interrupt';
  1449. procedure EIC_3_interrupt; external name 'EIC_3_interrupt';
  1450. procedure EIC_4_interrupt; external name 'EIC_4_interrupt';
  1451. procedure EIC_5_interrupt; external name 'EIC_5_interrupt';
  1452. procedure EIC_6_interrupt; external name 'EIC_6_interrupt';
  1453. procedure EIC_7_interrupt; external name 'EIC_7_interrupt';
  1454. procedure EIC_8_interrupt; external name 'EIC_8_interrupt';
  1455. procedure EIC_9_interrupt; external name 'EIC_9_interrupt';
  1456. procedure EIC_10_interrupt; external name 'EIC_10_interrupt';
  1457. procedure EIC_11_interrupt; external name 'EIC_11_interrupt';
  1458. procedure EIC_12_interrupt; external name 'EIC_12_interrupt';
  1459. procedure EIC_13_interrupt; external name 'EIC_13_interrupt';
  1460. procedure EIC_14_interrupt; external name 'EIC_14_interrupt';
  1461. procedure EIC_15_interrupt; external name 'EIC_15_interrupt';
  1462. procedure FREQM_interrupt; external name 'FREQM_interrupt';
  1463. procedure NVMCTRL_0_interrupt; external name 'NVMCTRL_0_interrupt';
  1464. procedure NVMCTRL_1_interrupt; external name 'NVMCTRL_1_interrupt';
  1465. procedure DMAC_0_interrupt; external name 'DMAC_0_interrupt';
  1466. procedure DMAC_1_interrupt; external name 'DMAC_1_interrupt';
  1467. procedure DMAC_2_interrupt; external name 'DMAC_2_interrupt';
  1468. procedure DMAC_3_interrupt; external name 'DMAC_3_interrupt';
  1469. procedure DMAC_4_interrupt; external name 'DMAC_4_interrupt';
  1470. procedure EVSYS_0_interrupt; external name 'EVSYS_0_interrupt';
  1471. procedure EVSYS_1_interrupt; external name 'EVSYS_1_interrupt';
  1472. procedure EVSYS_2_interrupt; external name 'EVSYS_2_interrupt';
  1473. procedure EVSYS_3_interrupt; external name 'EVSYS_3_interrupt';
  1474. procedure EVSYS_4_interrupt; external name 'EVSYS_4_interrupt';
  1475. procedure PAC_interrupt; external name 'PAC_interrupt';
  1476. procedure RAMECC_interrupt; external name 'RAMECC_interrupt';
  1477. procedure SERCOM0_0_interrupt; external name 'SERCOM0_0_interrupt';
  1478. procedure SERCOM0_1_interrupt; external name 'SERCOM0_1_interrupt';
  1479. procedure SERCOM0_2_interrupt; external name 'SERCOM0_2_interrupt';
  1480. procedure SERCOM0_3_interrupt; external name 'SERCOM0_3_interrupt';
  1481. procedure SERCOM1_0_interrupt; external name 'SERCOM1_0_interrupt';
  1482. procedure SERCOM1_1_interrupt; external name 'SERCOM1_1_interrupt';
  1483. procedure SERCOM1_2_interrupt; external name 'SERCOM1_2_interrupt';
  1484. procedure SERCOM1_3_interrupt; external name 'SERCOM1_3_interrupt';
  1485. procedure SERCOM2_0_interrupt; external name 'SERCOM2_0_interrupt';
  1486. procedure SERCOM2_1_interrupt; external name 'SERCOM2_1_interrupt';
  1487. procedure SERCOM2_2_interrupt; external name 'SERCOM2_2_interrupt';
  1488. procedure SERCOM2_3_interrupt; external name 'SERCOM2_3_interrupt';
  1489. procedure SERCOM3_0_interrupt; external name 'SERCOM3_0_interrupt';
  1490. procedure SERCOM3_1_interrupt; external name 'SERCOM3_1_interrupt';
  1491. procedure SERCOM3_2_interrupt; external name 'SERCOM3_2_interrupt';
  1492. procedure SERCOM3_3_interrupt; external name 'SERCOM3_3_interrupt';
  1493. procedure SERCOM4_0_interrupt; external name 'SERCOM4_0_interrupt';
  1494. procedure SERCOM4_1_interrupt; external name 'SERCOM4_1_interrupt';
  1495. procedure SERCOM4_2_interrupt; external name 'SERCOM4_2_interrupt';
  1496. procedure SERCOM4_3_interrupt; external name 'SERCOM4_3_interrupt';
  1497. procedure SERCOM5_0_interrupt; external name 'SERCOM5_0_interrupt';
  1498. procedure SERCOM5_1_interrupt; external name 'SERCOM5_1_interrupt';
  1499. procedure SERCOM5_2_interrupt; external name 'SERCOM5_2_interrupt';
  1500. procedure SERCOM5_3_interrupt; external name 'SERCOM5_3_interrupt';
  1501. procedure SERCOM6_0_interrupt; external name 'SERCOM6_0_interrupt';
  1502. procedure SERCOM6_1_interrupt; external name 'SERCOM6_1_interrupt';
  1503. procedure SERCOM6_2_interrupt; external name 'SERCOM6_2_interrupt';
  1504. procedure SERCOM6_3_interrupt; external name 'SERCOM6_3_interrupt';
  1505. procedure SERCOM7_0_interrupt; external name 'SERCOM7_0_interrupt';
  1506. procedure SERCOM7_1_interrupt; external name 'SERCOM7_1_interrupt';
  1507. procedure SERCOM7_2_interrupt; external name 'SERCOM7_2_interrupt';
  1508. procedure SERCOM7_3_interrupt; external name 'SERCOM7_3_interrupt';
  1509. procedure USB_0_interrupt; external name 'USB_0_interrupt';
  1510. procedure USB_1_interrupt; external name 'USB_1_interrupt';
  1511. procedure USB_2_interrupt; external name 'USB_2_interrupt';
  1512. procedure USB_3_interrupt; external name 'USB_3_interrupt';
  1513. procedure TCC0_0_interrupt; external name 'TCC0_0_interrupt';
  1514. procedure TCC0_1_interrupt; external name 'TCC0_1_interrupt';
  1515. procedure TCC0_2_interrupt; external name 'TCC0_2_interrupt';
  1516. procedure TCC0_3_interrupt; external name 'TCC0_3_interrupt';
  1517. procedure TCC0_4_interrupt; external name 'TCC0_4_interrupt';
  1518. procedure TCC0_5_interrupt; external name 'TCC0_5_interrupt';
  1519. procedure TCC0_6_interrupt; external name 'TCC0_6_interrupt';
  1520. procedure TCC1_0_interrupt; external name 'TCC1_0_interrupt';
  1521. procedure TCC1_1_interrupt; external name 'TCC1_1_interrupt';
  1522. procedure TCC1_2_interrupt; external name 'TCC1_2_interrupt';
  1523. procedure TCC1_3_interrupt; external name 'TCC1_3_interrupt';
  1524. procedure TCC1_4_interrupt; external name 'TCC1_4_interrupt';
  1525. procedure TCC2_0_interrupt; external name 'TCC2_0_interrupt';
  1526. procedure TCC2_1_interrupt; external name 'TCC2_1_interrupt';
  1527. procedure TCC2_2_interrupt; external name 'TCC2_2_interrupt';
  1528. procedure TCC2_3_interrupt; external name 'TCC2_3_interrupt';
  1529. procedure TCC3_0_interrupt; external name 'TCC3_0_interrupt';
  1530. procedure TCC3_1_interrupt; external name 'TCC3_1_interrupt';
  1531. procedure TCC3_2_interrupt; external name 'TCC3_2_interrupt';
  1532. procedure TCC4_0_interrupt; external name 'TCC4_0_interrupt';
  1533. procedure TCC4_1_interrupt; external name 'TCC4_1_interrupt';
  1534. procedure TCC4_2_interrupt; external name 'TCC4_2_interrupt';
  1535. procedure TC0_interrupt; external name 'TC0_interrupt';
  1536. procedure TC1_interrupt; external name 'TC1_interrupt';
  1537. procedure TC2_interrupt; external name 'TC2_interrupt';
  1538. procedure TC3_interrupt; external name 'TC3_interrupt';
  1539. procedure TC4_interrupt; external name 'TC4_interrupt';
  1540. procedure TC5_interrupt; external name 'TC5_interrupt';
  1541. procedure TC6_interrupt; external name 'TC6_interrupt';
  1542. procedure TC7_interrupt; external name 'TC7_interrupt';
  1543. procedure PDEC_0_interrupt; external name 'PDEC_0_interrupt';
  1544. procedure PDEC_1_interrupt; external name 'PDEC_1_interrupt';
  1545. procedure PDEC_2_interrupt; external name 'PDEC_2_interrupt';
  1546. procedure ADC0_0_interrupt; external name 'ADC0_0_interrupt';
  1547. procedure ADC0_1_interrupt; external name 'ADC0_1_interrupt';
  1548. procedure ADC1_0_interrupt; external name 'ADC1_0_interrupt';
  1549. procedure ADC1_1_interrupt; external name 'ADC1_1_interrupt';
  1550. procedure AC_interrupt; external name 'AC_interrupt';
  1551. procedure DAC_0_interrupt; external name 'DAC_0_interrupt';
  1552. procedure DAC_1_interrupt; external name 'DAC_1_interrupt';
  1553. procedure DAC_2_interrupt; external name 'DAC_2_interrupt';
  1554. procedure DAC_3_interrupt; external name 'DAC_3_interrupt';
  1555. procedure DAC_4_interrupt; external name 'DAC_4_interrupt';
  1556. procedure I2S_interrupt; external name 'I2S_interrupt';
  1557. procedure PCC_interrupt; external name 'PCC_interrupt';
  1558. procedure AES_interrupt; external name 'AES_interrupt';
  1559. procedure TRNG_interrupt; external name 'TRNG_interrupt';
  1560. procedure ICM_interrupt; external name 'ICM_interrupt';
  1561. procedure PUKCC_interrupt; external name 'PUKCC_interrupt';
  1562. procedure QSPI_interrupt; external name 'QSPI_interrupt';
  1563. procedure SDHC0_interrupt; external name 'SDHC0_interrupt';
  1564. procedure SDHC1_interrupt; external name 'SDHC1_interrupt';
  1565. {$i cortexm4f_start.inc}
  1566. procedure Vectors; assembler; nostackframe;
  1567. label interrupt_vectors;
  1568. asm
  1569. .section ".init.interrupt_vectors"
  1570. interrupt_vectors:
  1571. .long _stack_top
  1572. .long Startup
  1573. .long NonMaskableInt_interrupt;
  1574. .long HardFault_interrupt;
  1575. .long MemoryManagement_interrupt;
  1576. .long BusFault_interrupt;
  1577. .long UsageFault_interrupt;
  1578. .long 0
  1579. .long 0
  1580. .long 0
  1581. .long 0
  1582. .long SVCall_interrupt;
  1583. .long DebugMonitor_interrupt;
  1584. .long 0
  1585. .long PendSV_interrupt;
  1586. .long SysTick_interrupt;
  1587. .long PM_interrupt;
  1588. .long MCLK_interrupt;
  1589. .long OSCCTRL_0_interrupt;
  1590. .long OSCCTRL_1_interrupt;
  1591. .long OSCCTRL_2_interrupt;
  1592. .long OSCCTRL_3_interrupt;
  1593. .long OSCCTRL_4_interrupt;
  1594. .long OSC32KCTRL_interrupt;
  1595. .long SUPC_0_interrupt;
  1596. .long SUPC_1_interrupt;
  1597. .long WDT_interrupt;
  1598. .long RTC_interrupt;
  1599. .long EIC_0_interrupt;
  1600. .long EIC_1_interrupt;
  1601. .long EIC_2_interrupt;
  1602. .long EIC_3_interrupt;
  1603. .long EIC_4_interrupt;
  1604. .long EIC_5_interrupt;
  1605. .long EIC_6_interrupt;
  1606. .long EIC_7_interrupt;
  1607. .long EIC_8_interrupt;
  1608. .long EIC_9_interrupt;
  1609. .long EIC_10_interrupt;
  1610. .long EIC_11_interrupt;
  1611. .long EIC_12_interrupt;
  1612. .long EIC_13_interrupt;
  1613. .long EIC_14_interrupt;
  1614. .long EIC_15_interrupt;
  1615. .long FREQM_interrupt;
  1616. .long NVMCTRL_0_interrupt;
  1617. .long NVMCTRL_1_interrupt;
  1618. .long DMAC_0_interrupt;
  1619. .long DMAC_1_interrupt;
  1620. .long DMAC_2_interrupt;
  1621. .long DMAC_3_interrupt;
  1622. .long DMAC_4_interrupt;
  1623. .long EVSYS_0_interrupt;
  1624. .long EVSYS_1_interrupt;
  1625. .long EVSYS_2_interrupt;
  1626. .long EVSYS_3_interrupt;
  1627. .long EVSYS_4_interrupt;
  1628. .long PAC_interrupt;
  1629. .long 0
  1630. .long 0
  1631. .long 0
  1632. .long RAMECC_interrupt;
  1633. .long SERCOM0_0_interrupt;
  1634. .long SERCOM0_1_interrupt;
  1635. .long SERCOM0_2_interrupt;
  1636. .long SERCOM0_3_interrupt;
  1637. .long SERCOM1_0_interrupt;
  1638. .long SERCOM1_1_interrupt;
  1639. .long SERCOM1_2_interrupt;
  1640. .long SERCOM1_3_interrupt;
  1641. .long SERCOM2_0_interrupt;
  1642. .long SERCOM2_1_interrupt;
  1643. .long SERCOM2_2_interrupt;
  1644. .long SERCOM2_3_interrupt;
  1645. .long SERCOM3_0_interrupt;
  1646. .long SERCOM3_1_interrupt;
  1647. .long SERCOM3_2_interrupt;
  1648. .long SERCOM3_3_interrupt;
  1649. .long SERCOM4_0_interrupt;
  1650. .long SERCOM4_1_interrupt;
  1651. .long SERCOM4_2_interrupt;
  1652. .long SERCOM4_3_interrupt;
  1653. .long SERCOM5_0_interrupt;
  1654. .long SERCOM5_1_interrupt;
  1655. .long SERCOM5_2_interrupt;
  1656. .long SERCOM5_3_interrupt;
  1657. .long SERCOM6_0_interrupt;
  1658. .long SERCOM6_1_interrupt;
  1659. .long SERCOM6_2_interrupt;
  1660. .long SERCOM6_3_interrupt;
  1661. .long SERCOM7_0_interrupt;
  1662. .long SERCOM7_1_interrupt;
  1663. .long SERCOM7_2_interrupt;
  1664. .long SERCOM7_3_interrupt;
  1665. .long 0
  1666. .long 0
  1667. .long USB_0_interrupt;
  1668. .long USB_1_interrupt;
  1669. .long USB_2_interrupt;
  1670. .long USB_3_interrupt;
  1671. .long 0
  1672. .long TCC0_0_interrupt;
  1673. .long TCC0_1_interrupt;
  1674. .long TCC0_2_interrupt;
  1675. .long TCC0_3_interrupt;
  1676. .long TCC0_4_interrupt;
  1677. .long TCC0_5_interrupt;
  1678. .long TCC0_6_interrupt;
  1679. .long TCC1_0_interrupt;
  1680. .long TCC1_1_interrupt;
  1681. .long TCC1_2_interrupt;
  1682. .long TCC1_3_interrupt;
  1683. .long TCC1_4_interrupt;
  1684. .long TCC2_0_interrupt;
  1685. .long TCC2_1_interrupt;
  1686. .long TCC2_2_interrupt;
  1687. .long TCC2_3_interrupt;
  1688. .long TCC3_0_interrupt;
  1689. .long TCC3_1_interrupt;
  1690. .long TCC3_2_interrupt;
  1691. .long TCC4_0_interrupt;
  1692. .long TCC4_1_interrupt;
  1693. .long TCC4_2_interrupt;
  1694. .long TC0_interrupt;
  1695. .long TC1_interrupt;
  1696. .long TC2_interrupt;
  1697. .long TC3_interrupt;
  1698. .long TC4_interrupt;
  1699. .long TC5_interrupt;
  1700. .long TC6_interrupt;
  1701. .long TC7_interrupt;
  1702. .long PDEC_0_interrupt;
  1703. .long PDEC_1_interrupt;
  1704. .long PDEC_2_interrupt;
  1705. .long ADC0_0_interrupt;
  1706. .long ADC0_1_interrupt;
  1707. .long ADC1_0_interrupt;
  1708. .long ADC1_1_interrupt;
  1709. .long AC_interrupt;
  1710. .long DAC_0_interrupt;
  1711. .long DAC_1_interrupt;
  1712. .long DAC_2_interrupt;
  1713. .long DAC_3_interrupt;
  1714. .long DAC_4_interrupt;
  1715. .long I2S_interrupt;
  1716. .long PCC_interrupt;
  1717. .long AES_interrupt;
  1718. .long TRNG_interrupt;
  1719. .long ICM_interrupt;
  1720. .long PUKCC_interrupt;
  1721. .long QSPI_interrupt;
  1722. .long SDHC0_interrupt;
  1723. .long SDHC1_interrupt;
  1724. .weak NonMaskableInt_interrupt;
  1725. .weak HardFault_interrupt;
  1726. .weak MemoryManagement_interrupt;
  1727. .weak BusFault_interrupt;
  1728. .weak UsageFault_interrupt;
  1729. .weak SVCall_interrupt;
  1730. .weak DebugMonitor_interrupt;
  1731. .weak PendSV_interrupt;
  1732. .weak SysTick_interrupt;
  1733. .weak PM_interrupt;
  1734. .weak MCLK_interrupt;
  1735. .weak OSCCTRL_0_interrupt;
  1736. .weak OSCCTRL_1_interrupt;
  1737. .weak OSCCTRL_2_interrupt;
  1738. .weak OSCCTRL_3_interrupt;
  1739. .weak OSCCTRL_4_interrupt;
  1740. .weak OSC32KCTRL_interrupt;
  1741. .weak SUPC_0_interrupt;
  1742. .weak SUPC_1_interrupt;
  1743. .weak WDT_interrupt;
  1744. .weak RTC_interrupt;
  1745. .weak EIC_0_interrupt;
  1746. .weak EIC_1_interrupt;
  1747. .weak EIC_2_interrupt;
  1748. .weak EIC_3_interrupt;
  1749. .weak EIC_4_interrupt;
  1750. .weak EIC_5_interrupt;
  1751. .weak EIC_6_interrupt;
  1752. .weak EIC_7_interrupt;
  1753. .weak EIC_8_interrupt;
  1754. .weak EIC_9_interrupt;
  1755. .weak EIC_10_interrupt;
  1756. .weak EIC_11_interrupt;
  1757. .weak EIC_12_interrupt;
  1758. .weak EIC_13_interrupt;
  1759. .weak EIC_14_interrupt;
  1760. .weak EIC_15_interrupt;
  1761. .weak FREQM_interrupt;
  1762. .weak NVMCTRL_0_interrupt;
  1763. .weak NVMCTRL_1_interrupt;
  1764. .weak DMAC_0_interrupt;
  1765. .weak DMAC_1_interrupt;
  1766. .weak DMAC_2_interrupt;
  1767. .weak DMAC_3_interrupt;
  1768. .weak DMAC_4_interrupt;
  1769. .weak EVSYS_0_interrupt;
  1770. .weak EVSYS_1_interrupt;
  1771. .weak EVSYS_2_interrupt;
  1772. .weak EVSYS_3_interrupt;
  1773. .weak EVSYS_4_interrupt;
  1774. .weak PAC_interrupt;
  1775. .weak RAMECC_interrupt;
  1776. .weak SERCOM0_0_interrupt;
  1777. .weak SERCOM0_1_interrupt;
  1778. .weak SERCOM0_2_interrupt;
  1779. .weak SERCOM0_3_interrupt;
  1780. .weak SERCOM1_0_interrupt;
  1781. .weak SERCOM1_1_interrupt;
  1782. .weak SERCOM1_2_interrupt;
  1783. .weak SERCOM1_3_interrupt;
  1784. .weak SERCOM2_0_interrupt;
  1785. .weak SERCOM2_1_interrupt;
  1786. .weak SERCOM2_2_interrupt;
  1787. .weak SERCOM2_3_interrupt;
  1788. .weak SERCOM3_0_interrupt;
  1789. .weak SERCOM3_1_interrupt;
  1790. .weak SERCOM3_2_interrupt;
  1791. .weak SERCOM3_3_interrupt;
  1792. .weak SERCOM4_0_interrupt;
  1793. .weak SERCOM4_1_interrupt;
  1794. .weak SERCOM4_2_interrupt;
  1795. .weak SERCOM4_3_interrupt;
  1796. .weak SERCOM5_0_interrupt;
  1797. .weak SERCOM5_1_interrupt;
  1798. .weak SERCOM5_2_interrupt;
  1799. .weak SERCOM5_3_interrupt;
  1800. .weak SERCOM6_0_interrupt;
  1801. .weak SERCOM6_1_interrupt;
  1802. .weak SERCOM6_2_interrupt;
  1803. .weak SERCOM6_3_interrupt;
  1804. .weak SERCOM7_0_interrupt;
  1805. .weak SERCOM7_1_interrupt;
  1806. .weak SERCOM7_2_interrupt;
  1807. .weak SERCOM7_3_interrupt;
  1808. .weak USB_0_interrupt;
  1809. .weak USB_1_interrupt;
  1810. .weak USB_2_interrupt;
  1811. .weak USB_3_interrupt;
  1812. .weak TCC0_0_interrupt;
  1813. .weak TCC0_1_interrupt;
  1814. .weak TCC0_2_interrupt;
  1815. .weak TCC0_3_interrupt;
  1816. .weak TCC0_4_interrupt;
  1817. .weak TCC0_5_interrupt;
  1818. .weak TCC0_6_interrupt;
  1819. .weak TCC1_0_interrupt;
  1820. .weak TCC1_1_interrupt;
  1821. .weak TCC1_2_interrupt;
  1822. .weak TCC1_3_interrupt;
  1823. .weak TCC1_4_interrupt;
  1824. .weak TCC2_0_interrupt;
  1825. .weak TCC2_1_interrupt;
  1826. .weak TCC2_2_interrupt;
  1827. .weak TCC2_3_interrupt;
  1828. .weak TCC3_0_interrupt;
  1829. .weak TCC3_1_interrupt;
  1830. .weak TCC3_2_interrupt;
  1831. .weak TCC4_0_interrupt;
  1832. .weak TCC4_1_interrupt;
  1833. .weak TCC4_2_interrupt;
  1834. .weak TC0_interrupt;
  1835. .weak TC1_interrupt;
  1836. .weak TC2_interrupt;
  1837. .weak TC3_interrupt;
  1838. .weak TC4_interrupt;
  1839. .weak TC5_interrupt;
  1840. .weak TC6_interrupt;
  1841. .weak TC7_interrupt;
  1842. .weak PDEC_0_interrupt;
  1843. .weak PDEC_1_interrupt;
  1844. .weak PDEC_2_interrupt;
  1845. .weak ADC0_0_interrupt;
  1846. .weak ADC0_1_interrupt;
  1847. .weak ADC1_0_interrupt;
  1848. .weak ADC1_1_interrupt;
  1849. .weak AC_interrupt;
  1850. .weak DAC_0_interrupt;
  1851. .weak DAC_1_interrupt;
  1852. .weak DAC_2_interrupt;
  1853. .weak DAC_3_interrupt;
  1854. .weak DAC_4_interrupt;
  1855. .weak I2S_interrupt;
  1856. .weak PCC_interrupt;
  1857. .weak AES_interrupt;
  1858. .weak TRNG_interrupt;
  1859. .weak ICM_interrupt;
  1860. .weak PUKCC_interrupt;
  1861. .weak QSPI_interrupt;
  1862. .weak SDHC0_interrupt;
  1863. .weak SDHC1_interrupt;
  1864. .set NonMaskableInt_interrupt, Haltproc
  1865. .set HardFault_interrupt, Haltproc
  1866. .set MemoryManagement_interrupt,Haltproc
  1867. .set BusFault_interrupt, Haltproc
  1868. .set UsageFault_interrupt, Haltproc
  1869. .set SVCall_interrupt, Haltproc
  1870. .set DebugMonitor_interrupt, Haltproc
  1871. .set PendSV_interrupt, Haltproc
  1872. .set SysTick_interrupt, Haltproc
  1873. .set PM_interrupt, Haltproc
  1874. .set MCLK_interrupt, Haltproc
  1875. .set OSCCTRL_0_interrupt, Haltproc
  1876. .set OSCCTRL_1_interrupt, Haltproc
  1877. .set OSCCTRL_2_interrupt, Haltproc
  1878. .set OSCCTRL_3_interrupt, Haltproc
  1879. .set OSCCTRL_4_interrupt, Haltproc
  1880. .set OSC32KCTRL_interrupt, Haltproc
  1881. .set SUPC_0_interrupt, Haltproc
  1882. .set SUPC_1_interrupt, Haltproc
  1883. .set WDT_interrupt, Haltproc
  1884. .set RTC_interrupt, Haltproc
  1885. .set EIC_0_interrupt, Haltproc
  1886. .set EIC_1_interrupt, Haltproc
  1887. .set EIC_2_interrupt, Haltproc
  1888. .set EIC_3_interrupt, Haltproc
  1889. .set EIC_4_interrupt, Haltproc
  1890. .set EIC_5_interrupt, Haltproc
  1891. .set EIC_6_interrupt, Haltproc
  1892. .set EIC_7_interrupt, Haltproc
  1893. .set EIC_8_interrupt, Haltproc
  1894. .set EIC_9_interrupt, Haltproc
  1895. .set EIC_10_interrupt, Haltproc
  1896. .set EIC_11_interrupt, Haltproc
  1897. .set EIC_12_interrupt, Haltproc
  1898. .set EIC_13_interrupt, Haltproc
  1899. .set EIC_14_interrupt, Haltproc
  1900. .set EIC_15_interrupt, Haltproc
  1901. .set FREQM_interrupt, Haltproc
  1902. .set NVMCTRL_0_interrupt, Haltproc
  1903. .set NVMCTRL_1_interrupt, Haltproc
  1904. .set DMAC_0_interrupt, Haltproc
  1905. .set DMAC_1_interrupt, Haltproc
  1906. .set DMAC_2_interrupt, Haltproc
  1907. .set DMAC_3_interrupt, Haltproc
  1908. .set DMAC_4_interrupt, Haltproc
  1909. .set EVSYS_0_interrupt, Haltproc
  1910. .set EVSYS_1_interrupt, Haltproc
  1911. .set EVSYS_2_interrupt, Haltproc
  1912. .set EVSYS_3_interrupt, Haltproc
  1913. .set EVSYS_4_interrupt, Haltproc
  1914. .set PAC_interrupt, Haltproc
  1915. .set RAMECC_interrupt, Haltproc
  1916. .set SERCOM0_0_interrupt, Haltproc
  1917. .set SERCOM0_1_interrupt, Haltproc
  1918. .set SERCOM0_2_interrupt, Haltproc
  1919. .set SERCOM0_3_interrupt, Haltproc
  1920. .set SERCOM1_0_interrupt, Haltproc
  1921. .set SERCOM1_1_interrupt, Haltproc
  1922. .set SERCOM1_2_interrupt, Haltproc
  1923. .set SERCOM1_3_interrupt, Haltproc
  1924. .set SERCOM2_0_interrupt, Haltproc
  1925. .set SERCOM2_1_interrupt, Haltproc
  1926. .set SERCOM2_2_interrupt, Haltproc
  1927. .set SERCOM2_3_interrupt, Haltproc
  1928. .set SERCOM3_0_interrupt, Haltproc
  1929. .set SERCOM3_1_interrupt, Haltproc
  1930. .set SERCOM3_2_interrupt, Haltproc
  1931. .set SERCOM3_3_interrupt, Haltproc
  1932. .set SERCOM4_0_interrupt, Haltproc
  1933. .set SERCOM4_1_interrupt, Haltproc
  1934. .set SERCOM4_2_interrupt, Haltproc
  1935. .set SERCOM4_3_interrupt, Haltproc
  1936. .set SERCOM5_0_interrupt, Haltproc
  1937. .set SERCOM5_1_interrupt, Haltproc
  1938. .set SERCOM5_2_interrupt, Haltproc
  1939. .set SERCOM5_3_interrupt, Haltproc
  1940. .set SERCOM6_0_interrupt, Haltproc
  1941. .set SERCOM6_1_interrupt, Haltproc
  1942. .set SERCOM6_2_interrupt, Haltproc
  1943. .set SERCOM6_3_interrupt, Haltproc
  1944. .set SERCOM7_0_interrupt, Haltproc
  1945. .set SERCOM7_1_interrupt, Haltproc
  1946. .set SERCOM7_2_interrupt, Haltproc
  1947. .set SERCOM7_3_interrupt, Haltproc
  1948. .set USB_0_interrupt, Haltproc
  1949. .set USB_1_interrupt, Haltproc
  1950. .set USB_2_interrupt, Haltproc
  1951. .set USB_3_interrupt, Haltproc
  1952. .set TCC0_0_interrupt, Haltproc
  1953. .set TCC0_1_interrupt, Haltproc
  1954. .set TCC0_2_interrupt, Haltproc
  1955. .set TCC0_3_interrupt, Haltproc
  1956. .set TCC0_4_interrupt, Haltproc
  1957. .set TCC0_5_interrupt, Haltproc
  1958. .set TCC0_6_interrupt, Haltproc
  1959. .set TCC1_0_interrupt, Haltproc
  1960. .set TCC1_1_interrupt, Haltproc
  1961. .set TCC1_2_interrupt, Haltproc
  1962. .set TCC1_3_interrupt, Haltproc
  1963. .set TCC1_4_interrupt, Haltproc
  1964. .set TCC2_0_interrupt, Haltproc
  1965. .set TCC2_1_interrupt, Haltproc
  1966. .set TCC2_2_interrupt, Haltproc
  1967. .set TCC2_3_interrupt, Haltproc
  1968. .set TCC3_0_interrupt, Haltproc
  1969. .set TCC3_1_interrupt, Haltproc
  1970. .set TCC3_2_interrupt, Haltproc
  1971. .set TCC4_0_interrupt, Haltproc
  1972. .set TCC4_1_interrupt, Haltproc
  1973. .set TCC4_2_interrupt, Haltproc
  1974. .set TC0_interrupt, Haltproc
  1975. .set TC1_interrupt, Haltproc
  1976. .set TC2_interrupt, Haltproc
  1977. .set TC3_interrupt, Haltproc
  1978. .set TC4_interrupt, Haltproc
  1979. .set TC5_interrupt, Haltproc
  1980. .set TC6_interrupt, Haltproc
  1981. .set TC7_interrupt, Haltproc
  1982. .set PDEC_0_interrupt, Haltproc
  1983. .set PDEC_1_interrupt, Haltproc
  1984. .set PDEC_2_interrupt, Haltproc
  1985. .set ADC0_0_interrupt, Haltproc
  1986. .set ADC0_1_interrupt, Haltproc
  1987. .set ADC1_0_interrupt, Haltproc
  1988. .set ADC1_1_interrupt, Haltproc
  1989. .set AC_interrupt, Haltproc
  1990. .set DAC_0_interrupt, Haltproc
  1991. .set DAC_1_interrupt, Haltproc
  1992. .set DAC_2_interrupt, Haltproc
  1993. .set DAC_3_interrupt, Haltproc
  1994. .set DAC_4_interrupt, Haltproc
  1995. .set I2S_interrupt, Haltproc
  1996. .set PCC_interrupt, Haltproc
  1997. .set AES_interrupt, Haltproc
  1998. .set TRNG_interrupt, Haltproc
  1999. .set ICM_interrupt, Haltproc
  2000. .set PUKCC_interrupt, Haltproc
  2001. .set QSPI_interrupt, Haltproc
  2002. .set SDHC0_interrupt, Haltproc
  2003. .set SDHC1_interrupt, Haltproc
  2004. .text
  2005. end;
  2006. end.