aasmcpu.pas 143 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  3. Contains the abstract assembler implementation for the i386
  4. * Portions of this code was inspired by the NASM sources
  5. The Netwide Assembler is Copyright (c) 1996 Simon Tatham and
  6. Julian Hall. All rights reserved.
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. ****************************************************************************
  19. }
  20. unit aasmcpu;
  21. {$i fpcdefs.inc}
  22. interface
  23. uses
  24. globtype,verbose,
  25. cpubase,
  26. cgbase,cgutils,
  27. aasmbase,aasmtai,aasmsym,
  28. ogbase;
  29. const
  30. { "mov reg,reg" source operand number }
  31. O_MOV_SOURCE = 0;
  32. { "mov reg,reg" destination operand number }
  33. O_MOV_DEST = 1;
  34. { Operand types }
  35. OT_NONE = $00000000;
  36. { Bits 0..7: sizes }
  37. OT_BITS8 = $00000001;
  38. OT_BITS16 = $00000002;
  39. OT_BITS32 = $00000004;
  40. OT_BITS64 = $00000008; { x86_64 and FPU }
  41. OT_BITS128 = $10000000; { 16 byte SSE }
  42. OT_BITS256 = $20000000; { 32 byte AVX }
  43. OT_BITS80 = $00000010; { FPU only }
  44. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  45. OT_NEAR = $00000040;
  46. OT_SHORT = $00000080;
  47. { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask,
  48. but this requires adjusting the opcode table }
  49. OT_SIZE_MASK = $3000001F; { all the size attributes }
  50. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  51. { Bits 8..11: modifiers }
  52. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  53. OT_TO = $00000200; { reverse effect in FADD, FSUB &c }
  54. OT_COLON = $00000400; { operand is followed by a colon }
  55. OT_MODIFIER_MASK = $00000F00;
  56. { Bits 12..15: type of operand }
  57. OT_REGISTER = $00001000;
  58. OT_IMMEDIATE = $00002000;
  59. OT_MEMORY = $0000C000; { always includes 'OT_REGMEM' bit as well }
  60. OT_REGMEM = $00008000; { for r/m, ie EA, operands }
  61. OT_TYPE_MASK = OT_REGISTER or OT_IMMEDIATE or OT_MEMORY or OT_REGMEM;
  62. OT_REGNORM = OT_REGISTER or OT_REGMEM; { 'normal' reg, qualifies as EA }
  63. { Bits 20..22, 24..26: register classes
  64. otf_* consts are not used alone, only to build other constants. }
  65. otf_reg_cdt = $00100000;
  66. otf_reg_gpr = $00200000;
  67. otf_reg_sreg = $00400000;
  68. otf_reg_fpu = $01000000;
  69. otf_reg_mmx = $02000000;
  70. otf_reg_xmm = $04000000;
  71. otf_reg_ymm = $08000000;
  72. { Bits 16..19: subclasses, meaning depends on classes field }
  73. otf_sub0 = $00010000;
  74. otf_sub1 = $00020000;
  75. otf_sub2 = $00040000;
  76. otf_sub3 = $00080000;
  77. OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
  78. OT_REG_TYPMASK = otf_reg_cdt or otf_reg_gpr or otf_reg_sreg or otf_reg_fpu or otf_reg_mmx or otf_reg_xmm or otf_reg_ymm;
  79. { register class 0: CRx, DRx and TRx }
  80. {$ifdef x86_64}
  81. OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS64;
  82. {$else x86_64}
  83. OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS32;
  84. {$endif x86_64}
  85. OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn }
  86. OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn }
  87. OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn }
  88. OT_REG_CR4 = OT_REG_CDT or otf_sub3; { CR4 (Pentium only) }
  89. { register class 1: general-purpose registers }
  90. OT_REG_GPR = OT_REGNORM or otf_reg_gpr;
  91. OT_RM_GPR = OT_REGMEM or otf_reg_gpr;
  92. OT_REG8 = OT_REG_GPR or OT_BITS8; { 8-bit GPR }
  93. OT_REG16 = OT_REG_GPR or OT_BITS16;
  94. OT_REG32 = OT_REG_GPR or OT_BITS32;
  95. OT_REG64 = OT_REG_GPR or OT_BITS64;
  96. { GPR subclass 0: accumulator: AL, AX, EAX or RAX }
  97. OT_REG_ACCUM = OT_REG_GPR or otf_sub0;
  98. OT_REG_AL = OT_REG_ACCUM or OT_BITS8;
  99. OT_REG_AX = OT_REG_ACCUM or OT_BITS16;
  100. OT_REG_EAX = OT_REG_ACCUM or OT_BITS32;
  101. {$ifdef x86_64}
  102. OT_REG_RAX = OT_REG_ACCUM or OT_BITS64;
  103. {$endif x86_64}
  104. { GPR subclass 1: counter: CL, CX, ECX or RCX }
  105. OT_REG_COUNT = OT_REG_GPR or otf_sub1;
  106. OT_REG_CL = OT_REG_COUNT or OT_BITS8;
  107. OT_REG_CX = OT_REG_COUNT or OT_BITS16;
  108. OT_REG_ECX = OT_REG_COUNT or OT_BITS32;
  109. {$ifdef x86_64}
  110. OT_REG_RCX = OT_REG_COUNT or OT_BITS64;
  111. {$endif x86_64}
  112. { GPR subclass 2: data register: DL, DX, EDX or RDX }
  113. OT_REG_DX = OT_REG_GPR or otf_sub2 or OT_BITS16;
  114. OT_REG_EDX = OT_REG_GPR or otf_sub2 or OT_BITS32;
  115. { register class 2: Segment registers }
  116. OT_REG_SREG = OT_REGISTER or otf_reg_sreg or OT_BITS16;
  117. OT_REG_CS = OT_REG_SREG or otf_sub0; { CS }
  118. OT_REG_DESS = OT_REG_SREG or otf_sub1; { DS, ES, SS (non-CS 86 registers) }
  119. OT_REG_FSGS = OT_REG_SREG or otf_sub2; { FS, GS (386 extended registers) }
  120. { register class 3: FPU registers }
  121. OT_FPUREG = OT_REGISTER or otf_reg_fpu;
  122. OT_FPU0 = OT_FPUREG or otf_sub0; { FPU stack register zero }
  123. { register class 4: MMX (both reg and r/m) }
  124. OT_MMXREG = OT_REGNORM or otf_reg_mmx;
  125. OT_MMXRM = OT_REGMEM or otf_reg_mmx;
  126. { register class 5: XMM (both reg and r/m) }
  127. OT_XMMREG = OT_REGNORM or otf_reg_xmm;
  128. OT_XMMRM = OT_REGMEM or otf_reg_xmm;
  129. OT_XMEM32 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS32;
  130. OT_XMEM64 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS64;
  131. { register class 5: XMM (both reg and r/m) }
  132. OT_YMMREG = OT_REGNORM or otf_reg_ymm;
  133. OT_YMMRM = OT_REGMEM or otf_reg_ymm;
  134. OT_YMEM32 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS32;
  135. OT_YMEM64 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS64;
  136. { Vector-Memory operands }
  137. OT_VMEM_ANY = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64;
  138. { Memory operands }
  139. OT_MEM8 = OT_MEMORY or OT_BITS8;
  140. OT_MEM16 = OT_MEMORY or OT_BITS16;
  141. OT_MEM32 = OT_MEMORY or OT_BITS32;
  142. OT_MEM64 = OT_MEMORY or OT_BITS64;
  143. OT_MEM128 = OT_MEMORY or OT_BITS128;
  144. OT_MEM256 = OT_MEMORY or OT_BITS256;
  145. OT_MEM80 = OT_MEMORY or OT_BITS80;
  146. OT_MEM_OFFS = OT_MEMORY or otf_sub0; { special type of EA }
  147. { simple [address] offset }
  148. { Matches any type of r/m operand }
  149. OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM;
  150. { Immediate operands }
  151. OT_IMM8 = OT_IMMEDIATE or OT_BITS8;
  152. OT_IMM16 = OT_IMMEDIATE or OT_BITS16;
  153. OT_IMM32 = OT_IMMEDIATE or OT_BITS32;
  154. OT_IMM64 = OT_IMMEDIATE or OT_BITS64;
  155. OT_ONENESS = otf_sub0; { special type of immediate operand }
  156. OT_UNITY = OT_IMMEDIATE or OT_ONENESS; { for shift/rotate instructions }
  157. { Size of the instruction table converted by nasmconv.pas }
  158. {$if defined(x86_64)}
  159. instabentries = {$i x8664nop.inc}
  160. {$elseif defined(i386)}
  161. instabentries = {$i i386nop.inc}
  162. {$elseif defined(i8086)}
  163. instabentries = {$i i8086nop.inc}
  164. {$endif}
  165. maxinfolen = 8;
  166. type
  167. { What an instruction can change. Needed for optimizer and spilling code.
  168. Note: The order of this enumeration is should not be changed! }
  169. TInsChange = (Ch_None,
  170. {Read from a register}
  171. Ch_REAX, Ch_RECX, Ch_REDX, Ch_REBX, Ch_RESP, Ch_REBP, Ch_RESI, Ch_REDI,
  172. {write from a register}
  173. Ch_WEAX, Ch_WECX, Ch_WEDX, Ch_WEBX, Ch_WESP, Ch_WEBP, Ch_WESI, Ch_WEDI,
  174. {read and write from/to a register}
  175. Ch_RWEAX, Ch_RWECX, Ch_RWEDX, Ch_RWEBX, Ch_RWESP, Ch_RWEBP, Ch_RWESI, Ch_RWEDI,
  176. {modify the contents of a register with the purpose of using
  177. this changed content afterwards (add/sub/..., but e.g. not rep
  178. or movsd)}
  179. Ch_MEAX, Ch_MECX, Ch_MEDX, Ch_MEBX, Ch_MESP, Ch_MEBP, Ch_MESI, Ch_MEDI,
  180. {read individual flag bits from the flags register}
  181. Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  182. {write individual flag bits to the flags register}
  183. Ch_WCarryFlag,Ch_WParityFlag,Ch_WAuxiliaryFlag,Ch_WZeroFlag,Ch_WSignFlag,Ch_WOverflowFlag,
  184. {set individual flag bits to 0 in the flags register}
  185. Ch_W0CarryFlag,Ch_W0ParityFlag,Ch_W0AuxiliaryFlag,Ch_W0ZeroFlag,Ch_W0SignFlag,Ch_W0OverflowFlag,
  186. {set individual flag bits to 1 in the flags register}
  187. Ch_W1CarryFlag,Ch_W1ParityFlag,Ch_W1AuxiliaryFlag,Ch_W1ZeroFlag,Ch_W1SignFlag,Ch_W1OverflowFlag,
  188. {write an undefined value to individual flag bits in the flags register}
  189. Ch_WUCarryFlag,Ch_WUParityFlag,Ch_WUAuxiliaryFlag,Ch_WUZeroFlag,Ch_WUSignFlag,Ch_WUOverflowFlag,
  190. {read and write flag bits}
  191. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  192. {more specialized flag bits (not considered part of NR_DEFAULTFLAGS by the compiler)}
  193. Ch_RDirFlag,Ch_W0DirFlag,Ch_W1DirFlag,Ch_W0IntFlag,Ch_W1IntFlag,
  194. {instruction reads flag bits, according to its condition (used by Jcc/SETcc/CMOVcc)}
  195. Ch_RFLAGScc,
  196. {read/write/read+write the entire flags/eflags/rflags register}
  197. Ch_RFlags, Ch_WFlags, Ch_RWFlags,
  198. Ch_FPU,
  199. Ch_Rop1, Ch_Wop1, Ch_RWop1, Ch_Mop1,
  200. Ch_Rop2, Ch_Wop2, Ch_RWop2, Ch_Mop2,
  201. Ch_Rop3, Ch_WOp3, Ch_RWOp3, Ch_Mop3,
  202. Ch_Rop4, Ch_WOp4, Ch_RWOp4, Ch_Mop4,
  203. { instruction doesn't read it's input register, in case both parameters
  204. are the same register (e.g. xor eax,eax; sub eax,eax; sbb eax,eax (reads flags only), etc.) }
  205. Ch_NoReadIfEqualRegs,
  206. Ch_RMemEDI,Ch_WMemEDI,
  207. Ch_All,
  208. { x86_64 registers }
  209. Ch_RRAX, Ch_RRCX, Ch_RRDX, Ch_RRBX, Ch_RRSP, Ch_RRBP, Ch_RRSI, Ch_RRDI,
  210. Ch_WRAX, Ch_WRCX, Ch_WRDX, Ch_WRBX, Ch_WRSP, Ch_WRBP, Ch_WRSI, Ch_WRDI,
  211. Ch_RWRAX, Ch_RWRCX, Ch_RWRDX, Ch_RWRBX, Ch_RWRSP, Ch_RWRBP, Ch_RWRSI, Ch_RWRDI,
  212. Ch_MRAX, Ch_MRCX, Ch_MRDX, Ch_MRBX, Ch_MRSP, Ch_MRBP, Ch_MRSI, Ch_MRDI
  213. );
  214. TInsProp = packed record
  215. Ch : set of TInsChange;
  216. end;
  217. TMemRefSizeInfo = (msiUnkown, msiUnsupported, msiNoSize,
  218. msiMultiple, msiMultiple8, msiMultiple16, msiMultiple32,
  219. msiMultiple64, msiMultiple128, msiMultiple256,
  220. msiMemRegSize, msiMemRegx16y32, msiMemRegx32y64, msiMemRegx64y128, msiMemRegx64y256,
  221. msiMem8, msiMem16, msiMem32, msiMem64, msiMem128, msiMem256,
  222. msiXMem32, msiXMem64, msiYMem32, msiYMem64,
  223. msiVMemMultiple, msiVMemRegSize);
  224. TConstSizeInfo = (csiUnkown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64);
  225. TInsTabMemRefSizeInfoRec = record
  226. MemRefSize : TMemRefSizeInfo;
  227. ExistsSSEAVX: boolean;
  228. ConstSize : TConstSizeInfo;
  229. end;
  230. const
  231. MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultiple8,
  232. msiMultiple16, msiMultiple32,
  233. msiMultiple64, msiMultiple128,
  234. msiMultiple256, msiVMemMultiple];
  235. MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64,
  236. msiVMemMultiple, msiVMemRegSize];
  237. InsProp : array[tasmop] of TInsProp =
  238. {$if defined(x86_64)}
  239. {$i x8664pro.inc}
  240. {$elseif defined(i386)}
  241. {$i i386prop.inc}
  242. {$elseif defined(i8086)}
  243. {$i i8086prop.inc}
  244. {$endif}
  245. type
  246. TOperandOrder = (op_intel,op_att);
  247. {Instruction flags }
  248. tinsflag = (
  249. { please keep these in order and in sync with IF_SMASK }
  250. IF_SM, { size match first two operands }
  251. IF_SM2,
  252. IF_SB, { unsized operands can't be non-byte }
  253. IF_SW, { unsized operands can't be non-word }
  254. IF_SD, { unsized operands can't be nondword }
  255. { unsized argument spec }
  256. { please keep these in order and in sync with IF_ARMASK }
  257. IF_AR0, { SB, SW, SD applies to argument 0 }
  258. IF_AR1, { SB, SW, SD applies to argument 1 }
  259. IF_AR2, { SB, SW, SD applies to argument 2 }
  260. IF_PRIV, { it's a privileged instruction }
  261. IF_SMM, { it's only valid in SMM }
  262. IF_PROT, { it's protected mode only }
  263. IF_NOX86_64, { removed instruction in x86_64 }
  264. IF_UNDOC, { it's an undocumented instruction }
  265. IF_FPU, { it's an FPU instruction }
  266. IF_MMX, { it's an MMX instruction }
  267. { it's a 3DNow! instruction }
  268. IF_3DNOW,
  269. { it's a SSE (KNI, MMX2) instruction }
  270. IF_SSE,
  271. { SSE2 instructions }
  272. IF_SSE2,
  273. { SSE3 instructions }
  274. IF_SSE3,
  275. { SSE64 instructions }
  276. IF_SSE64,
  277. { SVM instructions }
  278. IF_SVM,
  279. { SSE4 instructions }
  280. IF_SSE4,
  281. IF_SSSE3,
  282. IF_SSE41,
  283. IF_SSE42,
  284. IF_AVX,
  285. IF_AVX2,
  286. IF_BMI1,
  287. IF_BMI2,
  288. IF_16BITONLY,
  289. IF_FMA,
  290. IF_FMA4,
  291. IF_TSX,
  292. IF_RAND,
  293. IF_XSAVE,
  294. IF_PREFETCHWT1,
  295. { mask for processor level }
  296. { please keep these in order and in sync with IF_PLEVEL }
  297. IF_8086, { 8086 instruction }
  298. IF_186, { 186+ instruction }
  299. IF_286, { 286+ instruction }
  300. IF_386, { 386+ instruction }
  301. IF_486, { 486+ instruction }
  302. IF_PENT, { Pentium instruction }
  303. IF_P6, { P6 instruction }
  304. IF_KATMAI, { Katmai instructions }
  305. IF_WILLAMETTE, { Willamette instructions }
  306. IF_PRESCOTT, { Prescott instructions }
  307. IF_X86_64,
  308. IF_SANDYBRIDGE, { Sandybridge-specific instruction }
  309. IF_NEC, { NEC V20/V30 instruction }
  310. { the following are not strictly part of the processor level, because
  311. they are never used standalone, but always in combination with a
  312. separate processor level flag. Therefore, they use bits outside of
  313. IF_PLEVEL, otherwise they would mess up the processor level they're
  314. used in combination with.
  315. The following combinations are currently used:
  316. [IF_AMD, IF_P6],
  317. [IF_CYRIX, IF_486],
  318. [IF_CYRIX, IF_PENT],
  319. [IF_CYRIX, IF_P6] }
  320. IF_CYRIX, { Cyrix, Centaur or VIA-specific instruction }
  321. IF_AMD, { AMD-specific instruction }
  322. { added flags }
  323. IF_PRE, { it's a prefix instruction }
  324. IF_PASS2, { if the instruction can change in a second pass }
  325. IF_IMM4, { immediate operand is a nibble (must be in range [0..15]) }
  326. IF_IMM3 { immediate operand is a triad (must be in range [0..7]) }
  327. );
  328. tinsflags=set of tinsflag;
  329. const
  330. IF_SMASK=[IF_SM,IF_SM2,IF_SB,IF_SW,IF_SD];
  331. IF_ARMASK=[IF_AR0,IF_AR1,IF_AR2]; { mask for unsized argument spec }
  332. IF_PLEVEL=[IF_8086..IF_NEC]; { mask for processor level }
  333. type
  334. tinsentry=packed record
  335. opcode : tasmop;
  336. ops : byte;
  337. optypes : array[0..max_operands-1] of longint;
  338. code : array[0..maxinfolen] of char;
  339. flags : tinsflags;
  340. end;
  341. pinsentry=^tinsentry;
  342. { alignment for operator }
  343. tai_align = class(tai_align_abstract)
  344. reg : tregister;
  345. constructor create(b:byte);override;
  346. constructor create_op(b: byte; _op: byte);override;
  347. function calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;override;
  348. end;
  349. taicpu = class(tai_cpu_abstract_sym)
  350. opsize : topsize;
  351. constructor op_none(op : tasmop);
  352. constructor op_none(op : tasmop;_size : topsize);
  353. constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  354. constructor op_const(op : tasmop;_size : topsize;_op1 : aint);
  355. constructor op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  356. constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  357. constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  358. constructor op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  359. constructor op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  360. constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  361. constructor op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  362. constructor op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  363. constructor op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  364. constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  365. constructor op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  366. constructor op_ref_reg_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2,_op3 : tregister);
  367. constructor op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  368. constructor op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  369. constructor op_const_reg_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2, _op3, _op4 : tregister);
  370. { this is for Jmp instructions }
  371. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  372. constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  373. constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  374. constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  375. constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  376. procedure changeopsize(siz:topsize);
  377. function GetString:string;
  378. { This is a workaround for the GAS non commutative fpu instruction braindamage.
  379. Early versions of the UnixWare assembler had a bug where some fpu instructions
  380. were reversed and GAS still keeps this "feature" for compatibility.
  381. for details: http://sourceware.org/binutils/docs/as/i386_002dBugs.html#i386_002dBugs
  382. http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=372528
  383. http://en.wikibooks.org/wiki/X86_Assembly/GAS_Syntax#Caveats
  384. Since FPC is "GAS centric" due to its history it generates instructions with the same operand order so
  385. when generating output for other assemblers, the opcodes must be fixed before writing them.
  386. This function returns the fixed opcodes. Changing the opcodes permanently is no good idea
  387. because in case of smartlinking assembler is generated twice so at the second run wrong
  388. assembler is generated.
  389. }
  390. function FixNonCommutativeOpcodes: tasmop;
  391. private
  392. FOperandOrder : TOperandOrder;
  393. procedure init(_size : topsize); { this need to be called by all constructor }
  394. public
  395. { the next will reset all instructions that can change in pass 2 }
  396. procedure ResetPass1;override;
  397. procedure ResetPass2;override;
  398. function CheckIfValid:boolean;
  399. function Pass1(objdata:TObjData):longint;override;
  400. procedure Pass2(objdata:TObjData);override;
  401. procedure SetOperandOrder(order:TOperandOrder);
  402. function is_same_reg_move(regtype: Tregistertype):boolean;override;
  403. { register spilling code }
  404. function spilling_get_operation_type(opnr: longint): topertype;override;
  405. {$ifdef i8086}
  406. procedure loadsegsymbol(opidx:longint;s:tasmsymbol);
  407. {$endif i8086}
  408. private
  409. { next fields are filled in pass1, so pass2 is faster }
  410. insentry : PInsEntry;
  411. insoffset : longint;
  412. LastInsOffset : longint; { need to be public to be reset }
  413. inssize : shortint;
  414. {$ifdef x86_64}
  415. rex : byte;
  416. {$endif x86_64}
  417. function InsEnd:longint;
  418. procedure create_ot(objdata:TObjData);
  419. function Matches(p:PInsEntry):boolean;
  420. function calcsize(p:PInsEntry):shortint;
  421. procedure gencode(objdata:TObjData);
  422. function NeedAddrPrefix(opidx:byte):boolean;
  423. function NeedAddrPrefix:boolean;
  424. procedure write0x66prefix(objdata:TObjData);
  425. procedure write0x67prefix(objdata:TObjData);
  426. procedure Swapoperands;
  427. function FindInsentry(objdata:TObjData):boolean;
  428. end;
  429. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  430. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  431. function MemRefInfo(aAsmop: TAsmOp): TInsTabMemRefSizeInfoRec;
  432. procedure InitAsm;
  433. procedure DoneAsm;
  434. {*****************************************************************************
  435. External Symbol Chain
  436. used for agx86nsm and agx86int
  437. *****************************************************************************}
  438. type
  439. PExternChain = ^TExternChain;
  440. TExternChain = Record
  441. psym : pshortstring;
  442. is_defined : boolean;
  443. next : PExternChain;
  444. end;
  445. const
  446. FEC : PExternChain = nil;
  447. procedure AddSymbol(symname : string; defined : boolean);
  448. procedure FreeExternChainList;
  449. implementation
  450. uses
  451. cutils,
  452. globals,
  453. systems,
  454. itcpugas,
  455. cpuinfo;
  456. procedure AddSymbol(symname : string; defined : boolean);
  457. var
  458. EC : PExternChain;
  459. begin
  460. EC:=FEC;
  461. while assigned(EC) do
  462. begin
  463. if EC^.psym^=symname then
  464. begin
  465. if defined then
  466. EC^.is_defined:=true;
  467. exit;
  468. end;
  469. EC:=EC^.next;
  470. end;
  471. New(EC);
  472. EC^.next:=FEC;
  473. FEC:=EC;
  474. FEC^.psym:=stringdup(symname);
  475. FEC^.is_defined := defined;
  476. end;
  477. procedure FreeExternChainList;
  478. var
  479. EC : PExternChain;
  480. begin
  481. EC:=FEC;
  482. while assigned(EC) do
  483. begin
  484. FEC:=EC^.next;
  485. stringdispose(EC^.psym);
  486. Dispose(EC);
  487. EC:=FEC;
  488. end;
  489. end;
  490. {*****************************************************************************
  491. Instruction table
  492. *****************************************************************************}
  493. type
  494. TInsTabCache=array[TasmOp] of longint;
  495. PInsTabCache=^TInsTabCache;
  496. TInsTabMemRefSizeInfoCache=array[TasmOp] of TInsTabMemRefSizeInfoRec;
  497. PInsTabMemRefSizeInfoCache=^TInsTabMemRefSizeInfoCache;
  498. const
  499. {$if defined(x86_64)}
  500. InsTab:array[0..instabentries-1] of TInsEntry={$i x8664tab.inc}
  501. {$elseif defined(i386)}
  502. InsTab:array[0..instabentries-1] of TInsEntry={$i i386tab.inc}
  503. {$elseif defined(i8086)}
  504. InsTab:array[0..instabentries-1] of TInsEntry={$i i8086tab.inc}
  505. {$endif}
  506. var
  507. InsTabCache : PInsTabCache;
  508. InsTabMemRefSizeInfoCache: PInsTabMemRefSizeInfoCache;
  509. const
  510. {$if defined(x86_64)}
  511. { Intel style operands ! }
  512. opsize_2_type:array[0..2,topsize] of longint=(
  513. (OT_NONE,
  514. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
  515. OT_BITS16,OT_BITS32,OT_BITS64,
  516. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  517. OT_BITS64,
  518. OT_NEAR,OT_FAR,OT_SHORT,
  519. OT_NONE,
  520. OT_BITS128,
  521. OT_BITS256
  522. ),
  523. (OT_NONE,
  524. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,OT_BITS8,OT_BITS16,OT_BITS32,
  525. OT_BITS16,OT_BITS32,OT_BITS64,
  526. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  527. OT_BITS64,
  528. OT_NEAR,OT_FAR,OT_SHORT,
  529. OT_NONE,
  530. OT_BITS128,
  531. OT_BITS256
  532. ),
  533. (OT_NONE,
  534. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,
  535. OT_BITS16,OT_BITS32,OT_BITS64,
  536. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  537. OT_BITS64,
  538. OT_NEAR,OT_FAR,OT_SHORT,
  539. OT_NONE,
  540. OT_BITS128,
  541. OT_BITS256
  542. )
  543. );
  544. reg_ot_table : array[tregisterindex] of longint = (
  545. {$i r8664ot.inc}
  546. );
  547. {$elseif defined(i386)}
  548. { Intel style operands ! }
  549. opsize_2_type:array[0..2,topsize] of longint=(
  550. (OT_NONE,
  551. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  552. OT_BITS16,OT_BITS32,OT_BITS64,
  553. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  554. OT_BITS64,
  555. OT_NEAR,OT_FAR,OT_SHORT,
  556. OT_NONE,
  557. OT_BITS128,
  558. OT_BITS256
  559. ),
  560. (OT_NONE,
  561. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  562. OT_BITS16,OT_BITS32,OT_BITS64,
  563. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  564. OT_BITS64,
  565. OT_NEAR,OT_FAR,OT_SHORT,
  566. OT_NONE,
  567. OT_BITS128,
  568. OT_BITS256
  569. ),
  570. (OT_NONE,
  571. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  572. OT_BITS16,OT_BITS32,OT_BITS64,
  573. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  574. OT_BITS64,
  575. OT_NEAR,OT_FAR,OT_SHORT,
  576. OT_NONE,
  577. OT_BITS128,
  578. OT_BITS256
  579. )
  580. );
  581. reg_ot_table : array[tregisterindex] of longint = (
  582. {$i r386ot.inc}
  583. );
  584. {$elseif defined(i8086)}
  585. { Intel style operands ! }
  586. opsize_2_type:array[0..2,topsize] of longint=(
  587. (OT_NONE,
  588. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  589. OT_BITS16,OT_BITS32,OT_BITS64,
  590. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  591. OT_BITS64,
  592. OT_NEAR,OT_FAR,OT_SHORT,
  593. OT_NONE,
  594. OT_BITS128,
  595. OT_BITS256
  596. ),
  597. (OT_NONE,
  598. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  599. OT_BITS16,OT_BITS32,OT_BITS64,
  600. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  601. OT_BITS64,
  602. OT_NEAR,OT_FAR,OT_SHORT,
  603. OT_NONE,
  604. OT_BITS128,
  605. OT_BITS256
  606. ),
  607. (OT_NONE,
  608. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  609. OT_BITS16,OT_BITS32,OT_BITS64,
  610. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  611. OT_BITS64,
  612. OT_NEAR,OT_FAR,OT_SHORT,
  613. OT_NONE,
  614. OT_BITS128,
  615. OT_BITS256
  616. )
  617. );
  618. reg_ot_table : array[tregisterindex] of longint = (
  619. {$i r8086ot.inc}
  620. );
  621. {$endif}
  622. function MemRefInfo(aAsmop: TAsmOp): TInsTabMemRefSizeInfoRec;
  623. begin
  624. result := InsTabMemRefSizeInfoCache^[aAsmop];
  625. end;
  626. { Operation type for spilling code }
  627. type
  628. toperation_type_table=array[tasmop,0..Max_Operands] of topertype;
  629. var
  630. operation_type_table : ^toperation_type_table;
  631. {****************************************************************************
  632. TAI_ALIGN
  633. ****************************************************************************}
  634. constructor tai_align.create(b: byte);
  635. begin
  636. inherited create(b);
  637. reg:=NR_ECX;
  638. end;
  639. constructor tai_align.create_op(b: byte; _op: byte);
  640. begin
  641. inherited create_op(b,_op);
  642. reg:=NR_NO;
  643. end;
  644. function tai_align.calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;
  645. const
  646. { Updated according to
  647. Software Optimization Guide for AMD Family 15h Processors, Verison 3.08, January 2014
  648. and
  649. Intel 64 and IA-32 Architectures Software Developer’s Manual
  650. Volume 2B: Instruction Set Reference, N-Z, January 2015
  651. }
  652. alignarray_cmovcpus:array[0..10] of string[11]=(
  653. #$66#$66#$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  654. #$66#$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  655. #$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  656. #$0F#$1F#$84#$00#$00#$00#$00#$00,
  657. #$0F#$1F#$80#$00#$00#$00#$00,
  658. #$66#$0F#$1F#$44#$00#$00,
  659. #$0F#$1F#$44#$00#$00,
  660. #$0F#$1F#$40#$00,
  661. #$0F#$1F#$00,
  662. #$66#$90,
  663. #$90);
  664. {$ifdef i8086}
  665. alignarray:array[0..5] of string[8]=(
  666. #$90#$90#$90#$90#$90#$90#$90,
  667. #$90#$90#$90#$90#$90#$90,
  668. #$90#$90#$90#$90,
  669. #$90#$90#$90,
  670. #$90#$90,
  671. #$90);
  672. {$else i8086}
  673. alignarray:array[0..5] of string[8]=(
  674. #$8D#$B4#$26#$00#$00#$00#$00,
  675. #$8D#$B6#$00#$00#$00#$00,
  676. #$8D#$74#$26#$00,
  677. #$8D#$76#$00,
  678. #$89#$F6,
  679. #$90);
  680. {$endif i8086}
  681. var
  682. bufptr : pchar;
  683. j : longint;
  684. localsize: byte;
  685. begin
  686. inherited calculatefillbuf(buf,executable);
  687. if not(use_op) and executable then
  688. begin
  689. bufptr:=pchar(@buf);
  690. { fillsize may still be used afterwards, so don't modify }
  691. { e.g. writebytes(hp.calculatefillbuf(buf)^,hp.fillsize) }
  692. localsize:=fillsize;
  693. while (localsize>0) do
  694. begin
  695. {$ifndef i8086}
  696. if CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype] then
  697. begin
  698. for j:=low(alignarray_cmovcpus) to high(alignarray_cmovcpus) do
  699. if (localsize>=length(alignarray_cmovcpus[j])) then
  700. break;
  701. move(alignarray_cmovcpus[j][1],bufptr^,length(alignarray_cmovcpus[j]));
  702. inc(bufptr,length(alignarray_cmovcpus[j]));
  703. dec(localsize,length(alignarray_cmovcpus[j]));
  704. end
  705. else
  706. {$endif not i8086}
  707. begin
  708. for j:=low(alignarray) to high(alignarray) do
  709. if (localsize>=length(alignarray[j])) then
  710. break;
  711. move(alignarray[j][1],bufptr^,length(alignarray[j]));
  712. inc(bufptr,length(alignarray[j]));
  713. dec(localsize,length(alignarray[j]));
  714. end
  715. end;
  716. end;
  717. calculatefillbuf:=pchar(@buf);
  718. end;
  719. {*****************************************************************************
  720. Taicpu Constructors
  721. *****************************************************************************}
  722. procedure taicpu.changeopsize(siz:topsize);
  723. begin
  724. opsize:=siz;
  725. end;
  726. procedure taicpu.init(_size : topsize);
  727. begin
  728. { default order is att }
  729. FOperandOrder:=op_att;
  730. segprefix:=NR_NO;
  731. opsize:=_size;
  732. insentry:=nil;
  733. LastInsOffset:=-1;
  734. InsOffset:=0;
  735. InsSize:=0;
  736. end;
  737. constructor taicpu.op_none(op : tasmop);
  738. begin
  739. inherited create(op);
  740. init(S_NO);
  741. end;
  742. constructor taicpu.op_none(op : tasmop;_size : topsize);
  743. begin
  744. inherited create(op);
  745. init(_size);
  746. end;
  747. constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  748. begin
  749. inherited create(op);
  750. init(_size);
  751. ops:=1;
  752. loadreg(0,_op1);
  753. end;
  754. constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : aint);
  755. begin
  756. inherited create(op);
  757. init(_size);
  758. ops:=1;
  759. loadconst(0,_op1);
  760. end;
  761. constructor taicpu.op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  762. begin
  763. inherited create(op);
  764. init(_size);
  765. ops:=1;
  766. loadref(0,_op1);
  767. end;
  768. constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  769. begin
  770. inherited create(op);
  771. init(_size);
  772. ops:=2;
  773. loadreg(0,_op1);
  774. loadreg(1,_op2);
  775. end;
  776. constructor taicpu.op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  777. begin
  778. inherited create(op);
  779. init(_size);
  780. ops:=2;
  781. loadreg(0,_op1);
  782. loadconst(1,_op2);
  783. end;
  784. constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  785. begin
  786. inherited create(op);
  787. init(_size);
  788. ops:=2;
  789. loadreg(0,_op1);
  790. loadref(1,_op2);
  791. end;
  792. constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  793. begin
  794. inherited create(op);
  795. init(_size);
  796. ops:=2;
  797. loadconst(0,_op1);
  798. loadreg(1,_op2);
  799. end;
  800. constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  801. begin
  802. inherited create(op);
  803. init(_size);
  804. ops:=2;
  805. loadconst(0,_op1);
  806. loadconst(1,_op2);
  807. end;
  808. constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  809. begin
  810. inherited create(op);
  811. init(_size);
  812. ops:=2;
  813. loadconst(0,_op1);
  814. loadref(1,_op2);
  815. end;
  816. constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  817. begin
  818. inherited create(op);
  819. init(_size);
  820. ops:=2;
  821. loadref(0,_op1);
  822. loadreg(1,_op2);
  823. end;
  824. constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  825. begin
  826. inherited create(op);
  827. init(_size);
  828. ops:=3;
  829. loadreg(0,_op1);
  830. loadreg(1,_op2);
  831. loadreg(2,_op3);
  832. end;
  833. constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  834. begin
  835. inherited create(op);
  836. init(_size);
  837. ops:=3;
  838. loadconst(0,_op1);
  839. loadreg(1,_op2);
  840. loadreg(2,_op3);
  841. end;
  842. constructor taicpu.op_ref_reg_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2,_op3 : tregister);
  843. begin
  844. inherited create(op);
  845. init(_size);
  846. ops:=3;
  847. loadref(0,_op1);
  848. loadreg(1,_op2);
  849. loadreg(2,_op3);
  850. end;
  851. constructor taicpu.op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  852. begin
  853. inherited create(op);
  854. init(_size);
  855. ops:=3;
  856. loadconst(0,_op1);
  857. loadref(1,_op2);
  858. loadreg(2,_op3);
  859. end;
  860. constructor taicpu.op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  861. begin
  862. inherited create(op);
  863. init(_size);
  864. ops:=3;
  865. loadconst(0,_op1);
  866. loadreg(1,_op2);
  867. loadref(2,_op3);
  868. end;
  869. constructor taicpu.op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  870. begin
  871. inherited create(op);
  872. init(_size);
  873. ops:=3;
  874. loadreg(0,_op1);
  875. loadreg(1,_op2);
  876. loadref(2,_op3);
  877. end;
  878. constructor taicpu.op_const_reg_reg_reg(op : tasmop; _size : topsize; _op1 : aint; _op2, _op3, _op4 : tregister);
  879. begin
  880. inherited create(op);
  881. init(_size);
  882. ops:=4;
  883. loadconst(0,_op1);
  884. loadreg(1,_op2);
  885. loadreg(2,_op3);
  886. loadreg(3,_op4);
  887. end;
  888. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  889. begin
  890. inherited create(op);
  891. init(_size);
  892. condition:=cond;
  893. ops:=1;
  894. loadsymbol(0,_op1,0);
  895. end;
  896. constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  897. begin
  898. inherited create(op);
  899. init(_size);
  900. ops:=1;
  901. loadsymbol(0,_op1,0);
  902. end;
  903. constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  904. begin
  905. inherited create(op);
  906. init(_size);
  907. ops:=1;
  908. loadsymbol(0,_op1,_op1ofs);
  909. end;
  910. constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  911. begin
  912. inherited create(op);
  913. init(_size);
  914. ops:=2;
  915. loadsymbol(0,_op1,_op1ofs);
  916. loadreg(1,_op2);
  917. end;
  918. constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  919. begin
  920. inherited create(op);
  921. init(_size);
  922. ops:=2;
  923. loadsymbol(0,_op1,_op1ofs);
  924. loadref(1,_op2);
  925. end;
  926. function taicpu.GetString:string;
  927. var
  928. i : longint;
  929. s : string;
  930. addsize : boolean;
  931. begin
  932. s:='['+std_op2str[opcode];
  933. for i:=0 to ops-1 do
  934. begin
  935. with oper[i]^ do
  936. begin
  937. if i=0 then
  938. s:=s+' '
  939. else
  940. s:=s+',';
  941. { type }
  942. addsize:=false;
  943. if (ot and OT_XMMREG)=OT_XMMREG then
  944. s:=s+'xmmreg'
  945. else
  946. if (ot and OT_YMMREG)=OT_YMMREG then
  947. s:=s+'ymmreg'
  948. else
  949. if (ot and OT_MMXREG)=OT_MMXREG then
  950. s:=s+'mmxreg'
  951. else
  952. if (ot and OT_FPUREG)=OT_FPUREG then
  953. s:=s+'fpureg'
  954. else
  955. if (ot and OT_REGISTER)=OT_REGISTER then
  956. begin
  957. s:=s+'reg';
  958. addsize:=true;
  959. end
  960. else
  961. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  962. begin
  963. s:=s+'imm';
  964. addsize:=true;
  965. end
  966. else
  967. if (ot and OT_MEMORY)=OT_MEMORY then
  968. begin
  969. s:=s+'mem';
  970. addsize:=true;
  971. end
  972. else
  973. s:=s+'???';
  974. { size }
  975. if addsize then
  976. begin
  977. if (ot and OT_BITS8)<>0 then
  978. s:=s+'8'
  979. else
  980. if (ot and OT_BITS16)<>0 then
  981. s:=s+'16'
  982. else
  983. if (ot and OT_BITS32)<>0 then
  984. s:=s+'32'
  985. else
  986. if (ot and OT_BITS64)<>0 then
  987. s:=s+'64'
  988. else
  989. if (ot and OT_BITS128)<>0 then
  990. s:=s+'128'
  991. else
  992. if (ot and OT_BITS256)<>0 then
  993. s:=s+'256'
  994. else
  995. s:=s+'??';
  996. { signed }
  997. if (ot and OT_SIGNED)<>0 then
  998. s:=s+'s';
  999. end;
  1000. end;
  1001. end;
  1002. GetString:=s+']';
  1003. end;
  1004. procedure taicpu.Swapoperands;
  1005. var
  1006. p : POper;
  1007. begin
  1008. { Fix the operands which are in AT&T style and we need them in Intel style }
  1009. case ops of
  1010. 0,1:
  1011. ;
  1012. 2 : begin
  1013. { 0,1 -> 1,0 }
  1014. p:=oper[0];
  1015. oper[0]:=oper[1];
  1016. oper[1]:=p;
  1017. end;
  1018. 3 : begin
  1019. { 0,1,2 -> 2,1,0 }
  1020. p:=oper[0];
  1021. oper[0]:=oper[2];
  1022. oper[2]:=p;
  1023. end;
  1024. 4 : begin
  1025. { 0,1,2,3 -> 3,2,1,0 }
  1026. p:=oper[0];
  1027. oper[0]:=oper[3];
  1028. oper[3]:=p;
  1029. p:=oper[1];
  1030. oper[1]:=oper[2];
  1031. oper[2]:=p;
  1032. end;
  1033. else
  1034. internalerror(201108141);
  1035. end;
  1036. end;
  1037. procedure taicpu.SetOperandOrder(order:TOperandOrder);
  1038. begin
  1039. if FOperandOrder<>order then
  1040. begin
  1041. Swapoperands;
  1042. FOperandOrder:=order;
  1043. end;
  1044. end;
  1045. function taicpu.FixNonCommutativeOpcodes: tasmop;
  1046. begin
  1047. result:=opcode;
  1048. { we need ATT order }
  1049. SetOperandOrder(op_att);
  1050. if (
  1051. (ops=2) and
  1052. (oper[0]^.typ=top_reg) and
  1053. (oper[1]^.typ=top_reg) and
  1054. { if the first is ST and the second is also a register
  1055. it is necessarily ST1 .. ST7 }
  1056. ((oper[0]^.reg=NR_ST) or
  1057. (oper[0]^.reg=NR_ST0))
  1058. ) or
  1059. { ((ops=1) and
  1060. (oper[0]^.typ=top_reg) and
  1061. (oper[0]^.reg in [R_ST1..R_ST7])) or}
  1062. (ops=0) then
  1063. begin
  1064. if opcode=A_FSUBR then
  1065. result:=A_FSUB
  1066. else if opcode=A_FSUB then
  1067. result:=A_FSUBR
  1068. else if opcode=A_FDIVR then
  1069. result:=A_FDIV
  1070. else if opcode=A_FDIV then
  1071. result:=A_FDIVR
  1072. else if opcode=A_FSUBRP then
  1073. result:=A_FSUBP
  1074. else if opcode=A_FSUBP then
  1075. result:=A_FSUBRP
  1076. else if opcode=A_FDIVRP then
  1077. result:=A_FDIVP
  1078. else if opcode=A_FDIVP then
  1079. result:=A_FDIVRP;
  1080. end;
  1081. if (
  1082. (ops=1) and
  1083. (oper[0]^.typ=top_reg) and
  1084. (getregtype(oper[0]^.reg)=R_FPUREGISTER) and
  1085. (oper[0]^.reg<>NR_ST)
  1086. ) then
  1087. begin
  1088. if opcode=A_FSUBRP then
  1089. result:=A_FSUBP
  1090. else if opcode=A_FSUBP then
  1091. result:=A_FSUBRP
  1092. else if opcode=A_FDIVRP then
  1093. result:=A_FDIVP
  1094. else if opcode=A_FDIVP then
  1095. result:=A_FDIVRP;
  1096. end;
  1097. end;
  1098. {*****************************************************************************
  1099. Assembler
  1100. *****************************************************************************}
  1101. type
  1102. ea = packed record
  1103. sib_present : boolean;
  1104. bytes : byte;
  1105. size : byte;
  1106. modrm : byte;
  1107. sib : byte;
  1108. {$ifdef x86_64}
  1109. rex : byte;
  1110. {$endif x86_64}
  1111. end;
  1112. procedure taicpu.create_ot(objdata:TObjData);
  1113. {
  1114. this function will also fix some other fields which only needs to be once
  1115. }
  1116. var
  1117. i,l,relsize : longint;
  1118. currsym : TObjSymbol;
  1119. begin
  1120. if ops=0 then
  1121. exit;
  1122. { update oper[].ot field }
  1123. for i:=0 to ops-1 do
  1124. with oper[i]^ do
  1125. begin
  1126. case typ of
  1127. top_reg :
  1128. begin
  1129. ot:=reg_ot_table[findreg_by_number(reg)];
  1130. end;
  1131. top_ref :
  1132. begin
  1133. if (ref^.refaddr=addr_no)
  1134. {$ifdef i386}
  1135. or (
  1136. (ref^.refaddr in [addr_pic]) and
  1137. (ref^.base<>NR_NO)
  1138. )
  1139. {$endif i386}
  1140. {$ifdef x86_64}
  1141. or (
  1142. (ref^.refaddr in [addr_pic,addr_pic_no_got]) and
  1143. (ref^.base<>NR_NO)
  1144. )
  1145. {$endif x86_64}
  1146. then
  1147. begin
  1148. { create ot field }
  1149. if (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR = OT_REG_GPR) and
  1150. ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
  1151. (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG)
  1152. ) then
  1153. // AVX2 - vector-memory-referenz (e.g. vgatherdpd xmm0, [rax xmm1], xmm2)
  1154. ot := (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR) or
  1155. (reg_ot_table[findreg_by_number(ref^.index)])
  1156. else if (ref^.base = NR_NO) and
  1157. ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
  1158. (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG)
  1159. ) then
  1160. // AVX2 - vector-memory-referenz without base-register (e.g. vgatherdpd xmm0, [xmm1], xmm2)
  1161. ot := (OT_REG_GPR) or
  1162. (reg_ot_table[findreg_by_number(ref^.index)])
  1163. else if (ot and OT_SIZE_MASK)=0 then
  1164. ot:=OT_MEMORY_ANY or opsize_2_type[i,opsize]
  1165. else
  1166. ot:=OT_MEMORY_ANY or (ot and OT_SIZE_MASK);
  1167. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  1168. ot:=ot or OT_MEM_OFFS;
  1169. { fix scalefactor }
  1170. if (ref^.index=NR_NO) then
  1171. ref^.scalefactor:=0
  1172. else
  1173. if (ref^.scalefactor=0) then
  1174. ref^.scalefactor:=1;
  1175. end
  1176. else
  1177. begin
  1178. { Jumps use a relative offset which can be 8bit,
  1179. for other opcodes we always need to generate the full
  1180. 32bit address }
  1181. if assigned(objdata) and
  1182. is_jmp then
  1183. begin
  1184. currsym:=objdata.symbolref(ref^.symbol);
  1185. l:=ref^.offset;
  1186. {$push}
  1187. {$r-,q-} { disable also overflow as address returns a qword for x86_64 }
  1188. if assigned(currsym) then
  1189. inc(l,currsym.address);
  1190. {$pop}
  1191. { when it is a forward jump we need to compensate the
  1192. offset of the instruction since the previous time,
  1193. because the symbol address is then still using the
  1194. 'old-style' addressing.
  1195. For backwards jumps this is not required because the
  1196. address of the symbol is already adjusted to the
  1197. new offset }
  1198. if (l>InsOffset) and (LastInsOffset<>-1) then
  1199. inc(l,InsOffset-LastInsOffset);
  1200. { instruction size will then always become 2 (PFV) }
  1201. relsize:=(InsOffset+2)-l;
  1202. if (relsize>=-128) and (relsize<=127) and
  1203. (
  1204. not assigned(currsym) or
  1205. (currsym.objsection=objdata.currobjsec)
  1206. ) then
  1207. ot:=OT_IMM8 or OT_SHORT
  1208. else
  1209. {$ifdef i8086}
  1210. ot:=OT_IMM16 or OT_NEAR;
  1211. {$else i8086}
  1212. ot:=OT_IMM32 or OT_NEAR;
  1213. {$endif i8086}
  1214. end
  1215. else
  1216. {$ifdef i8086}
  1217. if opsize=S_FAR then
  1218. ot:=OT_IMM16 or OT_FAR
  1219. else
  1220. ot:=OT_IMM16 or OT_NEAR;
  1221. {$else i8086}
  1222. ot:=OT_IMM32 or OT_NEAR;
  1223. {$endif i8086}
  1224. end;
  1225. end;
  1226. top_local :
  1227. begin
  1228. if (ot and OT_SIZE_MASK)=0 then
  1229. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  1230. else
  1231. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1232. end;
  1233. top_const :
  1234. begin
  1235. // if opcode is a SSE or AVX-instruction then we need a
  1236. // special handling (opsize can different from const-size)
  1237. // (e.g. "pextrw reg/m16, xmmreg, imm8" =>> opsize (16 bit), const-size (8 bit)
  1238. if (InsTabMemRefSizeInfoCache^[opcode].ExistsSSEAVX) and
  1239. (not(InsTabMemRefSizeInfoCache^[opcode].ConstSize in [csiMultiple, csiUnkown])) then
  1240. begin
  1241. case InsTabMemRefSizeInfoCache^[opcode].ConstSize of
  1242. csiNoSize: ot := ot and (not(OT_SIZE_MASK)) or OT_IMMEDIATE;
  1243. csiMem8: ot := ot and (not(OT_SIZE_MASK)) or OT_IMMEDIATE or OT_BITS8;
  1244. csiMem16: ot := ot and (not(OT_SIZE_MASK)) or OT_IMMEDIATE or OT_BITS16;
  1245. csiMem32: ot := ot and (not(OT_SIZE_MASK)) or OT_IMMEDIATE or OT_BITS32;
  1246. csiMem64: ot := ot and (not(OT_SIZE_MASK)) or OT_IMMEDIATE or OT_BITS64;
  1247. end;
  1248. end
  1249. else
  1250. begin
  1251. { allow 2nd, 3rd or 4th operand being a constant and expect no size for shuf* etc. }
  1252. { further, allow AAD and AAM with imm. operand }
  1253. if (opsize=S_NO) and not((i in [1,2,3])
  1254. {$ifndef x86_64}
  1255. or ((i=0) and (opcode in [A_AAD,A_AAM]))
  1256. {$endif x86_64}
  1257. ) then
  1258. message(asmr_e_invalid_opcode_and_operand);
  1259. if
  1260. {$ifndef i8086}
  1261. (opsize<>S_W) and
  1262. {$endif not i8086}
  1263. (aint(val)>=-128) and (val<=127) then
  1264. ot:=OT_IMM8 or OT_SIGNED
  1265. else
  1266. ot:=OT_IMMEDIATE or opsize_2_type[i,opsize];
  1267. if (val=1) and (i=1) then
  1268. ot := ot or OT_ONENESS;
  1269. end;
  1270. end;
  1271. top_none :
  1272. begin
  1273. { generated when there was an error in the
  1274. assembler reader. It never happends when generating
  1275. assembler }
  1276. end;
  1277. else
  1278. internalerror(200402266);
  1279. end;
  1280. end;
  1281. end;
  1282. function taicpu.InsEnd:longint;
  1283. begin
  1284. InsEnd:=InsOffset+InsSize;
  1285. end;
  1286. function taicpu.Matches(p:PInsEntry):boolean;
  1287. { * IF_SM stands for Size Match: any operand whose size is not
  1288. * explicitly specified by the template is `really' intended to be
  1289. * the same size as the first size-specified operand.
  1290. * Non-specification is tolerated in the input instruction, but
  1291. * _wrong_ specification is not.
  1292. *
  1293. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1294. * three-operand instructions such as SHLD: it implies that the
  1295. * first two operands must match in size, but that the third is
  1296. * required to be _unspecified_.
  1297. *
  1298. * IF_SB invokes Size Byte: operands with unspecified size in the
  1299. * template are really bytes, and so no non-byte specification in
  1300. * the input instruction will be tolerated. IF_SW similarly invokes
  1301. * Size Word, and IF_SD invokes Size Doubleword.
  1302. *
  1303. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1304. * that any operand with unspecified size in the template is
  1305. * required to have unspecified size in the instruction too...)
  1306. }
  1307. var
  1308. insot,
  1309. currot,
  1310. i,j,asize,oprs : longint;
  1311. insflags:tinsflags;
  1312. siz : array[0..max_operands-1] of longint;
  1313. begin
  1314. result:=false;
  1315. { Check the opcode and operands }
  1316. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1317. exit;
  1318. {$ifdef i8086}
  1319. { On i8086, we need to skip the i386+ version of Jcc near, if the target
  1320. cpu is earlier than 386. There's another entry, later in the table for
  1321. i8086, which simulates it with i8086 instructions:
  1322. JNcc short +3
  1323. JMP near target }
  1324. if (p^.opcode=A_Jcc) and (current_settings.cputype<cpu_386) and
  1325. (IF_386 in p^.flags) then
  1326. exit;
  1327. {$endif i8086}
  1328. for i:=0 to p^.ops-1 do
  1329. begin
  1330. insot:=p^.optypes[i];
  1331. currot:=oper[i]^.ot;
  1332. { Check the operand flags }
  1333. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  1334. exit;
  1335. { Check if the passed operand size matches with one of
  1336. the supported operand sizes }
  1337. if ((insot and OT_SIZE_MASK)<>0) and
  1338. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  1339. exit;
  1340. { "far" matches only with "far" }
  1341. if (insot and OT_FAR)<>(currot and OT_FAR) then
  1342. exit;
  1343. end;
  1344. { Check operand sizes }
  1345. insflags:=p^.flags;
  1346. if (insflags*IF_SMASK)<>[] then
  1347. begin
  1348. { as default an untyped size can get all the sizes, this is different
  1349. from nasm, but else we need to do a lot checking which opcodes want
  1350. size or not with the automatic size generation }
  1351. asize:=-1;
  1352. if IF_SB in insflags then
  1353. asize:=OT_BITS8
  1354. else if IF_SW in insflags then
  1355. asize:=OT_BITS16
  1356. else if IF_SD in insflags then
  1357. asize:=OT_BITS32;
  1358. if insflags*IF_ARMASK<>[] then
  1359. begin
  1360. siz[0]:=-1;
  1361. siz[1]:=-1;
  1362. siz[2]:=-1;
  1363. if IF_AR0 in insflags then
  1364. siz[0]:=asize
  1365. else if IF_AR1 in insflags then
  1366. siz[1]:=asize
  1367. else if IF_AR2 in insflags then
  1368. siz[2]:=asize
  1369. else
  1370. internalerror(2017092101);
  1371. end
  1372. else
  1373. begin
  1374. siz[0]:=asize;
  1375. siz[1]:=asize;
  1376. siz[2]:=asize;
  1377. end;
  1378. if insflags*[IF_SM,IF_SM2]<>[] then
  1379. begin
  1380. if IF_SM2 in insflags then
  1381. oprs:=2
  1382. else
  1383. oprs:=p^.ops;
  1384. for i:=0 to oprs-1 do
  1385. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1386. begin
  1387. for j:=0 to oprs-1 do
  1388. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1389. break;
  1390. end;
  1391. end
  1392. else
  1393. oprs:=2;
  1394. { Check operand sizes }
  1395. for i:=0 to p^.ops-1 do
  1396. begin
  1397. insot:=p^.optypes[i];
  1398. currot:=oper[i]^.ot;
  1399. if ((insot and OT_SIZE_MASK)=0) and
  1400. ((currot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1401. { Immediates can always include smaller size }
  1402. ((currot and OT_IMMEDIATE)=0) and
  1403. (((insot and OT_SIZE_MASK) or siz[i])<(currot and OT_SIZE_MASK)) then
  1404. exit;
  1405. if (insot and OT_FAR)<>(currot and OT_FAR) then
  1406. exit;
  1407. end;
  1408. end;
  1409. if (InsTabMemRefSizeInfoCache^[opcode].MemRefSize in MemRefMultiples) and
  1410. (InsTabMemRefSizeInfoCache^[opcode].ExistsSSEAVX) then
  1411. begin
  1412. for i:=0 to p^.ops-1 do
  1413. begin
  1414. insot:=p^.optypes[i];
  1415. if ((insot and OT_XMMRM) = OT_XMMRM) OR
  1416. ((insot and OT_YMMRM) = OT_YMMRM) then
  1417. begin
  1418. if (insot and OT_SIZE_MASK) = 0 then
  1419. begin
  1420. case insot and (OT_XMMRM or OT_YMMRM) of
  1421. OT_XMMRM: insot := insot or OT_BITS128;
  1422. OT_YMMRM: insot := insot or OT_BITS256;
  1423. end;
  1424. end;
  1425. end;
  1426. currot:=oper[i]^.ot;
  1427. { Check the operand flags }
  1428. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  1429. exit;
  1430. { Check if the passed operand size matches with one of
  1431. the supported operand sizes }
  1432. if ((insot and OT_SIZE_MASK)<>0) and
  1433. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  1434. exit;
  1435. end;
  1436. end;
  1437. result:=true;
  1438. end;
  1439. procedure taicpu.ResetPass1;
  1440. begin
  1441. { we need to reset everything here, because the choosen insentry
  1442. can be invalid for a new situation where the previously optimized
  1443. insentry is not correct }
  1444. InsEntry:=nil;
  1445. InsSize:=0;
  1446. LastInsOffset:=-1;
  1447. end;
  1448. procedure taicpu.ResetPass2;
  1449. begin
  1450. { we are here in a second pass, check if the instruction can be optimized }
  1451. if assigned(InsEntry) and
  1452. (IF_PASS2 in InsEntry^.flags) then
  1453. begin
  1454. InsEntry:=nil;
  1455. InsSize:=0;
  1456. end;
  1457. LastInsOffset:=-1;
  1458. end;
  1459. function taicpu.CheckIfValid:boolean;
  1460. begin
  1461. result:=FindInsEntry(nil);
  1462. end;
  1463. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1464. var
  1465. i : longint;
  1466. begin
  1467. result:=false;
  1468. { Things which may only be done once, not when a second pass is done to
  1469. optimize }
  1470. if (Insentry=nil) or (IF_PASS2 in InsEntry^.flags) then
  1471. begin
  1472. current_filepos:=fileinfo;
  1473. { We need intel style operands }
  1474. SetOperandOrder(op_intel);
  1475. { create the .ot fields }
  1476. create_ot(objdata);
  1477. { set the file postion }
  1478. end
  1479. else
  1480. begin
  1481. { we've already an insentry so it's valid }
  1482. result:=true;
  1483. exit;
  1484. end;
  1485. { Lookup opcode in the table }
  1486. InsSize:=-1;
  1487. i:=instabcache^[opcode];
  1488. if i=-1 then
  1489. begin
  1490. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1491. exit;
  1492. end;
  1493. insentry:=@instab[i];
  1494. while (insentry^.opcode=opcode) do
  1495. begin
  1496. if matches(insentry) then
  1497. begin
  1498. result:=true;
  1499. exit;
  1500. end;
  1501. inc(insentry);
  1502. end;
  1503. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1504. { No instruction found, set insentry to nil and inssize to -1 }
  1505. insentry:=nil;
  1506. inssize:=-1;
  1507. end;
  1508. function taicpu.Pass1(objdata:TObjData):longint;
  1509. begin
  1510. Pass1:=0;
  1511. { Save the old offset and set the new offset }
  1512. InsOffset:=ObjData.CurrObjSec.Size;
  1513. { Error? }
  1514. if (Insentry=nil) and (InsSize=-1) then
  1515. exit;
  1516. { set the file postion }
  1517. current_filepos:=fileinfo;
  1518. { Get InsEntry }
  1519. if FindInsEntry(ObjData) then
  1520. begin
  1521. { Calculate instruction size }
  1522. InsSize:=calcsize(insentry);
  1523. if segprefix<>NR_NO then
  1524. inc(InsSize);
  1525. if NeedAddrPrefix then
  1526. inc(InsSize);
  1527. { Fix opsize if size if forced }
  1528. if insentry^.flags*[IF_SB,IF_SW,IF_SD]<>[] then
  1529. begin
  1530. if insentry^.flags*IF_ARMASK=[] then
  1531. begin
  1532. if IF_SB in insentry^.flags then
  1533. begin
  1534. if opsize=S_NO then
  1535. opsize:=S_B;
  1536. end
  1537. else if IF_SW in insentry^.flags then
  1538. begin
  1539. if opsize=S_NO then
  1540. opsize:=S_W;
  1541. end
  1542. else if IF_SD in insentry^.flags then
  1543. begin
  1544. if opsize=S_NO then
  1545. opsize:=S_L;
  1546. end;
  1547. end;
  1548. end;
  1549. LastInsOffset:=InsOffset;
  1550. Pass1:=InsSize;
  1551. exit;
  1552. end;
  1553. LastInsOffset:=-1;
  1554. end;
  1555. const
  1556. segprefixes: array[NR_ES..NR_GS] of Byte=(
  1557. // es cs ss ds fs gs
  1558. $26, $2E, $36, $3E, $64, $65
  1559. );
  1560. procedure taicpu.Pass2(objdata:TObjData);
  1561. begin
  1562. { error in pass1 ? }
  1563. if insentry=nil then
  1564. exit;
  1565. current_filepos:=fileinfo;
  1566. { Segment override }
  1567. if (segprefix>=NR_ES) and (segprefix<=NR_GS) then
  1568. begin
  1569. {$ifdef i8086}
  1570. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) and
  1571. ((segprefix=NR_FS) or (segprefix=NR_GS)) then
  1572. Message(asmw_e_instruction_not_supported_by_cpu);
  1573. {$endif i8086}
  1574. objdata.writebytes(segprefixes[segprefix],1);
  1575. { fix the offset for GenNode }
  1576. inc(InsOffset);
  1577. end
  1578. else if segprefix<>NR_NO then
  1579. InternalError(201001071);
  1580. { Address size prefix? }
  1581. if NeedAddrPrefix then
  1582. begin
  1583. write0x67prefix(objdata);
  1584. { fix the offset for GenNode }
  1585. inc(InsOffset);
  1586. end;
  1587. { Generate the instruction }
  1588. GenCode(objdata);
  1589. end;
  1590. function is_16_bit_ref(const input:toper):boolean;
  1591. var
  1592. ir,br : Tregister;
  1593. isub,bsub : tsubregister;
  1594. has_16_bit_regs: Boolean;
  1595. begin
  1596. if (input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)=R_MMREGISTER) then
  1597. exit(false);
  1598. ir:=input.ref^.index;
  1599. br:=input.ref^.base;
  1600. isub:=getsubreg(ir);
  1601. bsub:=getsubreg(br);
  1602. { it's a direct address }
  1603. if (br=NR_NO) and (ir=NR_NO) then
  1604. begin
  1605. {$ifdef i8086}
  1606. result:=true;
  1607. {$else i8086}
  1608. result:=false;
  1609. {$endif}
  1610. end
  1611. else
  1612. { it's an indirection }
  1613. begin
  1614. result := ((ir<>NR_NO) and (isub=R_SUBW)) or
  1615. ((br<>NR_NO) and (bsub=R_SUBW));
  1616. end;
  1617. end;
  1618. function taicpu.needaddrprefix(opidx:byte):boolean;
  1619. begin
  1620. {$if defined(x86_64)}
  1621. result:=(oper[opidx]^.typ=top_ref) and
  1622. (oper[opidx]^.ref^.refaddr=addr_no) and
  1623. {$ifdef x86_64}
  1624. (oper[opidx]^.ref^.base<>NR_RIP) and
  1625. {$endif x86_64}
  1626. (
  1627. (
  1628. (oper[opidx]^.ref^.index<>NR_NO) and
  1629. (getsubreg(oper[opidx]^.ref^.index)<>R_SUBADDR)
  1630. ) or
  1631. (
  1632. (oper[opidx]^.ref^.base<>NR_NO) and
  1633. (getsubreg(oper[opidx]^.ref^.base)<>R_SUBADDR)
  1634. )
  1635. );
  1636. {$elseif defined(i386)}
  1637. result:=(oper[opidx]^.typ=top_ref) and is_16_bit_ref(oper[opidx]^);
  1638. {$elseif defined(i8086)}
  1639. result:=(oper[opidx]^.typ=top_ref) and not is_16_bit_ref(oper[opidx]^);
  1640. {$endif}
  1641. end;
  1642. function taicpu.NeedAddrPrefix:boolean;
  1643. var
  1644. i: Integer;
  1645. begin
  1646. for i:=0 to ops-1 do
  1647. if needaddrprefix(i) then
  1648. exit(true);
  1649. result:=false;
  1650. end;
  1651. procedure badreg(r:Tregister);
  1652. begin
  1653. Message1(asmw_e_invalid_register,generic_regname(r));
  1654. end;
  1655. function regval(r:Tregister):byte;
  1656. const
  1657. intsupreg2opcode: array[0..7] of byte=
  1658. // ax cx dx bx si di bp sp -- in x86reg.dat
  1659. // ax cx dx bx sp bp si di -- needed order
  1660. (0, 1, 2, 3, 6, 7, 5, 4);
  1661. maxsupreg: array[tregistertype] of tsuperregister=
  1662. {$ifdef x86_64}
  1663. (0, 16, 9, 8, 16, 32, 0, 0);
  1664. {$else x86_64}
  1665. (0, 8, 9, 8, 8, 32, 0, 0);
  1666. {$endif x86_64}
  1667. var
  1668. rs: tsuperregister;
  1669. rt: tregistertype;
  1670. begin
  1671. rs:=getsupreg(r);
  1672. rt:=getregtype(r);
  1673. if (rs>=maxsupreg[rt]) then
  1674. badreg(r);
  1675. result:=rs and 7;
  1676. if (rt=R_INTREGISTER) then
  1677. begin
  1678. if (rs<8) then
  1679. result:=intsupreg2opcode[rs];
  1680. if getsubreg(r)=R_SUBH then
  1681. inc(result,4);
  1682. end;
  1683. end;
  1684. {$if defined(x86_64)}
  1685. function rexbits(r: tregister): byte;
  1686. begin
  1687. result:=0;
  1688. case getregtype(r) of
  1689. R_INTREGISTER:
  1690. if (getsupreg(r)>=RS_R8) then
  1691. { Either B,X or R bits can be set, depending on register role in instruction.
  1692. Set all three bits here, caller will discard unnecessary ones. }
  1693. result:=result or $47
  1694. else if (getsubreg(r)=R_SUBL) and
  1695. (getsupreg(r) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  1696. result:=result or $40
  1697. else if (getsubreg(r)=R_SUBH) then
  1698. { Not an actual REX bit, used to detect incompatible usage of
  1699. AH/BH/CH/DH }
  1700. result:=result or $80;
  1701. R_MMREGISTER:
  1702. if getsupreg(r)>=RS_XMM8 then
  1703. result:=result or $47;
  1704. end;
  1705. end;
  1706. function process_ea_ref_64_32(const input:toper;var output:ea;rfield:longint):boolean;
  1707. var
  1708. sym : tasmsymbol;
  1709. md,s : byte;
  1710. base,index,scalefactor,
  1711. o : longint;
  1712. ir,br : Tregister;
  1713. isub,bsub : tsubregister;
  1714. begin
  1715. result:=false;
  1716. ir:=input.ref^.index;
  1717. br:=input.ref^.base;
  1718. isub:=getsubreg(ir);
  1719. bsub:=getsubreg(br);
  1720. s:=input.ref^.scalefactor;
  1721. o:=input.ref^.offset;
  1722. sym:=input.ref^.symbol;
  1723. //if ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER)) or
  1724. // ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  1725. if ((ir<>NR_NO) and (getregtype(ir)=R_MMREGISTER) and (br<>NR_NO) and (getregtype(br)<>R_INTREGISTER)) or // vector memory (AVX2)
  1726. ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER) and (getregtype(ir)<>R_MMREGISTER)) or
  1727. ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  1728. internalerror(200301081);
  1729. { it's direct address }
  1730. if (br=NR_NO) and (ir=NR_NO) then
  1731. begin
  1732. output.sib_present:=true;
  1733. output.bytes:=4;
  1734. output.modrm:=4 or (rfield shl 3);
  1735. output.sib:=$25;
  1736. end
  1737. else if (br=NR_RIP) and (ir=NR_NO) then
  1738. begin
  1739. { rip based }
  1740. output.sib_present:=false;
  1741. output.bytes:=4;
  1742. output.modrm:=5 or (rfield shl 3);
  1743. end
  1744. else
  1745. { it's an indirection }
  1746. begin
  1747. { 16 bit? }
  1748. if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY]) and
  1749. (br<>NR_NO) and (bsub=R_SUBQ)
  1750. ) then
  1751. begin
  1752. // vector memory (AVX2) =>> ignore
  1753. end
  1754. else if ((ir<>NR_NO) and (isub<>R_SUBQ) and (isub<>R_SUBD)) or
  1755. ((br<>NR_NO) and (bsub<>R_SUBQ) and (bsub<>R_SUBD)) then
  1756. begin
  1757. message(asmw_e_16bit_32bit_not_supported);
  1758. end;
  1759. { wrong, for various reasons }
  1760. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1761. exit;
  1762. output.rex:=output.rex or (rexbits(br) and $F1) or (rexbits(ir) and $F2);
  1763. result:=true;
  1764. { base }
  1765. case br of
  1766. NR_R8D,
  1767. NR_EAX,
  1768. NR_R8,
  1769. NR_RAX : base:=0;
  1770. NR_R9D,
  1771. NR_ECX,
  1772. NR_R9,
  1773. NR_RCX : base:=1;
  1774. NR_R10D,
  1775. NR_EDX,
  1776. NR_R10,
  1777. NR_RDX : base:=2;
  1778. NR_R11D,
  1779. NR_EBX,
  1780. NR_R11,
  1781. NR_RBX : base:=3;
  1782. NR_R12D,
  1783. NR_ESP,
  1784. NR_R12,
  1785. NR_RSP : base:=4;
  1786. NR_R13D,
  1787. NR_EBP,
  1788. NR_R13,
  1789. NR_NO,
  1790. NR_RBP : base:=5;
  1791. NR_R14D,
  1792. NR_ESI,
  1793. NR_R14,
  1794. NR_RSI : base:=6;
  1795. NR_R15D,
  1796. NR_EDI,
  1797. NR_R15,
  1798. NR_RDI : base:=7;
  1799. else
  1800. exit;
  1801. end;
  1802. { index }
  1803. case ir of
  1804. NR_R8D,
  1805. NR_EAX,
  1806. NR_R8,
  1807. NR_RAX,
  1808. NR_XMM0,
  1809. NR_XMM8,
  1810. NR_YMM0,
  1811. NR_YMM8 : index:=0;
  1812. NR_R9D,
  1813. NR_ECX,
  1814. NR_R9,
  1815. NR_RCX,
  1816. NR_XMM1,
  1817. NR_XMM9,
  1818. NR_YMM1,
  1819. NR_YMM9 : index:=1;
  1820. NR_R10D,
  1821. NR_EDX,
  1822. NR_R10,
  1823. NR_RDX,
  1824. NR_XMM2,
  1825. NR_XMM10,
  1826. NR_YMM2,
  1827. NR_YMM10 : index:=2;
  1828. NR_R11D,
  1829. NR_EBX,
  1830. NR_R11,
  1831. NR_RBX,
  1832. NR_XMM3,
  1833. NR_XMM11,
  1834. NR_YMM3,
  1835. NR_YMM11 : index:=3;
  1836. NR_R12D,
  1837. NR_ESP,
  1838. NR_R12,
  1839. NR_NO,
  1840. NR_XMM4,
  1841. NR_XMM12,
  1842. NR_YMM4,
  1843. NR_YMM12 : index:=4;
  1844. NR_R13D,
  1845. NR_EBP,
  1846. NR_R13,
  1847. NR_RBP,
  1848. NR_XMM5,
  1849. NR_XMM13,
  1850. NR_YMM5,
  1851. NR_YMM13: index:=5;
  1852. NR_R14D,
  1853. NR_ESI,
  1854. NR_R14,
  1855. NR_RSI,
  1856. NR_XMM6,
  1857. NR_XMM14,
  1858. NR_YMM6,
  1859. NR_YMM14: index:=6;
  1860. NR_R15D,
  1861. NR_EDI,
  1862. NR_R15,
  1863. NR_RDI,
  1864. NR_XMM7,
  1865. NR_XMM15,
  1866. NR_YMM7,
  1867. NR_YMM15: index:=7;
  1868. else
  1869. exit;
  1870. end;
  1871. case s of
  1872. 0,
  1873. 1 : scalefactor:=0;
  1874. 2 : scalefactor:=1;
  1875. 4 : scalefactor:=2;
  1876. 8 : scalefactor:=3;
  1877. else
  1878. exit;
  1879. end;
  1880. { If rbp or r13 is used we must always include an offset }
  1881. if (br=NR_NO) or
  1882. ((br<>NR_RBP) and (br<>NR_R13) and (br<>NR_EBP) and (br<>NR_R13D) and (o=0) and (sym=nil)) then
  1883. md:=0
  1884. else
  1885. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1886. md:=1
  1887. else
  1888. md:=2;
  1889. if (br=NR_NO) or (md=2) then
  1890. output.bytes:=4
  1891. else
  1892. output.bytes:=md;
  1893. { SIB needed ? }
  1894. if (ir=NR_NO) and (br<>NR_RSP) and (br<>NR_R12) and (br<>NR_ESP) and (br<>NR_R12D) then
  1895. begin
  1896. output.sib_present:=false;
  1897. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  1898. end
  1899. else
  1900. begin
  1901. output.sib_present:=true;
  1902. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  1903. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1904. end;
  1905. end;
  1906. output.size:=1+ord(output.sib_present)+output.bytes;
  1907. result:=true;
  1908. end;
  1909. {$elseif defined(i386) or defined(i8086)}
  1910. function process_ea_ref_32(const input:toper;out output:ea;rfield:longint):boolean;
  1911. var
  1912. sym : tasmsymbol;
  1913. md,s : byte;
  1914. base,index,scalefactor,
  1915. o : longint;
  1916. ir,br : Tregister;
  1917. isub,bsub : tsubregister;
  1918. begin
  1919. result:=false;
  1920. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)=R_MMREGISTER) and (input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) or // vector memory (AVX2)
  1921. ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER) and (getregtype(input.ref^.index)<>R_MMREGISTER)) or
  1922. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  1923. internalerror(200301081);
  1924. ir:=input.ref^.index;
  1925. br:=input.ref^.base;
  1926. isub:=getsubreg(ir);
  1927. bsub:=getsubreg(br);
  1928. s:=input.ref^.scalefactor;
  1929. o:=input.ref^.offset;
  1930. sym:=input.ref^.symbol;
  1931. { it's direct address }
  1932. if (br=NR_NO) and (ir=NR_NO) then
  1933. begin
  1934. { it's a pure offset }
  1935. output.sib_present:=false;
  1936. output.bytes:=4;
  1937. output.modrm:=5 or (rfield shl 3);
  1938. end
  1939. else
  1940. { it's an indirection }
  1941. begin
  1942. { 16 bit address? }
  1943. if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY]) and
  1944. (br<>NR_NO) and (bsub=R_SUBD)
  1945. ) then
  1946. begin
  1947. // vector memory (AVX2) =>> ignore
  1948. end
  1949. else if ((ir<>NR_NO) and (isub<>R_SUBD)) or
  1950. ((br<>NR_NO) and (bsub<>R_SUBD)) then
  1951. message(asmw_e_16bit_not_supported);
  1952. {$ifdef OPTEA}
  1953. { make single reg base }
  1954. if (br=NR_NO) and (s=1) then
  1955. begin
  1956. br:=ir;
  1957. ir:=NR_NO;
  1958. end;
  1959. { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX }
  1960. if (br=NR_NO) and
  1961. (((s=2) and (ir<>NR_ESP)) or
  1962. (s=3) or (s=5) or (s=9)) then
  1963. begin
  1964. br:=ir;
  1965. dec(s);
  1966. end;
  1967. { swap ESP into base if scalefactor is 1 }
  1968. if (s=1) and (ir=NR_ESP) then
  1969. begin
  1970. ir:=br;
  1971. br:=NR_ESP;
  1972. end;
  1973. {$endif OPTEA}
  1974. { wrong, for various reasons }
  1975. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1976. exit;
  1977. { base }
  1978. case br of
  1979. NR_EAX : base:=0;
  1980. NR_ECX : base:=1;
  1981. NR_EDX : base:=2;
  1982. NR_EBX : base:=3;
  1983. NR_ESP : base:=4;
  1984. NR_NO,
  1985. NR_EBP : base:=5;
  1986. NR_ESI : base:=6;
  1987. NR_EDI : base:=7;
  1988. else
  1989. exit;
  1990. end;
  1991. { index }
  1992. case ir of
  1993. NR_EAX,
  1994. NR_XMM0,
  1995. NR_YMM0: index:=0;
  1996. NR_ECX,
  1997. NR_XMM1,
  1998. NR_YMM1: index:=1;
  1999. NR_EDX,
  2000. NR_XMM2,
  2001. NR_YMM2: index:=2;
  2002. NR_EBX,
  2003. NR_XMM3,
  2004. NR_YMM3: index:=3;
  2005. NR_NO,
  2006. NR_XMM4,
  2007. NR_YMM4: index:=4;
  2008. NR_EBP,
  2009. NR_XMM5,
  2010. NR_YMM5: index:=5;
  2011. NR_ESI,
  2012. NR_XMM6,
  2013. NR_YMM6: index:=6;
  2014. NR_EDI,
  2015. NR_XMM7,
  2016. NR_YMM7: index:=7;
  2017. else
  2018. exit;
  2019. end;
  2020. case s of
  2021. 0,
  2022. 1 : scalefactor:=0;
  2023. 2 : scalefactor:=1;
  2024. 4 : scalefactor:=2;
  2025. 8 : scalefactor:=3;
  2026. else
  2027. exit;
  2028. end;
  2029. if (br=NR_NO) or
  2030. ((br<>NR_EBP) and (o=0) and (sym=nil)) then
  2031. md:=0
  2032. else
  2033. if ((o>=-128) and (o<=127) and (sym=nil)) then
  2034. md:=1
  2035. else
  2036. md:=2;
  2037. if (br=NR_NO) or (md=2) then
  2038. output.bytes:=4
  2039. else
  2040. output.bytes:=md;
  2041. { SIB needed ? }
  2042. if (ir=NR_NO) and (br<>NR_ESP) then
  2043. begin
  2044. output.sib_present:=false;
  2045. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or base;
  2046. end
  2047. else
  2048. begin
  2049. output.sib_present:=true;
  2050. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or 4;
  2051. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  2052. end;
  2053. end;
  2054. if output.sib_present then
  2055. output.size:=2+output.bytes
  2056. else
  2057. output.size:=1+output.bytes;
  2058. result:=true;
  2059. end;
  2060. procedure maybe_swap_index_base(var br,ir:Tregister);
  2061. var
  2062. tmpreg: Tregister;
  2063. begin
  2064. if ((br=NR_NO) or (br=NR_SI) or (br=NR_DI)) and
  2065. ((ir=NR_NO) or (ir=NR_BP) or (ir=NR_BX)) then
  2066. begin
  2067. tmpreg:=br;
  2068. br:=ir;
  2069. ir:=tmpreg;
  2070. end;
  2071. end;
  2072. function process_ea_ref_16(const input:toper;out output:ea;rfield:longint):boolean;
  2073. var
  2074. sym : tasmsymbol;
  2075. md,s,rv : byte;
  2076. base,
  2077. o : longint;
  2078. ir,br : Tregister;
  2079. isub,bsub : tsubregister;
  2080. begin
  2081. result:=false;
  2082. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
  2083. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  2084. internalerror(200301081);
  2085. ir:=input.ref^.index;
  2086. br:=input.ref^.base;
  2087. isub:=getsubreg(ir);
  2088. bsub:=getsubreg(br);
  2089. s:=input.ref^.scalefactor;
  2090. o:=input.ref^.offset;
  2091. sym:=input.ref^.symbol;
  2092. { it's a direct address }
  2093. if (br=NR_NO) and (ir=NR_NO) then
  2094. begin
  2095. { it's a pure offset }
  2096. output.bytes:=2;
  2097. output.modrm:=6 or (rfield shl 3);
  2098. end
  2099. else
  2100. { it's an indirection }
  2101. begin
  2102. { 32 bit address? }
  2103. if ((ir<>NR_NO) and (isub<>R_SUBW)) or
  2104. ((br<>NR_NO) and (bsub<>R_SUBW)) then
  2105. message(asmw_e_32bit_not_supported);
  2106. { scalefactor can only be 1 in 16-bit addresses }
  2107. if (s<>1) and (ir<>NR_NO) then
  2108. exit;
  2109. maybe_swap_index_base(br,ir);
  2110. if (br=NR_BX) and (ir=NR_SI) then
  2111. base:=0
  2112. else if (br=NR_BX) and (ir=NR_DI) then
  2113. base:=1
  2114. else if (br=NR_BP) and (ir=NR_SI) then
  2115. base:=2
  2116. else if (br=NR_BP) and (ir=NR_DI) then
  2117. base:=3
  2118. else if (br=NR_NO) and (ir=NR_SI) then
  2119. base:=4
  2120. else if (br=NR_NO) and (ir=NR_DI) then
  2121. base:=5
  2122. else if (br=NR_BP) and (ir=NR_NO) then
  2123. base:=6
  2124. else if (br=NR_BX) and (ir=NR_NO) then
  2125. base:=7
  2126. else
  2127. exit;
  2128. if (base<>6) and (o=0) and (sym=nil) then
  2129. md:=0
  2130. else if ((o>=-128) and (o<=127) and (sym=nil)) then
  2131. md:=1
  2132. else
  2133. md:=2;
  2134. output.bytes:=md;
  2135. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or base;
  2136. end;
  2137. output.size:=1+output.bytes;
  2138. output.sib_present:=false;
  2139. result:=true;
  2140. end;
  2141. {$endif}
  2142. function process_ea(const input:toper;out output:ea;rfield:longint):boolean;
  2143. var
  2144. rv : byte;
  2145. begin
  2146. result:=false;
  2147. fillchar(output,sizeof(output),0);
  2148. {Register ?}
  2149. if (input.typ=top_reg) then
  2150. begin
  2151. rv:=regval(input.reg);
  2152. output.modrm:=$c0 or (rfield shl 3) or rv;
  2153. output.size:=1;
  2154. {$ifdef x86_64}
  2155. output.rex:=output.rex or (rexbits(input.reg) and $F1);
  2156. {$endif x86_64}
  2157. result:=true;
  2158. exit;
  2159. end;
  2160. {No register, so memory reference.}
  2161. if input.typ<>top_ref then
  2162. internalerror(200409263);
  2163. {$if defined(x86_64)}
  2164. result:=process_ea_ref_64_32(input,output,rfield);
  2165. {$elseif defined(i386) or defined(i8086)}
  2166. if is_16_bit_ref(input) then
  2167. result:=process_ea_ref_16(input,output,rfield)
  2168. else
  2169. result:=process_ea_ref_32(input,output,rfield);
  2170. {$endif}
  2171. end;
  2172. function taicpu.calcsize(p:PInsEntry):shortint;
  2173. var
  2174. codes : pchar;
  2175. c : byte;
  2176. len : shortint;
  2177. ea_data : ea;
  2178. exists_vex: boolean;
  2179. exists_vex_extension: boolean;
  2180. exists_prefix_66: boolean;
  2181. exists_prefix_F2: boolean;
  2182. exists_prefix_F3: boolean;
  2183. {$ifdef x86_64}
  2184. omit_rexw : boolean;
  2185. {$endif x86_64}
  2186. begin
  2187. len:=0;
  2188. codes:=@p^.code[0];
  2189. exists_vex := false;
  2190. exists_vex_extension := false;
  2191. exists_prefix_66 := false;
  2192. exists_prefix_F2 := false;
  2193. exists_prefix_F3 := false;
  2194. {$ifdef x86_64}
  2195. rex:=0;
  2196. omit_rexw:=false;
  2197. {$endif x86_64}
  2198. repeat
  2199. c:=ord(codes^);
  2200. inc(codes);
  2201. case c of
  2202. &0 :
  2203. break;
  2204. &1,&2,&3 :
  2205. begin
  2206. inc(codes,c);
  2207. inc(len,c);
  2208. end;
  2209. &10,&11,&12 :
  2210. begin
  2211. {$ifdef x86_64}
  2212. rex:=rex or (rexbits(oper[c-&10]^.reg) and $F1);
  2213. {$endif x86_64}
  2214. inc(codes);
  2215. inc(len);
  2216. end;
  2217. &13,&23 :
  2218. begin
  2219. inc(codes);
  2220. inc(len);
  2221. end;
  2222. &4,&5,&6,&7 :
  2223. begin
  2224. if opsize={$ifdef i8086}S_L{$else}S_W{$endif} then
  2225. inc(len,2)
  2226. else
  2227. inc(len);
  2228. end;
  2229. &14,&15,&16,
  2230. &20,&21,&22,
  2231. &24,&25,&26,&27,
  2232. &50,&51,&52 :
  2233. inc(len);
  2234. &30,&31,&32,
  2235. &37,
  2236. &60,&61,&62 :
  2237. inc(len,2);
  2238. &34,&35,&36:
  2239. begin
  2240. {$ifdef i8086}
  2241. inc(len,2);
  2242. {$else i8086}
  2243. if opsize=S_Q then
  2244. inc(len,8)
  2245. else
  2246. inc(len,4);
  2247. {$endif i8086}
  2248. end;
  2249. &44,&45,&46:
  2250. inc(len,sizeof(pint));
  2251. &54,&55,&56:
  2252. inc(len,8);
  2253. &40,&41,&42,
  2254. &70,&71,&72,
  2255. &254,&255,&256 :
  2256. inc(len,4);
  2257. &64,&65,&66:
  2258. {$ifdef i8086}
  2259. inc(len,2);
  2260. {$else i8086}
  2261. inc(len,4);
  2262. {$endif i8086}
  2263. &74,&75,&76,&77: ; // ignore vex-coded operand-idx
  2264. &320,&321,&322 :
  2265. begin
  2266. case (oper[c-&320]^.ot and OT_SIZE_MASK) of
  2267. {$if defined(i386) or defined(x86_64)}
  2268. OT_BITS16 :
  2269. {$elseif defined(i8086)}
  2270. OT_BITS32 :
  2271. {$endif}
  2272. inc(len);
  2273. {$ifdef x86_64}
  2274. OT_BITS64:
  2275. begin
  2276. rex:=rex or $48;
  2277. end;
  2278. {$endif x86_64}
  2279. end;
  2280. end;
  2281. &310 :
  2282. {$if defined(x86_64)}
  2283. { every insentry with code 0310 must be marked with NOX86_64 }
  2284. InternalError(2011051301);
  2285. {$elseif defined(i386)}
  2286. inc(len);
  2287. {$elseif defined(i8086)}
  2288. {nothing};
  2289. {$endif}
  2290. &311 :
  2291. {$if defined(x86_64) or defined(i8086)}
  2292. inc(len)
  2293. {$endif x86_64 or i8086}
  2294. ;
  2295. &324 :
  2296. {$ifndef i8086}
  2297. inc(len)
  2298. {$endif not i8086}
  2299. ;
  2300. &326 :
  2301. begin
  2302. {$ifdef x86_64}
  2303. rex:=rex or $48;
  2304. {$endif x86_64}
  2305. end;
  2306. &312,
  2307. &323,
  2308. &327,
  2309. &331,&332: ;
  2310. &325:
  2311. {$ifdef i8086}
  2312. inc(len)
  2313. {$endif i8086}
  2314. ;
  2315. &333:
  2316. begin
  2317. inc(len);
  2318. exists_prefix_F2 := true;
  2319. end;
  2320. &334:
  2321. begin
  2322. inc(len);
  2323. exists_prefix_F3 := true;
  2324. end;
  2325. &361:
  2326. begin
  2327. {$ifndef i8086}
  2328. inc(len);
  2329. exists_prefix_66 := true;
  2330. {$endif not i8086}
  2331. end;
  2332. &335:
  2333. {$ifdef x86_64}
  2334. omit_rexw:=true
  2335. {$endif x86_64}
  2336. ;
  2337. &100..&227 :
  2338. begin
  2339. {$ifdef x86_64}
  2340. if (c<&177) then
  2341. begin
  2342. if (oper[c and 7]^.typ=top_reg) then
  2343. begin
  2344. rex:=rex or (rexbits(oper[c and 7]^.reg) and $F4);
  2345. end;
  2346. end;
  2347. {$endif x86_64}
  2348. if not process_ea(oper[(c shr 3) and 7]^, ea_data, 0) then
  2349. Message(asmw_e_invalid_effective_address)
  2350. else
  2351. inc(len,ea_data.size);
  2352. {$ifdef x86_64}
  2353. rex:=rex or ea_data.rex;
  2354. {$endif x86_64}
  2355. end;
  2356. &362: // VEX prefix for AVX (length = 2 or 3 bytes, dependens on REX.XBW or opcode-prefix ($0F38 or $0F3A))
  2357. // =>> DEFAULT = 2 Bytes
  2358. begin
  2359. if not(exists_vex) then
  2360. begin
  2361. inc(len, 2);
  2362. exists_vex := true;
  2363. end;
  2364. end;
  2365. &363: // REX.W = 1
  2366. // =>> VEX prefix length = 3
  2367. begin
  2368. if not(exists_vex_extension) then
  2369. begin
  2370. inc(len);
  2371. exists_vex_extension := true;
  2372. end;
  2373. end;
  2374. &364: ; // VEX length bit
  2375. &366, // operand 2 (ymmreg) encoded immediate byte (bit 4-7)
  2376. &367: inc(len); // operand 3 (ymmreg) encoded immediate byte (bit 4-7)
  2377. &370: // VEX-Extension prefix $0F
  2378. // ignore for calculating length
  2379. ;
  2380. &371, // VEX-Extension prefix $0F38
  2381. &372: // VEX-Extension prefix $0F3A
  2382. begin
  2383. if not(exists_vex_extension) then
  2384. begin
  2385. inc(len);
  2386. exists_vex_extension := true;
  2387. end;
  2388. end;
  2389. &300,&301,&302:
  2390. begin
  2391. {$if defined(x86_64) or defined(i8086)}
  2392. if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
  2393. inc(len);
  2394. {$endif x86_64 or i8086}
  2395. end;
  2396. else
  2397. InternalError(200603141);
  2398. end;
  2399. until false;
  2400. {$ifdef x86_64}
  2401. if ((rex and $80)<>0) and ((rex and $4F)<>0) then
  2402. Message(asmw_e_bad_reg_with_rex);
  2403. rex:=rex and $4F; { reset extra bits in upper nibble }
  2404. if omit_rexw then
  2405. begin
  2406. if rex=$48 then { remove rex entirely? }
  2407. rex:=0
  2408. else
  2409. rex:=rex and $F7;
  2410. end;
  2411. if not(exists_vex) then
  2412. begin
  2413. if rex<>0 then
  2414. Inc(len);
  2415. end;
  2416. {$endif}
  2417. if exists_vex then
  2418. begin
  2419. if exists_prefix_66 then dec(len);
  2420. if exists_prefix_F2 then dec(len);
  2421. if exists_prefix_F3 then dec(len);
  2422. {$ifdef x86_64}
  2423. if not(exists_vex_extension) then
  2424. if rex and $0B <> 0 then inc(len); // REX.WXB <> 0 =>> needed VEX-Extension
  2425. {$endif x86_64}
  2426. end;
  2427. calcsize:=len;
  2428. end;
  2429. procedure taicpu.write0x66prefix(objdata:TObjData);
  2430. const
  2431. b66: Byte=$66;
  2432. begin
  2433. {$ifdef i8086}
  2434. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) then
  2435. Message(asmw_e_instruction_not_supported_by_cpu);
  2436. {$endif i8086}
  2437. objdata.writebytes(b66,1);
  2438. end;
  2439. procedure taicpu.write0x67prefix(objdata:TObjData);
  2440. const
  2441. b67: Byte=$67;
  2442. begin
  2443. {$ifdef i8086}
  2444. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) then
  2445. Message(asmw_e_instruction_not_supported_by_cpu);
  2446. {$endif i8086}
  2447. objdata.writebytes(b67,1);
  2448. end;
  2449. procedure taicpu.GenCode(objdata:TObjData);
  2450. {
  2451. * the actual codes (C syntax, i.e. octal):
  2452. * \0 - terminates the code. (Unless it's a literal of course.)
  2453. * \1, \2, \3 - that many literal bytes follow in the code stream
  2454. * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  2455. * (POP is never used for CS) depending on operand 0
  2456. * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
  2457. * on operand 0
  2458. * \10, \11, \12 - a literal byte follows in the code stream, to be added
  2459. * to the register value of operand 0, 1 or 2
  2460. * \13 - a literal byte follows in the code stream, to be added
  2461. * to the condition code value of the instruction.
  2462. * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
  2463. * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
  2464. * \23 - a literal byte follows in the code stream, to be added
  2465. * to the inverted condition code value of the instruction
  2466. * (inverted version of \13).
  2467. * \24, \25, \26, \27 - an unsigned byte immediate operand, from operand 0, 1, 2 or 3
  2468. * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
  2469. * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
  2470. * assembly mode or the address-size override on the operand
  2471. * \37 - a word constant, from the _segment_ part of operand 0
  2472. * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
  2473. * \44, \45, \46 - select between \3[012], \4[012] or \5[456] depending
  2474. on the address size of instruction
  2475. * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
  2476. * \54, \55, \56 - a qword immediate, from operand 0, 1 or 2
  2477. * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
  2478. * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
  2479. * assembly mode or the address-size override on the operand
  2480. * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
  2481. * \74, \75, \76 - a vex-coded vector operand, from operand 0, 1 or 2
  2482. * \1ab - a ModRM, calculated on EA in operand a, with the spare
  2483. * field the register value of operand b.
  2484. * \2ab - a ModRM, calculated on EA in operand a, with the spare
  2485. * field equal to digit b.
  2486. * \254,\255,\256 - a signed 32-bit immediate to be extended to 64 bits
  2487. * \300,\301,\302 - might be an 0x67, depending on the address size of
  2488. * the memory reference in operand x.
  2489. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
  2490. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
  2491. * \312 - (disassembler only) invalid with non-default address size.
  2492. * \320,\321,\322 - might be an 0x66 or 0x48 byte, depending on the operand
  2493. * size of operand x.
  2494. * \324 - indicates fixed 16-bit operand size, i.e. optional 0x66.
  2495. * \325 - indicates fixed 32-bit operand size, i.e. optional 0x66.
  2496. * \326 - indicates fixed 64-bit operand size, i.e. optional 0x48.
  2497. * \327 - indicates that this instruction is only valid when the
  2498. * operand size is the default (instruction to disassembler,
  2499. * generates no code in the assembler)
  2500. * \331 - instruction not valid with REP prefix. Hint for
  2501. * disassembler only; for SSE instructions.
  2502. * \332 - disassemble a rep (0xF3 byte) prefix as repe not rep.
  2503. * \333 - 0xF3 prefix for SSE instructions
  2504. * \334 - 0xF2 prefix for SSE instructions
  2505. * \335 - Indicates 64-bit operand size with REX.W not necessary
  2506. * \361 - 0x66 prefix for SSE instructions
  2507. * \362 - VEX prefix for AVX instructions
  2508. * \363 - VEX W1
  2509. * \364 - VEX Vector length 256
  2510. * \366 - operand 2 (ymmreg) encoded in bit 4-7 of the immediate byte
  2511. * \367 - operand 3 (ymmreg) encoded in bit 4-7 of the immediate byte
  2512. * \370 - VEX 0F-FLAG
  2513. * \371 - VEX 0F38-FLAG
  2514. * \372 - VEX 0F3A-FLAG
  2515. }
  2516. var
  2517. currval : aint;
  2518. currsym : tobjsymbol;
  2519. currrelreloc,
  2520. currabsreloc,
  2521. currabsreloc32 : TObjRelocationType;
  2522. {$ifdef x86_64}
  2523. rexwritten : boolean;
  2524. {$endif x86_64}
  2525. procedure getvalsym(opidx:longint);
  2526. begin
  2527. case oper[opidx]^.typ of
  2528. top_ref :
  2529. begin
  2530. currval:=oper[opidx]^.ref^.offset;
  2531. currsym:=ObjData.symbolref(oper[opidx]^.ref^.symbol);
  2532. {$ifdef i8086}
  2533. if oper[opidx]^.ref^.refaddr=addr_seg then
  2534. begin
  2535. currrelreloc:=RELOC_SEGREL;
  2536. currabsreloc:=RELOC_SEG;
  2537. currabsreloc32:=RELOC_SEG;
  2538. end
  2539. else if oper[opidx]^.ref^.refaddr=addr_dgroup then
  2540. begin
  2541. currrelreloc:=RELOC_DGROUPREL;
  2542. currabsreloc:=RELOC_DGROUP;
  2543. currabsreloc32:=RELOC_DGROUP;
  2544. end
  2545. else if oper[opidx]^.ref^.refaddr=addr_fardataseg then
  2546. begin
  2547. currrelreloc:=RELOC_FARDATASEGREL;
  2548. currabsreloc:=RELOC_FARDATASEG;
  2549. currabsreloc32:=RELOC_FARDATASEG;
  2550. end
  2551. else
  2552. {$endif i8086}
  2553. {$ifdef i386}
  2554. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  2555. (tf_pic_uses_got in target_info.flags) then
  2556. begin
  2557. currrelreloc:=RELOC_PLT32;
  2558. currabsreloc:=RELOC_GOT32;
  2559. currabsreloc32:=RELOC_GOT32;
  2560. end
  2561. else
  2562. {$endif i386}
  2563. {$ifdef x86_64}
  2564. if oper[opidx]^.ref^.refaddr=addr_pic then
  2565. begin
  2566. currrelreloc:=RELOC_PLT32;
  2567. currabsreloc:=RELOC_GOTPCREL;
  2568. currabsreloc32:=RELOC_GOTPCREL;
  2569. end
  2570. else if oper[opidx]^.ref^.refaddr=addr_pic_no_got then
  2571. begin
  2572. currrelreloc:=RELOC_RELATIVE;
  2573. currabsreloc:=RELOC_RELATIVE;
  2574. currabsreloc32:=RELOC_RELATIVE;
  2575. end
  2576. else
  2577. {$endif x86_64}
  2578. begin
  2579. currrelreloc:=RELOC_RELATIVE;
  2580. currabsreloc:=RELOC_ABSOLUTE;
  2581. currabsreloc32:=RELOC_ABSOLUTE32;
  2582. end;
  2583. end;
  2584. top_const :
  2585. begin
  2586. currval:=aint(oper[opidx]^.val);
  2587. currsym:=nil;
  2588. currabsreloc:=RELOC_ABSOLUTE;
  2589. currabsreloc32:=RELOC_ABSOLUTE32;
  2590. end;
  2591. else
  2592. Message(asmw_e_immediate_or_reference_expected);
  2593. end;
  2594. end;
  2595. {$ifdef x86_64}
  2596. procedure maybewriterex;
  2597. begin
  2598. if (rex<>0) and not(rexwritten) then
  2599. begin
  2600. rexwritten:=true;
  2601. objdata.writebytes(rex,1);
  2602. end;
  2603. end;
  2604. {$endif x86_64}
  2605. procedure objdata_writereloc(Data:TRelocDataInt;len:aword;p:TObjSymbol;Reloctype:TObjRelocationType);
  2606. begin
  2607. {$ifdef i386}
  2608. { Special case of '_GLOBAL_OFFSET_TABLE_'
  2609. which needs a special relocation type R_386_GOTPC }
  2610. if assigned (p) and
  2611. (p.name='_GLOBAL_OFFSET_TABLE_') and
  2612. (tf_pic_uses_got in target_info.flags) then
  2613. begin
  2614. { nothing else than a 4 byte relocation should occur
  2615. for GOT }
  2616. if len<>4 then
  2617. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  2618. Reloctype:=RELOC_GOTPC;
  2619. { We need to add the offset of the relocation
  2620. of _GLOBAL_OFFSET_TABLE symbol within
  2621. the current instruction }
  2622. inc(data,objdata.currobjsec.size-insoffset);
  2623. end;
  2624. {$endif i386}
  2625. objdata.writereloc(data,len,p,Reloctype);
  2626. end;
  2627. const
  2628. CondVal:array[TAsmCond] of byte=($0,
  2629. $7, $3, $2, $6, $2, $4, $F, $D, $C, $E, $6, $2,
  2630. $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
  2631. $0, $A, $A, $B, $8, $4);
  2632. var
  2633. c : byte;
  2634. pb : pbyte;
  2635. codes : pchar;
  2636. bytes : array[0..3] of byte;
  2637. rfield,
  2638. data,s,opidx : longint;
  2639. ea_data : ea;
  2640. relsym : TObjSymbol;
  2641. needed_VEX_Extension: boolean;
  2642. needed_VEX: boolean;
  2643. opmode: integer;
  2644. VEXvvvv: byte;
  2645. VEXmmmmm: byte;
  2646. begin
  2647. { safety check }
  2648. if objdata.currobjsec.size<>longword(insoffset) then
  2649. internalerror(200130121);
  2650. { those variables are initialized inside local procedures, the dfa cannot handle this yet }
  2651. currsym:=nil;
  2652. currabsreloc:=RELOC_NONE;
  2653. currabsreloc32:=RELOC_NONE;
  2654. currrelreloc:=RELOC_NONE;
  2655. currval:=0;
  2656. { check instruction's processor level }
  2657. { todo: maybe adapt and enable this code for i386 and x86_64 as well }
  2658. {$ifdef i8086}
  2659. if objdata.CPUType<>cpu_none then
  2660. begin
  2661. if IF_8086 in insentry^.flags then
  2662. else if IF_186 in insentry^.flags then
  2663. begin
  2664. if objdata.CPUType<cpu_186 then
  2665. Message(asmw_e_instruction_not_supported_by_cpu);
  2666. end
  2667. else if IF_286 in insentry^.flags then
  2668. begin
  2669. if objdata.CPUType<cpu_286 then
  2670. Message(asmw_e_instruction_not_supported_by_cpu);
  2671. end
  2672. else if IF_386 in insentry^.flags then
  2673. begin
  2674. if objdata.CPUType<cpu_386 then
  2675. Message(asmw_e_instruction_not_supported_by_cpu);
  2676. end
  2677. else if IF_486 in insentry^.flags then
  2678. begin
  2679. if objdata.CPUType<cpu_486 then
  2680. Message(asmw_e_instruction_not_supported_by_cpu);
  2681. end
  2682. else if IF_PENT in insentry^.flags then
  2683. begin
  2684. if objdata.CPUType<cpu_Pentium then
  2685. Message(asmw_e_instruction_not_supported_by_cpu);
  2686. end
  2687. else if IF_P6 in insentry^.flags then
  2688. begin
  2689. if objdata.CPUType<cpu_Pentium2 then
  2690. Message(asmw_e_instruction_not_supported_by_cpu);
  2691. end
  2692. else if IF_KATMAI in insentry^.flags then
  2693. begin
  2694. if objdata.CPUType<cpu_Pentium3 then
  2695. Message(asmw_e_instruction_not_supported_by_cpu);
  2696. end
  2697. else if insentry^.flags*[IF_WILLAMETTE,IF_PRESCOTT]<>[] then
  2698. begin
  2699. if objdata.CPUType<cpu_Pentium4 then
  2700. Message(asmw_e_instruction_not_supported_by_cpu);
  2701. end
  2702. else if IF_NEC in insentry^.flags then
  2703. begin
  2704. { the NEC V20/V30 extensions are incompatible with 386+, due to overlapping opcodes }
  2705. if objdata.CPUType>=cpu_386 then
  2706. Message(asmw_e_instruction_not_supported_by_cpu);
  2707. end
  2708. else if IF_SANDYBRIDGE in insentry^.flags then
  2709. begin
  2710. { todo: handle these properly }
  2711. end;
  2712. end;
  2713. {$endif i8086}
  2714. { load data to write }
  2715. codes:=insentry^.code;
  2716. {$ifdef x86_64}
  2717. rexwritten:=false;
  2718. {$endif x86_64}
  2719. { Force word push/pop for registers }
  2720. if (opsize={$ifdef i8086}S_L{$else}S_W{$endif}) and ((codes[0]=#4) or (codes[0]=#6) or
  2721. ((codes[0]=#1) and ((codes[2]=#5) or (codes[2]=#7)))) then
  2722. write0x66prefix(objdata);
  2723. // needed VEX Prefix (for AVX etc.)
  2724. needed_VEX := false;
  2725. needed_VEX_Extension := false;
  2726. opmode := -1;
  2727. VEXvvvv := 0;
  2728. VEXmmmmm := 0;
  2729. repeat
  2730. c:=ord(codes^);
  2731. inc(codes);
  2732. case c of
  2733. &0: break;
  2734. &1,
  2735. &2,
  2736. &3: inc(codes,c);
  2737. &74: opmode := 0;
  2738. &75: opmode := 1;
  2739. &76: opmode := 2;
  2740. &333: VEXvvvv := VEXvvvv OR $02; // set SIMD-prefix $F3
  2741. &334: VEXvvvv := VEXvvvv OR $03; // set SIMD-prefix $F2
  2742. &361: VEXvvvv := VEXvvvv OR $01; // set SIMD-prefix $66
  2743. &362: needed_VEX := true;
  2744. &363: begin
  2745. needed_VEX_Extension := true;
  2746. VEXvvvv := VEXvvvv OR (1 shl 7); // set REX.W
  2747. end;
  2748. &364: VEXvvvv := VEXvvvv OR $04; // vectorlength = 256 bits AND no scalar
  2749. &370: VEXmmmmm := VEXmmmmm OR $01; // set leading opcode byte $0F
  2750. &371: begin
  2751. needed_VEX_Extension := true;
  2752. VEXmmmmm := VEXmmmmm OR $02; // set leading opcode byte $0F38
  2753. end;
  2754. &372: begin
  2755. needed_VEX_Extension := true;
  2756. VEXmmmmm := VEXmmmmm OR $03; // set leading opcode byte $0F3A
  2757. end;
  2758. end;
  2759. until false;
  2760. if needed_VEX then
  2761. begin
  2762. if (opmode > ops) or
  2763. (opmode < -1) then
  2764. begin
  2765. Internalerror(777100);
  2766. end
  2767. else if opmode = -1 then
  2768. begin
  2769. VEXvvvv := VEXvvvv or ($0F shl 3); // set VEXvvvv bits (bits 6-3) to 1
  2770. end
  2771. else if oper[opmode]^.typ = top_reg then
  2772. begin
  2773. VEXvvvv := VEXvvvv or ((not(regval(oper[opmode]^.reg)) and $07) shl 3);
  2774. {$ifdef x86_64}
  2775. if rexbits(oper[opmode]^.reg) = 0 then VEXvvvv := VEXvvvv or (1 shl 6);
  2776. {$else}
  2777. VEXvvvv := VEXvvvv or (1 shl 6);
  2778. {$endif x86_64}
  2779. end
  2780. else Internalerror(777101);
  2781. if not(needed_VEX_Extension) then
  2782. begin
  2783. {$ifdef x86_64}
  2784. if rex and $0B <> 0 then needed_VEX_Extension := true;
  2785. {$endif x86_64}
  2786. end;
  2787. if needed_VEX_Extension then
  2788. begin
  2789. // VEX-Prefix-Length = 3 Bytes
  2790. {$ifdef x86_64}
  2791. VEXmmmmm := VEXmmmmm or ((not(rex) and $07) shl 5); // set REX.rxb
  2792. VEXvvvv := VEXvvvv or ((rex and $08) shl 7); // set REX.w
  2793. {$else}
  2794. VEXmmmmm := VEXmmmmm or (7 shl 5); //
  2795. {$endif x86_64}
  2796. bytes[0]:=$C4;
  2797. bytes[1]:=VEXmmmmm;
  2798. bytes[2]:=VEXvvvv;
  2799. objdata.writebytes(bytes,3);
  2800. end
  2801. else
  2802. begin
  2803. // VEX-Prefix-Length = 2 Bytes
  2804. {$ifdef x86_64}
  2805. if rex and $04 = 0 then
  2806. {$endif x86_64}
  2807. begin
  2808. VEXvvvv := VEXvvvv or (1 shl 7);
  2809. end;
  2810. bytes[0]:=$C5;
  2811. bytes[1]:=VEXvvvv;
  2812. objdata.writebytes(bytes,2);
  2813. end;
  2814. end
  2815. else
  2816. begin
  2817. needed_VEX_Extension := false;
  2818. opmode := -1;
  2819. end;
  2820. { load data to write }
  2821. codes:=insentry^.code;
  2822. repeat
  2823. c:=ord(codes^);
  2824. inc(codes);
  2825. case c of
  2826. &0 :
  2827. break;
  2828. &1,&2,&3 :
  2829. begin
  2830. {$ifdef x86_64}
  2831. if not(needed_VEX) then // TG
  2832. maybewriterex;
  2833. {$endif x86_64}
  2834. objdata.writebytes(codes^,c);
  2835. inc(codes,c);
  2836. end;
  2837. &4,&6 :
  2838. begin
  2839. case oper[0]^.reg of
  2840. NR_CS:
  2841. bytes[0]:=$e;
  2842. NR_NO,
  2843. NR_DS:
  2844. bytes[0]:=$1e;
  2845. NR_ES:
  2846. bytes[0]:=$6;
  2847. NR_SS:
  2848. bytes[0]:=$16;
  2849. else
  2850. internalerror(777004);
  2851. end;
  2852. if c=&4 then
  2853. inc(bytes[0]);
  2854. objdata.writebytes(bytes,1);
  2855. end;
  2856. &5,&7 :
  2857. begin
  2858. case oper[0]^.reg of
  2859. NR_FS:
  2860. bytes[0]:=$a0;
  2861. NR_GS:
  2862. bytes[0]:=$a8;
  2863. else
  2864. internalerror(777005);
  2865. end;
  2866. if c=&5 then
  2867. inc(bytes[0]);
  2868. objdata.writebytes(bytes,1);
  2869. end;
  2870. &10,&11,&12 :
  2871. begin
  2872. {$ifdef x86_64}
  2873. if not(needed_VEX) then // TG
  2874. maybewriterex;
  2875. {$endif x86_64}
  2876. bytes[0]:=ord(codes^)+regval(oper[c-&10]^.reg);
  2877. inc(codes);
  2878. objdata.writebytes(bytes,1);
  2879. end;
  2880. &13 :
  2881. begin
  2882. bytes[0]:=ord(codes^)+condval[condition];
  2883. inc(codes);
  2884. objdata.writebytes(bytes,1);
  2885. end;
  2886. &14,&15,&16 :
  2887. begin
  2888. getvalsym(c-&14);
  2889. if (currval<-128) or (currval>127) then
  2890. Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
  2891. if assigned(currsym) then
  2892. objdata_writereloc(currval,1,currsym,currabsreloc)
  2893. else
  2894. objdata.writebytes(currval,1);
  2895. end;
  2896. &20,&21,&22 :
  2897. begin
  2898. getvalsym(c-&20);
  2899. if (currval<-256) or (currval>255) then
  2900. Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
  2901. if assigned(currsym) then
  2902. objdata_writereloc(currval,1,currsym,currabsreloc)
  2903. else
  2904. objdata.writebytes(currval,1);
  2905. end;
  2906. &23 :
  2907. begin
  2908. bytes[0]:=ord(codes^)+condval[inverse_cond(condition)];
  2909. inc(codes);
  2910. objdata.writebytes(bytes,1);
  2911. end;
  2912. &24,&25,&26,&27 :
  2913. begin
  2914. getvalsym(c-&24);
  2915. if IF_IMM3 in insentry^.flags then
  2916. begin
  2917. if (currval<0) or (currval>7) then
  2918. Message2(asmw_e_value_exceeds_bounds,'unsigned triad',tostr(currval));
  2919. end
  2920. else if IF_IMM4 in insentry^.flags then
  2921. begin
  2922. if (currval<0) or (currval>15) then
  2923. Message2(asmw_e_value_exceeds_bounds,'unsigned nibble',tostr(currval));
  2924. end
  2925. else
  2926. if (currval<0) or (currval>255) then
  2927. Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
  2928. if assigned(currsym) then
  2929. objdata_writereloc(currval,1,currsym,currabsreloc)
  2930. else
  2931. objdata.writebytes(currval,1);
  2932. end;
  2933. &30,&31,&32 : // 030..032
  2934. begin
  2935. getvalsym(c-&30);
  2936. {$ifndef i8086}
  2937. { currval is an aint so this cannot happen on i8086 and causes only a warning }
  2938. if (currval<-65536) or (currval>65535) then
  2939. Message2(asmw_e_value_exceeds_bounds,'word',tostr(currval));
  2940. {$endif i8086}
  2941. if assigned(currsym)
  2942. {$ifdef i8086}
  2943. or (currabsreloc in [RELOC_DGROUP,RELOC_FARDATASEG])
  2944. {$endif i8086}
  2945. then
  2946. objdata_writereloc(currval,2,currsym,currabsreloc)
  2947. else
  2948. objdata.writebytes(currval,2);
  2949. end;
  2950. &34,&35,&36 : // 034..036
  2951. { !!! These are intended (and used in opcode table) to select depending
  2952. on address size, *not* operand size. Works by coincidence only. }
  2953. begin
  2954. getvalsym(c-&34);
  2955. {$ifdef i8086}
  2956. if assigned(currsym) then
  2957. objdata_writereloc(currval,2,currsym,currabsreloc)
  2958. else
  2959. objdata.writebytes(currval,2);
  2960. {$else i8086}
  2961. if opsize=S_Q then
  2962. begin
  2963. if assigned(currsym) then
  2964. objdata_writereloc(currval,8,currsym,currabsreloc)
  2965. else
  2966. objdata.writebytes(currval,8);
  2967. end
  2968. else
  2969. begin
  2970. if assigned(currsym) then
  2971. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2972. else
  2973. objdata.writebytes(currval,4);
  2974. end
  2975. {$endif i8086}
  2976. end;
  2977. &40,&41,&42 : // 040..042
  2978. begin
  2979. getvalsym(c-&40);
  2980. if assigned(currsym) then
  2981. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2982. else
  2983. objdata.writebytes(currval,4);
  2984. end;
  2985. &44,&45,&46 :// 044..046 - select between word/dword/qword depending on
  2986. begin // address size (we support only default address sizes).
  2987. getvalsym(c-&44);
  2988. {$if defined(x86_64)}
  2989. if assigned(currsym) then
  2990. objdata_writereloc(currval,8,currsym,currabsreloc)
  2991. else
  2992. objdata.writebytes(currval,8);
  2993. {$elseif defined(i386)}
  2994. if assigned(currsym) then
  2995. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2996. else
  2997. objdata.writebytes(currval,4);
  2998. {$elseif defined(i8086)}
  2999. if assigned(currsym) then
  3000. objdata_writereloc(currval,2,currsym,currabsreloc)
  3001. else
  3002. objdata.writebytes(currval,2);
  3003. {$endif}
  3004. end;
  3005. &50,&51,&52 : // 050..052 - byte relative operand
  3006. begin
  3007. getvalsym(c-&50);
  3008. data:=currval-insend;
  3009. {$push}
  3010. {$r-,q-} { disable also overflow as address returns a qword for x86_64 }
  3011. if assigned(currsym) then
  3012. inc(data,currsym.address);
  3013. {$pop}
  3014. if (data>127) or (data<-128) then
  3015. Message1(asmw_e_short_jmp_out_of_range,tostr(data));
  3016. objdata.writebytes(data,1);
  3017. end;
  3018. &54,&55,&56: // 054..056 - qword immediate operand
  3019. begin
  3020. getvalsym(c-&54);
  3021. if assigned(currsym) then
  3022. objdata_writereloc(currval,8,currsym,currabsreloc)
  3023. else
  3024. objdata.writebytes(currval,8);
  3025. end;
  3026. &60,&61,&62 :
  3027. begin
  3028. getvalsym(c-&60);
  3029. {$ifdef i8086}
  3030. if assigned(currsym) then
  3031. objdata_writereloc(currval,2,currsym,currrelreloc)
  3032. else
  3033. objdata_writereloc(currval-insend,2,nil,currabsreloc)
  3034. {$else i8086}
  3035. InternalError(777006);
  3036. {$endif i8086}
  3037. end;
  3038. &64,&65,&66 : // 064..066 - select between 16/32 address mode, but we support only 32 (only 16 on i8086)
  3039. begin
  3040. getvalsym(c-&64);
  3041. {$ifdef i8086}
  3042. if assigned(currsym) then
  3043. objdata_writereloc(currval,2,currsym,currrelreloc)
  3044. else
  3045. objdata_writereloc(currval-insend,2,nil,currabsreloc)
  3046. {$else i8086}
  3047. if assigned(currsym) then
  3048. objdata_writereloc(currval,4,currsym,currrelreloc)
  3049. else
  3050. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  3051. {$endif i8086}
  3052. end;
  3053. &70,&71,&72 : // 070..072 - long relative operand
  3054. begin
  3055. getvalsym(c-&70);
  3056. if assigned(currsym) then
  3057. objdata_writereloc(currval,4,currsym,currrelreloc)
  3058. else
  3059. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  3060. end;
  3061. &74,&75,&76 : ; // 074..076 - vex-coded vector operand
  3062. // ignore
  3063. &254,&255,&256 : // 0254..0256 - dword implicitly sign-extended to 64-bit (x86_64 only)
  3064. begin
  3065. getvalsym(c-&254);
  3066. {$ifdef x86_64}
  3067. { for i386 as aint type is longint the
  3068. following test is useless }
  3069. if (currval<low(longint)) or (currval>high(longint)) then
  3070. Message2(asmw_e_value_exceeds_bounds,'signed dword',tostr(currval));
  3071. {$endif x86_64}
  3072. if assigned(currsym) then
  3073. objdata_writereloc(currval,4,currsym,currabsreloc32)
  3074. else
  3075. objdata.writebytes(currval,4);
  3076. end;
  3077. &300,&301,&302:
  3078. begin
  3079. {$if defined(x86_64) or defined(i8086)}
  3080. if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
  3081. write0x67prefix(objdata);
  3082. {$endif x86_64 or i8086}
  3083. end;
  3084. &310 : { fixed 16-bit addr }
  3085. {$if defined(x86_64)}
  3086. { every insentry having code 0310 must be marked with NOX86_64 }
  3087. InternalError(2011051302);
  3088. {$elseif defined(i386)}
  3089. write0x67prefix(objdata);
  3090. {$elseif defined(i8086)}
  3091. {nothing};
  3092. {$endif}
  3093. &311 : { fixed 32-bit addr }
  3094. {$if defined(x86_64) or defined(i8086)}
  3095. write0x67prefix(objdata)
  3096. {$endif x86_64 or i8086}
  3097. ;
  3098. &320,&321,&322 :
  3099. begin
  3100. case oper[c-&320]^.ot and OT_SIZE_MASK of
  3101. {$if defined(i386) or defined(x86_64)}
  3102. OT_BITS16 :
  3103. {$elseif defined(i8086)}
  3104. OT_BITS32 :
  3105. {$endif}
  3106. write0x66prefix(objdata);
  3107. {$ifndef x86_64}
  3108. OT_BITS64 :
  3109. Message(asmw_e_64bit_not_supported);
  3110. {$endif x86_64}
  3111. end;
  3112. end;
  3113. &323 : {no action needed};
  3114. &325:
  3115. {$ifdef i8086}
  3116. write0x66prefix(objdata);
  3117. {$else i8086}
  3118. {no action needed};
  3119. {$endif i8086}
  3120. &324,
  3121. &361:
  3122. begin
  3123. {$ifndef i8086}
  3124. if not(needed_VEX) then
  3125. write0x66prefix(objdata);
  3126. {$endif not i8086}
  3127. end;
  3128. &326 :
  3129. begin
  3130. {$ifndef x86_64}
  3131. Message(asmw_e_64bit_not_supported);
  3132. {$endif x86_64}
  3133. end;
  3134. &333 :
  3135. begin
  3136. if not(needed_VEX) then
  3137. begin
  3138. bytes[0]:=$f3;
  3139. objdata.writebytes(bytes,1);
  3140. end;
  3141. end;
  3142. &334 :
  3143. begin
  3144. if not(needed_VEX) then
  3145. begin
  3146. bytes[0]:=$f2;
  3147. objdata.writebytes(bytes,1);
  3148. end;
  3149. end;
  3150. &335:
  3151. ;
  3152. &312,
  3153. &327,
  3154. &331,&332 :
  3155. begin
  3156. { these are dissambler hints or 32 bit prefixes which
  3157. are not needed }
  3158. end;
  3159. &362..&364: ; // VEX flags =>> nothing todo
  3160. &366, &367:
  3161. begin
  3162. opidx:=c-&364; { 0366->operand 2, 0367->operand 3 }
  3163. if needed_VEX and
  3164. (ops=4) and
  3165. (oper[opidx]^.typ=top_reg) and
  3166. (oper[opidx]^.ot and (otf_reg_xmm or otf_reg_ymm)<>0) then
  3167. begin
  3168. bytes[0] := ((getsupreg(oper[opidx]^.reg) and 15) shl 4);
  3169. objdata.writebytes(bytes,1);
  3170. end
  3171. else
  3172. Internalerror(2014032001);
  3173. end;
  3174. &370..&372: ; // VEX flags =>> nothing todo
  3175. &37:
  3176. begin
  3177. {$ifdef i8086}
  3178. if assigned(currsym) then
  3179. objdata_writereloc(0,2,currsym,RELOC_SEG)
  3180. else
  3181. InternalError(2015041503);
  3182. {$else i8086}
  3183. InternalError(777006);
  3184. {$endif i8086}
  3185. end;
  3186. else
  3187. begin
  3188. { rex should be written at this point }
  3189. {$ifdef x86_64}
  3190. if not(needed_VEX) then // TG
  3191. if (rex<>0) and not(rexwritten) then
  3192. internalerror(200603191);
  3193. {$endif x86_64}
  3194. if (c>=&100) and (c<=&227) then // 0100..0227
  3195. begin
  3196. if (c<&177) then // 0177
  3197. begin
  3198. if (oper[c and 7]^.typ=top_reg) then
  3199. rfield:=regval(oper[c and 7]^.reg)
  3200. else
  3201. rfield:=regval(oper[c and 7]^.ref^.base);
  3202. end
  3203. else
  3204. rfield:=c and 7;
  3205. opidx:=(c shr 3) and 7;
  3206. if not process_ea(oper[opidx]^,ea_data,rfield) then
  3207. Message(asmw_e_invalid_effective_address);
  3208. pb:=@bytes[0];
  3209. pb^:=ea_data.modrm;
  3210. inc(pb);
  3211. if ea_data.sib_present then
  3212. begin
  3213. pb^:=ea_data.sib;
  3214. inc(pb);
  3215. end;
  3216. s:=pb-@bytes[0];
  3217. objdata.writebytes(bytes,s);
  3218. case ea_data.bytes of
  3219. 0 : ;
  3220. 1 :
  3221. begin
  3222. if (oper[opidx]^.ot and OT_MEMORY)=OT_MEMORY then
  3223. begin
  3224. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  3225. {$ifdef i386}
  3226. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  3227. (tf_pic_uses_got in target_info.flags) then
  3228. currabsreloc:=RELOC_GOT32
  3229. else
  3230. {$endif i386}
  3231. {$ifdef x86_64}
  3232. if oper[opidx]^.ref^.refaddr=addr_pic then
  3233. currabsreloc:=RELOC_GOTPCREL
  3234. else
  3235. {$endif x86_64}
  3236. currabsreloc:=RELOC_ABSOLUTE;
  3237. objdata_writereloc(oper[opidx]^.ref^.offset,1,currsym,currabsreloc);
  3238. end
  3239. else
  3240. begin
  3241. bytes[0]:=oper[opidx]^.ref^.offset;
  3242. objdata.writebytes(bytes,1);
  3243. end;
  3244. inc(s);
  3245. end;
  3246. 2,4 :
  3247. begin
  3248. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  3249. currval:=oper[opidx]^.ref^.offset;
  3250. {$ifdef x86_64}
  3251. if oper[opidx]^.ref^.refaddr=addr_pic then
  3252. currabsreloc:=RELOC_GOTPCREL
  3253. else
  3254. if oper[opidx]^.ref^.base=NR_RIP then
  3255. begin
  3256. currabsreloc:=RELOC_RELATIVE;
  3257. { Adjust reloc value by number of bytes following the displacement,
  3258. but not if displacement is specified by literal constant }
  3259. if Assigned(currsym) then
  3260. Dec(currval,InsEnd-objdata.CurrObjSec.Size-ea_data.bytes);
  3261. end
  3262. else
  3263. {$endif x86_64}
  3264. {$ifdef i386}
  3265. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  3266. (tf_pic_uses_got in target_info.flags) then
  3267. currabsreloc:=RELOC_GOT32
  3268. else
  3269. {$endif i386}
  3270. {$ifdef i8086}
  3271. if ea_data.bytes=2 then
  3272. currabsreloc:=RELOC_ABSOLUTE
  3273. else
  3274. {$endif i8086}
  3275. currabsreloc:=RELOC_ABSOLUTE32;
  3276. if (currabsreloc in [RELOC_ABSOLUTE32{$ifdef i8086},RELOC_ABSOLUTE{$endif}]) and
  3277. (Assigned(oper[opidx]^.ref^.relsymbol)) then
  3278. begin
  3279. relsym:=objdata.symbolref(oper[opidx]^.ref^.relsymbol);
  3280. if relsym.objsection=objdata.CurrObjSec then
  3281. begin
  3282. currval:=objdata.CurrObjSec.size+ea_data.bytes-relsym.offset+currval;
  3283. {$ifdef i8086}
  3284. if ea_data.bytes=4 then
  3285. currabsreloc:=RELOC_RELATIVE32
  3286. else
  3287. {$endif i8086}
  3288. currabsreloc:=RELOC_RELATIVE;
  3289. end
  3290. else
  3291. begin
  3292. currabsreloc:=RELOC_PIC_PAIR;
  3293. currval:=relsym.offset;
  3294. end;
  3295. end;
  3296. objdata_writereloc(currval,ea_data.bytes,currsym,currabsreloc);
  3297. inc(s,ea_data.bytes);
  3298. end;
  3299. end;
  3300. end
  3301. else
  3302. InternalError(777007);
  3303. end;
  3304. end;
  3305. until false;
  3306. end;
  3307. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  3308. begin
  3309. result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and
  3310. (regtype = R_INTREGISTER) and
  3311. (ops=2) and
  3312. (oper[0]^.typ=top_reg) and
  3313. (oper[1]^.typ=top_reg) and
  3314. (oper[0]^.reg=oper[1]^.reg)
  3315. ) or
  3316. (((opcode=A_MOVSS) or (opcode=A_MOVSD) or (opcode=A_MOVQ) or
  3317. (opcode=A_MOVAPS) or (opcode=A_MOVAPD) or
  3318. (opcode=A_VMOVSS) or (opcode=A_VMOVSD) or (opcode=A_VMOVQ) or
  3319. (opcode=A_VMOVAPS) or (opcode=A_VMOVAPD)) and
  3320. (regtype = R_MMREGISTER) and
  3321. (ops=2) and
  3322. (oper[0]^.typ=top_reg) and
  3323. (oper[1]^.typ=top_reg) and
  3324. (oper[0]^.reg=oper[1]^.reg)
  3325. );
  3326. end;
  3327. procedure build_spilling_operation_type_table;
  3328. var
  3329. opcode : tasmop;
  3330. i : integer;
  3331. begin
  3332. new(operation_type_table);
  3333. fillchar(operation_type_table^,sizeof(toperation_type_table),byte(operand_read));
  3334. for opcode:=low(tasmop) to high(tasmop) do
  3335. with InsProp[opcode] do
  3336. begin
  3337. if Ch_Rop1 in Ch then
  3338. operation_type_table^[opcode,0]:=operand_read;
  3339. if Ch_Wop1 in Ch then
  3340. operation_type_table^[opcode,0]:=operand_write;
  3341. if [Ch_RWop1,Ch_Mop1]*Ch<>[] then
  3342. operation_type_table^[opcode,0]:=operand_readwrite;
  3343. if Ch_Rop2 in Ch then
  3344. operation_type_table^[opcode,1]:=operand_read;
  3345. if Ch_Wop2 in Ch then
  3346. operation_type_table^[opcode,1]:=operand_write;
  3347. if [Ch_RWop2,Ch_Mop2]*Ch<>[] then
  3348. operation_type_table^[opcode,1]:=operand_readwrite;
  3349. if Ch_Rop3 in Ch then
  3350. operation_type_table^[opcode,2]:=operand_read;
  3351. if Ch_Wop3 in Ch then
  3352. operation_type_table^[opcode,2]:=operand_write;
  3353. if [Ch_RWop3,Ch_Mop3]*Ch<>[] then
  3354. operation_type_table^[opcode,2]:=operand_readwrite;
  3355. if Ch_Rop4 in Ch then
  3356. operation_type_table^[opcode,3]:=operand_read;
  3357. if Ch_Wop4 in Ch then
  3358. operation_type_table^[opcode,3]:=operand_write;
  3359. if [Ch_RWop4,Ch_Mop4]*Ch<>[] then
  3360. operation_type_table^[opcode,3]:=operand_readwrite;
  3361. end;
  3362. end;
  3363. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  3364. begin
  3365. { the information in the instruction table is made for the string copy
  3366. operation MOVSD so hack here (FK)
  3367. VMOVSS and VMOVSD has two and three operand flavours, this cannot modelled by x86ins.dat
  3368. so fix it here (FK)
  3369. }
  3370. if ((opcode=A_MOVSD) or (opcode=A_VMOVSS) or (opcode=A_VMOVSD)) and (ops=2) then
  3371. begin
  3372. case opnr of
  3373. 0:
  3374. result:=operand_read;
  3375. 1:
  3376. result:=operand_write;
  3377. else
  3378. internalerror(200506055);
  3379. end
  3380. end
  3381. { IMUL has 1, 2 and 3-operand forms }
  3382. else if opcode=A_IMUL then
  3383. begin
  3384. case ops of
  3385. 1:
  3386. if opnr=0 then
  3387. result:=operand_read
  3388. else
  3389. internalerror(2014011802);
  3390. 2:
  3391. begin
  3392. case opnr of
  3393. 0:
  3394. result:=operand_read;
  3395. 1:
  3396. result:=operand_readwrite;
  3397. else
  3398. internalerror(2014011803);
  3399. end;
  3400. end;
  3401. 3:
  3402. begin
  3403. case opnr of
  3404. 0,1:
  3405. result:=operand_read;
  3406. 2:
  3407. result:=operand_write;
  3408. else
  3409. internalerror(2014011804);
  3410. end;
  3411. end;
  3412. else
  3413. internalerror(2014011805);
  3414. end;
  3415. end
  3416. else
  3417. result:=operation_type_table^[opcode,opnr];
  3418. end;
  3419. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  3420. var
  3421. tmpref: treference;
  3422. begin
  3423. tmpref:=ref;
  3424. {$ifdef i8086}
  3425. if tmpref.segment=NR_SS then
  3426. tmpref.segment:=NR_NO;
  3427. {$endif i8086}
  3428. case getregtype(r) of
  3429. R_INTREGISTER :
  3430. begin
  3431. if getsubreg(r)=R_SUBH then
  3432. inc(tmpref.offset);
  3433. { we don't need special code here for 32 bit loads on x86_64, since
  3434. those will automatically zero-extend the upper 32 bits. }
  3435. result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),tmpref,r);
  3436. end;
  3437. R_MMREGISTER :
  3438. if current_settings.fputype in fpu_avx_instructionsets then
  3439. case getsubreg(r) of
  3440. R_SUBMMD:
  3441. result:=taicpu.op_ref_reg(A_VMOVSD,S_NO,tmpref,r);
  3442. R_SUBMMS:
  3443. result:=taicpu.op_ref_reg(A_VMOVSS,S_NO,tmpref,r);
  3444. R_SUBQ,
  3445. R_SUBMMWHOLE:
  3446. result:=taicpu.op_ref_reg(A_VMOVQ,S_NO,tmpref,r);
  3447. else
  3448. internalerror(200506043);
  3449. end
  3450. else
  3451. case getsubreg(r) of
  3452. R_SUBMMD:
  3453. result:=taicpu.op_ref_reg(A_MOVSD,S_NO,tmpref,r);
  3454. R_SUBMMS:
  3455. result:=taicpu.op_ref_reg(A_MOVSS,S_NO,tmpref,r);
  3456. R_SUBQ,
  3457. R_SUBMMWHOLE:
  3458. result:=taicpu.op_ref_reg(A_MOVQ,S_NO,tmpref,r);
  3459. else
  3460. internalerror(200506043);
  3461. end;
  3462. else
  3463. internalerror(200401041);
  3464. end;
  3465. end;
  3466. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  3467. var
  3468. size: topsize;
  3469. tmpref: treference;
  3470. begin
  3471. tmpref:=ref;
  3472. {$ifdef i8086}
  3473. if tmpref.segment=NR_SS then
  3474. tmpref.segment:=NR_NO;
  3475. {$endif i8086}
  3476. case getregtype(r) of
  3477. R_INTREGISTER :
  3478. begin
  3479. if getsubreg(r)=R_SUBH then
  3480. inc(tmpref.offset);
  3481. size:=reg2opsize(r);
  3482. {$ifdef x86_64}
  3483. { even if it's a 32 bit reg, we still have to spill 64 bits
  3484. because we often perform 64 bit operations on them }
  3485. if (size=S_L) then
  3486. begin
  3487. size:=S_Q;
  3488. r:=newreg(getregtype(r),getsupreg(r),R_SUBWHOLE);
  3489. end;
  3490. {$endif x86_64}
  3491. result:=taicpu.op_reg_ref(A_MOV,size,r,tmpref);
  3492. end;
  3493. R_MMREGISTER :
  3494. if current_settings.fputype in fpu_avx_instructionsets then
  3495. case getsubreg(r) of
  3496. R_SUBMMD:
  3497. result:=taicpu.op_reg_ref(A_VMOVSD,S_NO,r,tmpref);
  3498. R_SUBMMS:
  3499. result:=taicpu.op_reg_ref(A_VMOVSS,S_NO,r,tmpref);
  3500. R_SUBQ,
  3501. R_SUBMMWHOLE:
  3502. result:=taicpu.op_reg_ref(A_VMOVQ,S_NO,r,tmpref);
  3503. else
  3504. internalerror(200506042);
  3505. end
  3506. else
  3507. case getsubreg(r) of
  3508. R_SUBMMD:
  3509. result:=taicpu.op_reg_ref(A_MOVSD,S_NO,r,tmpref);
  3510. R_SUBMMS:
  3511. result:=taicpu.op_reg_ref(A_MOVSS,S_NO,r,tmpref);
  3512. R_SUBQ,
  3513. R_SUBMMWHOLE:
  3514. result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,tmpref);
  3515. else
  3516. internalerror(200506042);
  3517. end;
  3518. else
  3519. internalerror(200401041);
  3520. end;
  3521. end;
  3522. {$ifdef i8086}
  3523. procedure taicpu.loadsegsymbol(opidx:longint;s:tasmsymbol);
  3524. var
  3525. r: treference;
  3526. begin
  3527. reference_reset_symbol(r,s,0,1,[]);
  3528. r.refaddr:=addr_seg;
  3529. loadref(opidx,r);
  3530. end;
  3531. {$endif i8086}
  3532. {*****************************************************************************
  3533. Instruction table
  3534. *****************************************************************************}
  3535. procedure BuildInsTabCache;
  3536. var
  3537. i : longint;
  3538. begin
  3539. new(instabcache);
  3540. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  3541. i:=0;
  3542. while (i<InsTabEntries) do
  3543. begin
  3544. if InsTabCache^[InsTab[i].OPcode]=-1 then
  3545. InsTabCache^[InsTab[i].OPcode]:=i;
  3546. inc(i);
  3547. end;
  3548. end;
  3549. procedure BuildInsTabMemRefSizeInfoCache;
  3550. var
  3551. AsmOp: TasmOp;
  3552. i,j: longint;
  3553. insentry : PInsEntry;
  3554. MRefInfo: TMemRefSizeInfo;
  3555. SConstInfo: TConstSizeInfo;
  3556. actRegSize: int64;
  3557. actMemSize: int64;
  3558. actConstSize: int64;
  3559. actRegCount: integer;
  3560. actMemCount: integer;
  3561. actConstCount: integer;
  3562. actRegTypes : int64;
  3563. actRegMemTypes: int64;
  3564. NewRegSize: int64;
  3565. actVMemCount : integer;
  3566. actVMemTypes : int64;
  3567. RegMMXSizeMask: int64;
  3568. RegXMMSizeMask: int64;
  3569. RegYMMSizeMask: int64;
  3570. bitcount: integer;
  3571. function bitcnt(aValue: int64): integer;
  3572. var
  3573. i: integer;
  3574. begin
  3575. result := 0;
  3576. for i := 0 to 63 do
  3577. begin
  3578. if (aValue mod 2) = 1 then
  3579. begin
  3580. inc(result);
  3581. end;
  3582. aValue := aValue shr 1;
  3583. end;
  3584. end;
  3585. begin
  3586. new(InsTabMemRefSizeInfoCache);
  3587. FillChar(InsTabMemRefSizeInfoCache^,sizeof(TInsTabMemRefSizeInfoCache),0);
  3588. for AsmOp := low(TAsmOp) to high(TAsmOp) do
  3589. begin
  3590. i := InsTabCache^[AsmOp];
  3591. if i >= 0 then
  3592. begin
  3593. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnkown;
  3594. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnkown;
  3595. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := false;
  3596. insentry:=@instab[i];
  3597. RegMMXSizeMask := 0;
  3598. RegXMMSizeMask := 0;
  3599. RegYMMSizeMask := 0;
  3600. while (insentry^.opcode=AsmOp) do
  3601. begin
  3602. MRefInfo := msiUnkown;
  3603. actRegSize := 0;
  3604. actRegCount := 0;
  3605. actRegTypes := 0;
  3606. NewRegSize := 0;
  3607. actMemSize := 0;
  3608. actMemCount := 0;
  3609. actRegMemTypes := 0;
  3610. actVMemCount := 0;
  3611. actVMemTypes := 0;
  3612. actConstSize := 0;
  3613. actConstCount := 0;
  3614. for j := 0 to insentry^.ops -1 do
  3615. begin
  3616. if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR
  3617. ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR
  3618. ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR
  3619. ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) then
  3620. begin
  3621. inc(actVMemCount);
  3622. case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64) of
  3623. OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32;
  3624. OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64;
  3625. OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32;
  3626. OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64;
  3627. else InternalError(777206);
  3628. end;
  3629. end
  3630. else if (insentry^.optypes[j] and OT_REGISTER) = OT_REGISTER then
  3631. begin
  3632. inc(actRegCount);
  3633. NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK);
  3634. if NewRegSize = 0 then
  3635. begin
  3636. case insentry^.optypes[j] and (OT_MMXREG OR OT_XMMREG OR OT_YMMREG) of
  3637. OT_MMXREG: begin
  3638. NewRegSize := OT_BITS64;
  3639. end;
  3640. OT_XMMREG: begin
  3641. NewRegSize := OT_BITS128;
  3642. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  3643. end;
  3644. OT_YMMREG: begin
  3645. NewRegSize := OT_BITS256;
  3646. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  3647. end;
  3648. else NewRegSize := not(0);
  3649. end;
  3650. end;
  3651. actRegSize := actRegSize or NewRegSize;
  3652. actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG OR OT_XMMREG OR OT_YMMREG));
  3653. end
  3654. else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then
  3655. begin
  3656. inc(actMemCount);
  3657. actMemSize:=actMemSize or (insentry^.optypes[j] and OT_SIZE_MASK);
  3658. if (insentry^.optypes[j] and OT_REGMEM) = OT_REGMEM then
  3659. begin
  3660. actRegMemTypes := actRegMemTypes or insentry^.optypes[j];
  3661. end;
  3662. end
  3663. else if ((insentry^.optypes[j] and OT_IMMEDIATE) = OT_IMMEDIATE) then
  3664. begin
  3665. inc(actConstCount);
  3666. actConstSize := actConstSize or (insentry^.optypes[j] and OT_SIZE_MASK);
  3667. end
  3668. end;
  3669. if actConstCount > 0 then
  3670. begin
  3671. case actConstSize of
  3672. 0: SConstInfo := csiNoSize;
  3673. OT_BITS8: SConstInfo := csiMem8;
  3674. OT_BITS16: SConstInfo := csiMem16;
  3675. OT_BITS32: SConstInfo := csiMem32;
  3676. OT_BITS64: SConstInfo := csiMem64;
  3677. else SConstInfo := csiMultiple;
  3678. end;
  3679. if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize = csiUnkown then
  3680. begin
  3681. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := SConstInfo;
  3682. end
  3683. else if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize <> SConstInfo then
  3684. begin
  3685. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiMultiple;
  3686. end;
  3687. end;
  3688. if actVMemCount > 0 then
  3689. begin
  3690. if actVMemCount = 1 then
  3691. begin
  3692. if actVMemTypes > 0 then
  3693. begin
  3694. case actVMemTypes of
  3695. OT_XMEM32: MRefInfo := msiXMem32;
  3696. OT_XMEM64: MRefInfo := msiXMem64;
  3697. OT_YMEM32: MRefInfo := msiYMem32;
  3698. OT_YMEM64: MRefInfo := msiYMem64;
  3699. else InternalError(777208);
  3700. end;
  3701. case actRegTypes of
  3702. OT_XMMREG: case MRefInfo of
  3703. msiXMem32,
  3704. msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128;
  3705. msiYMem32,
  3706. msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256;
  3707. else InternalError(777210);
  3708. end;
  3709. OT_YMMREG: case MRefInfo of
  3710. msiXMem32,
  3711. msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128;
  3712. msiYMem32,
  3713. msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256;
  3714. else InternalError(777211);
  3715. end;
  3716. //else InternalError(777209);
  3717. end;
  3718. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnkown then
  3719. begin
  3720. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo;
  3721. end
  3722. else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then
  3723. begin
  3724. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64] then
  3725. begin
  3726. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple;
  3727. end
  3728. else InternalError(777212);
  3729. end;
  3730. end;
  3731. end
  3732. else InternalError(777207);
  3733. end
  3734. else
  3735. begin
  3736. if (actMemCount=2) and ((AsmOp=A_MOVS) or (AsmOp=A_CMPS)) then
  3737. actMemCount:=1;
  3738. case actMemCount of
  3739. 0: ; // nothing todo
  3740. 1: begin
  3741. MRefInfo := msiUnkown;
  3742. case actRegMemTypes and (OT_MMXRM OR OT_XMMRM OR OT_YMMRM) of
  3743. OT_MMXRM: actMemSize := actMemSize or OT_BITS64;
  3744. OT_XMMRM: actMemSize := actMemSize or OT_BITS128;
  3745. OT_YMMRM: actMemSize := actMemSize or OT_BITS256;
  3746. end;
  3747. case actMemSize of
  3748. 0: MRefInfo := msiNoSize;
  3749. OT_BITS8: MRefInfo := msiMem8;
  3750. OT_BITS16: MRefInfo := msiMem16;
  3751. OT_BITS32: MRefInfo := msiMem32;
  3752. OT_BITS64: MRefInfo := msiMem64;
  3753. OT_BITS128: MRefInfo := msiMem128;
  3754. OT_BITS256: MRefInfo := msiMem256;
  3755. OT_BITS80,
  3756. OT_FAR,
  3757. OT_NEAR,
  3758. OT_SHORT: ; // ignore
  3759. else
  3760. begin
  3761. bitcount := bitcnt(actMemSize);
  3762. if bitcount > 1 then MRefInfo := msiMultiple
  3763. else InternalError(777203);
  3764. end;
  3765. end;
  3766. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnkown then
  3767. begin
  3768. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo;
  3769. end
  3770. else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then
  3771. begin
  3772. with InsTabMemRefSizeInfoCache^[AsmOp] do
  3773. begin
  3774. if ((MemRefSize = msiMem8) OR (MRefInfo = msiMem8)) then MemRefSize := msiMultiple8
  3775. else if ((MemRefSize = msiMem16) OR (MRefInfo = msiMem16)) then MemRefSize := msiMultiple16
  3776. else if ((MemRefSize = msiMem32) OR (MRefInfo = msiMem32)) then MemRefSize := msiMultiple32
  3777. else if ((MemRefSize = msiMem64) OR (MRefInfo = msiMem64)) then MemRefSize := msiMultiple64
  3778. else if ((MemRefSize = msiMem128) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultiple128
  3779. else if ((MemRefSize = msiMem256) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultiple256
  3780. else MemRefSize := msiMultiple;
  3781. end;
  3782. end;
  3783. if actRegCount > 0 then
  3784. begin
  3785. case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG) of
  3786. OT_MMXREG: RegMMXSizeMask := RegMMXSizeMask or actMemSize;
  3787. OT_XMMREG: RegXMMSizeMask := RegXMMSizeMask or actMemSize;
  3788. OT_YMMREG: RegYMMSizeMask := RegYMMSizeMask or actMemSize;
  3789. else begin
  3790. RegMMXSizeMask := not(0);
  3791. RegXMMSizeMask := not(0);
  3792. RegYMMSizeMask := not(0);
  3793. end;
  3794. end;
  3795. end;
  3796. end;
  3797. else InternalError(777202);
  3798. end;
  3799. end;
  3800. inc(insentry);
  3801. end;
  3802. if (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples) and
  3803. (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX)then
  3804. begin
  3805. case RegXMMSizeMask of
  3806. OT_BITS16: case RegYMMSizeMask of
  3807. OT_BITS32: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32;
  3808. end;
  3809. OT_BITS32: case RegYMMSizeMask of
  3810. OT_BITS64: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64;
  3811. end;
  3812. OT_BITS64: case RegYMMSizeMask of
  3813. OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128;
  3814. OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256;
  3815. end;
  3816. OT_BITS128: begin
  3817. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiVMemMultiple then
  3818. begin
  3819. // vector-memory-operand AVX2 (e.g. VGATHER..)
  3820. case RegYMMSizeMask of
  3821. OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemRegSize;
  3822. end;
  3823. end
  3824. else if RegMMXSizeMask = 0 then
  3825. begin
  3826. case RegYMMSizeMask of
  3827. OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128;
  3828. OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize;
  3829. end;
  3830. end
  3831. else if RegYMMSizeMask = 0 then
  3832. begin
  3833. case RegMMXSizeMask of
  3834. OT_BITS64: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize;
  3835. end;
  3836. end
  3837. else InternalError(777205);
  3838. end;
  3839. end;
  3840. end;
  3841. end;
  3842. end;
  3843. for AsmOp := low(TAsmOp) to high(TAsmOp) do
  3844. begin
  3845. // only supported intructiones with SSE- or AVX-operands
  3846. if not(InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) then
  3847. begin
  3848. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnkown;
  3849. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnkown;
  3850. end;
  3851. end;
  3852. end;
  3853. procedure InitAsm;
  3854. begin
  3855. build_spilling_operation_type_table;
  3856. if not assigned(instabcache) then
  3857. BuildInsTabCache;
  3858. if not assigned(InsTabMemRefSizeInfoCache) then
  3859. BuildInsTabMemRefSizeInfoCache;
  3860. end;
  3861. procedure DoneAsm;
  3862. begin
  3863. if assigned(operation_type_table) then
  3864. begin
  3865. dispose(operation_type_table);
  3866. operation_type_table:=nil;
  3867. end;
  3868. if assigned(instabcache) then
  3869. begin
  3870. dispose(instabcache);
  3871. instabcache:=nil;
  3872. end;
  3873. if assigned(InsTabMemRefSizeInfoCache) then
  3874. begin
  3875. dispose(InsTabMemRefSizeInfoCache);
  3876. InsTabMemRefSizeInfoCache:=nil;
  3877. end;
  3878. end;
  3879. begin
  3880. cai_align:=tai_align;
  3881. cai_cpu:=taicpu;
  3882. end.