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aasmcpu.pas
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d0ae800da6
+ MIPS: Use INS and EXT instructions for bit manipulations when target CPU type is set to mips32r2.
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%!s(int64=12) %!d(string=hai) anos |
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aoptcpu.pas
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8e6d4b41e2
+ MIPS: started the peephole optimizer.
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%!s(int64=12) %!d(string=hai) anos |
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aoptcpub.pas
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93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
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%!s(int64=13) %!d(string=hai) anos |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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%!s(int64=16) %!d(string=hai) anos |
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cgcpu.pas
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9494fadf08
* MIPS: set pi_do_call flag for assembler procedures with stackframes, so in PIC mode it further receives pi_needs_got in PIC mode and allocates the GP save temp.
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%!s(int64=12) %!d(string=hai) anos |
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cpubase.pas
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f80ce76a69
+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.
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%!s(int64=12) %!d(string=hai) anos |
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cpuelf.pas
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e7f6b06969
+ MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265.
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%!s(int64=12) %!d(string=hai) anos |
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cpugas.pas
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456f991c51
* MIPS: 3-operand forms of DIV and DIVU are not macros if first operand is $zero.
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%!s(int64=12) %!d(string=hai) anos |
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cpuinfo.pas
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1c84c3edbf
* Fixed label optimizer to work with MIPS, and enabled level 1 optimization for MIPS targets.
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%!s(int64=12) %!d(string=hai) anos |
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cpunode.pas
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a3ef2b42a8
Remove more TABs in sources
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%!s(int64=13) %!d(string=hai) anos |
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cpupara.pas
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c3350d13f9
* MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp.
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%!s(int64=12) %!d(string=hai) anos |
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cpupi.pas
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404c3efa58
* MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary.
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%!s(int64=12) %!d(string=hai) anos |
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cputarg.pas
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32ffddaad8
+ ELF linker back-ends for ARM and MIPS.
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%!s(int64=12) %!d(string=hai) anos |
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hlcgcpu.pas
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d0ae800da6
+ MIPS: Use INS and EXT instructions for bit manipulations when target CPU type is set to mips32r2.
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%!s(int64=12) %!d(string=hai) anos |
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itcpugas.pas
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3d2a27c66c
* fix fpu register type
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%!s(int64=13) %!d(string=hai) anos |
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mipsreg.dat
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944d500d55
Change std reg names to allow use with GAS assembler
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%!s(int64=13) %!d(string=hai) anos |
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ncpuadd.pas
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f80ce76a69
+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.
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%!s(int64=12) %!d(string=hai) anos |
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ncpucall.pas
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a3ef2b42a8
Remove more TABs in sources
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%!s(int64=13) %!d(string=hai) anos |
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ncpucnv.pas
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f80ce76a69
+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.
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%!s(int64=12) %!d(string=hai) anos |
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ncpuinln.pas
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404c3efa58
* MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary.
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%!s(int64=12) %!d(string=hai) anos |
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ncpuld.pas
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4b820a1ca5
- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.
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%!s(int64=12) %!d(string=hai) anos |
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ncpumat.pas
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f80ce76a69
+ MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.
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%!s(int64=12) %!d(string=hai) anos |
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ncpuset.pas
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121271c38f
* MIPS case node: simplified code a bit.
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%!s(int64=12) %!d(string=hai) anos |
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opcode.inc
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828309e61d
- MIPS: removed opcodes that are not in any known documentation.
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%!s(int64=12) %!d(string=hai) anos |
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racpugas.pas
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2868a30cce
+ Added mips32r2 opcodes needed for pic32.
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%!s(int64=12) %!d(string=hai) anos |
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rgcpu.pas
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8b8553991a
+ MIPS: prevent coalescing written-to registers with $sp,$fp,$zero and $at.
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%!s(int64=12) %!d(string=hai) anos |
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rmipscon.inc
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de4a96f96d
* fixes several register allocation related mips issues
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%!s(int64=13) %!d(string=hai) anos |
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rmipsdwf.inc
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f58fcdf401
+ basic mips stuff
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%!s(int64=20) %!d(string=hai) anos |
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rmipsgas.inc
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ae37b9f5b9
* fix floating point registers gas name
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%!s(int64=13) %!d(string=hai) anos |
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rmipsgri.inc
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ae37b9f5b9
* fix floating point registers gas name
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%!s(int64=13) %!d(string=hai) anos |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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%!s(int64=20) %!d(string=hai) anos |
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rmipsnor.inc
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f58fcdf401
+ basic mips stuff
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%!s(int64=20) %!d(string=hai) anos |
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rmipsnum.inc
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de4a96f96d
* fixes several register allocation related mips issues
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%!s(int64=13) %!d(string=hai) anos |
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rmipsrni.inc
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f58fcdf401
+ basic mips stuff
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%!s(int64=20) %!d(string=hai) anos |
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rmipssri.inc
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944d500d55
Change std reg names to allow use with GAS assembler
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%!s(int64=13) %!d(string=hai) anos |
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rmipssta.inc
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f58fcdf401
+ basic mips stuff
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%!s(int64=20) %!d(string=hai) anos |
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rmipsstd.inc
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944d500d55
Change std reg names to allow use with GAS assembler
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%!s(int64=13) %!d(string=hai) anos |
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rmipssup.inc
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de4a96f96d
* fixes several register allocation related mips issues
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%!s(int64=13) %!d(string=hai) anos |
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strinst.inc
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828309e61d
- MIPS: removed opcodes that are not in any known documentation.
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%!s(int64=12) %!d(string=hai) anos |
sergei
e7f6b06969
+ MIPS internal linker: support TLS IE/LE and GPREL32 relocations, is now able to link tw14265.