cpuinfo.pas 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038
  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv6,
  31. cpu_armv7,
  32. cpu_armv7m
  33. );
  34. Const
  35. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  36. cpu_thumb = [];
  37. cpu_thumb2 = [cpu_armv7m];
  38. Type
  39. tfputype =
  40. (fpu_none,
  41. fpu_soft,
  42. fpu_libgcc,
  43. fpu_fpa,
  44. fpu_fpa10,
  45. fpu_fpa11,
  46. fpu_vfpv2,
  47. fpu_vfpv3,
  48. fpu_vfpv3_d16
  49. );
  50. tcontrollertype =
  51. (ct_none,
  52. { Phillips }
  53. ct_lpc2114,
  54. ct_lpc2124,
  55. ct_lpc2194,
  56. ct_lpc1768,
  57. { ATMEL }
  58. ct_at91sam7s256,
  59. ct_at91sam7se256,
  60. ct_at91sam7x256,
  61. ct_at91sam7xc256,
  62. { STMicroelectronics }
  63. ct_stm32f103rb,
  64. ct_stm32f103re,
  65. ct_stm32f103c4t,
  66. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  67. ct_lm3s1110,
  68. ct_lm3s1133,
  69. ct_lm3s1138,
  70. ct_lm3s1150,
  71. ct_lm3s1162,
  72. ct_lm3s1165,
  73. ct_lm3s1166,
  74. ct_lm3s2110,
  75. ct_lm3s2139,
  76. ct_lm3s6100,
  77. ct_lm3s6110,
  78. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  79. ct_lm3s1601,
  80. ct_lm3s1608,
  81. ct_lm3s1620,
  82. ct_lm3s1635,
  83. ct_lm3s1636,
  84. ct_lm3s1637,
  85. ct_lm3s1651,
  86. ct_lm3s2601,
  87. ct_lm3s2608,
  88. ct_lm3s2620,
  89. ct_lm3s2637,
  90. ct_lm3s2651,
  91. ct_lm3s6610,
  92. ct_lm3s6611,
  93. ct_lm3s6618,
  94. ct_lm3s6633,
  95. ct_lm3s6637,
  96. ct_lm3s8630,
  97. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  98. ct_lm3s1911,
  99. ct_lm3s1918,
  100. ct_lm3s1937,
  101. ct_lm3s1958,
  102. ct_lm3s1960,
  103. ct_lm3s1968,
  104. ct_lm3s1969,
  105. ct_lm3s2911,
  106. ct_lm3s2918,
  107. ct_lm3s2919,
  108. ct_lm3s2939,
  109. ct_lm3s2948,
  110. ct_lm3s2950,
  111. ct_lm3s2965,
  112. ct_lm3s6911,
  113. ct_lm3s6918,
  114. ct_lm3s6938,
  115. ct_lm3s6950,
  116. ct_lm3s6952,
  117. ct_lm3s6965,
  118. ct_lm3s8930,
  119. ct_lm3s8933,
  120. ct_lm3s8938,
  121. ct_lm3s8962,
  122. ct_lm3s8970,
  123. ct_lm3s8971,
  124. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  125. ct_lm3s5951,
  126. ct_lm3s5956,
  127. ct_lm3s1b21,
  128. ct_lm3s2b93,
  129. ct_lm3s5b91,
  130. ct_lm3s9b81,
  131. ct_lm3s9b90,
  132. ct_lm3s9b92,
  133. ct_lm3s9b95,
  134. ct_lm3s9b96,
  135. { SAMSUNG }
  136. ct_sc32442b,
  137. // generic Thumb2 target
  138. ct_thumb2bare
  139. );
  140. Const
  141. {# Size of native extended floating point type }
  142. extended_size = 12;
  143. {# Size of a multimedia register }
  144. mmreg_size = 16;
  145. { target cpu string (used by compiler options) }
  146. target_cpu_string = 'arm';
  147. { calling conventions supported by the code generator }
  148. supported_calling_conventions : tproccalloptions = [
  149. pocall_internproc,
  150. pocall_safecall,
  151. pocall_stdcall,
  152. { same as stdcall only different name mangling }
  153. pocall_cdecl,
  154. { same as stdcall only different name mangling }
  155. pocall_cppdecl,
  156. { same as stdcall but floating point numbers are handled like equal sized integers }
  157. pocall_softfloat,
  158. { same as stdcall (requires that all const records are passed by
  159. reference, but that's already done for stdcall) }
  160. pocall_mwpascal,
  161. { used for interrupt handling }
  162. pocall_interrupt
  163. ];
  164. cputypestr : array[tcputype] of string[8] = ('',
  165. 'ARMV3',
  166. 'ARMV4',
  167. 'ARMV4T',
  168. 'ARMV5',
  169. 'ARMV5T',
  170. 'ARMV6',
  171. 'ARMV7',
  172. 'ARMV7M'
  173. );
  174. fputypestr : array[tfputype] of string[9] = ('',
  175. 'SOFT',
  176. 'LIBGCC',
  177. 'FPA',
  178. 'FPA10',
  179. 'FPA11',
  180. 'VFPV2',
  181. 'VFPV3',
  182. 'VFPV3_D16'
  183. );
  184. { We know that there are fields after sramsize
  185. but we don't care about this warning }
  186. {$WARN 3177 OFF}
  187. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  188. ((
  189. controllertypestr:'';
  190. controllerunitstr:'';
  191. interruptvectors:0;
  192. flashbase:0;
  193. flashsize:0;
  194. srambase:0;
  195. sramsize:0
  196. ),
  197. (
  198. controllertypestr:'LPC2114';
  199. controllerunitstr:'LPC21x4';
  200. interruptvectors:8;
  201. flashbase:$00000000;
  202. flashsize:$00040000;
  203. srambase:$40000000;
  204. sramsize:$00004000
  205. ),
  206. (
  207. controllertypestr:'LPC2124';
  208. controllerunitstr:'LPC21x4';
  209. interruptvectors:8;
  210. flashbase:$00000000;
  211. flashsize:$00040000;
  212. srambase:$40000000;
  213. sramsize:$00004000
  214. ),
  215. (
  216. controllertypestr:'LPC2194';
  217. controllerunitstr:'LPC21x4';
  218. interruptvectors:8;
  219. flashbase:$00000000;
  220. flashsize:$00040000;
  221. srambase:$40000000;
  222. sramsize:$00004000
  223. ),
  224. (
  225. controllertypestr:'LPC1768';
  226. controllerunitstr:'LPC1768';
  227. interruptvectors:12;
  228. flashbase:$00000000;
  229. flashsize:$00040000;
  230. srambase:$10000000;
  231. sramsize:$00008000
  232. ),
  233. (
  234. controllertypestr:'AT91SAM7S256';
  235. controllerunitstr:'AT91SAM7x256';
  236. interruptvectors:8;
  237. flashbase:$00000000;
  238. flashsize:$00040000;
  239. srambase:$00200000;
  240. sramsize:$00010000
  241. ),
  242. (
  243. controllertypestr:'AT91SAM7SE256';
  244. controllerunitstr:'AT91SAM7x256';
  245. interruptvectors:8;
  246. flashbase:$00000000;
  247. flashsize:$00040000;
  248. srambase:$00200000;
  249. sramsize:$00010000
  250. ),
  251. (
  252. controllertypestr:'AT91SAM7X256';
  253. controllerunitstr:'AT91SAM7x256';
  254. interruptvectors:8;
  255. flashbase:$00000000;
  256. flashsize:$00040000;
  257. srambase:$00200000;
  258. sramsize:$00010000
  259. ),
  260. (
  261. controllertypestr:'AT91SAM7XC256';
  262. controllerunitstr:'AT91SAM7x256';
  263. interruptvectors:8;
  264. flashbase:$00000000;
  265. flashsize:$00040000;
  266. srambase:$00200000;
  267. sramsize:$00010000
  268. ),
  269. // ct_stm32f103rb,
  270. (
  271. controllertypestr:'STM32F103RB';
  272. controllerunitstr:'STM32F103';
  273. interruptvectors:12;
  274. flashbase:$08000000;
  275. flashsize:$00020000;
  276. srambase:$20000000;
  277. sramsize:$00005000
  278. ),
  279. // ct_stm32f103re,
  280. (
  281. controllertypestr:'STM32F103RE';
  282. controllerunitstr:'STM32F103';
  283. interruptvectors:12;
  284. flashbase:$08000000;
  285. flashsize:$00080000;
  286. srambase:$20000000;
  287. sramsize:$00010000
  288. ),
  289. // ct_stm32f103re,
  290. (
  291. controllertypestr:'STM32F103C4T';
  292. controllerunitstr:'STM32F103';
  293. interruptvectors:12;
  294. flashbase:$08000000;
  295. flashsize:$00004000;
  296. srambase:$20000000;
  297. sramsize:$00001800
  298. ),
  299. { TI - 64 K Flash, 16 K SRAM Devices }
  300. // ct_lm3s1110,
  301. (
  302. controllertypestr:'LM3S1110';
  303. controllerunitstr:'LM3FURY';
  304. interruptvectors:72;
  305. flashbase:$00000000;
  306. flashsize:$00010000;
  307. srambase:$20000000;
  308. sramsize:$00004000
  309. ),
  310. // ct_lm3s1133,
  311. (
  312. controllertypestr:'LM3S1133';
  313. controllerunitstr:'LM3FURY';
  314. interruptvectors:72;
  315. flashbase:$00000000;
  316. flashsize:$00010000;
  317. srambase:$20000000;
  318. sramsize:$00004000
  319. ),
  320. // ct_lm3s1138,
  321. (
  322. controllertypestr:'LM3S1138';
  323. controllerunitstr:'LM3FURY';
  324. interruptvectors:72;
  325. flashbase:$00000000;
  326. flashsize:$00010000;
  327. srambase:$20000000;
  328. sramsize:$00004000
  329. ),
  330. // ct_lm3s1150,
  331. (
  332. controllertypestr:'LM3S1150';
  333. controllerunitstr:'LM3FURY';
  334. interruptvectors:72;
  335. flashbase:$00000000;
  336. flashsize:$00010000;
  337. srambase:$20000000;
  338. sramsize:$00004000
  339. ),
  340. // ct_lm3s1162,
  341. (
  342. controllertypestr:'LM3S1162';
  343. controllerunitstr:'LM3FURY';
  344. interruptvectors:72;
  345. flashbase:$00000000;
  346. flashsize:$00010000;
  347. srambase:$20000000;
  348. sramsize:$00004000
  349. ),
  350. // ct_lm3s1165,
  351. (
  352. controllertypestr:'LM3S1165';
  353. controllerunitstr:'LM3FURY';
  354. interruptvectors:72;
  355. flashbase:$00000000;
  356. flashsize:$00010000;
  357. srambase:$20000000;
  358. sramsize:$00004000
  359. ),
  360. // ct_lm3s1166,
  361. (
  362. controllertypestr:'LM3S1166';
  363. controllerunitstr:'LM3FURY';
  364. interruptvectors:72;
  365. flashbase:$00000000;
  366. flashsize:$00010000;
  367. srambase:$20000000;
  368. sramsize:$00004000
  369. ),
  370. // ct_lm3s2110,
  371. (
  372. controllertypestr:'LM3S2110';
  373. controllerunitstr:'LM3FURY';
  374. interruptvectors:72;
  375. flashbase:$00000000;
  376. flashsize:$00010000;
  377. srambase:$20000000;
  378. sramsize:$00004000
  379. ),
  380. // ct_lm3s2139,
  381. (
  382. controllertypestr:'LM3S2139';
  383. controllerunitstr:'LM3FURY';
  384. interruptvectors:72;
  385. flashbase:$00000000;
  386. flashsize:$00010000;
  387. srambase:$20000000;
  388. sramsize:$00004000
  389. ),
  390. // ct_lm3s6100,
  391. (
  392. controllertypestr:'LM3S6100';
  393. controllerunitstr:'LM3FURY';
  394. interruptvectors:72;
  395. flashbase:$00000000;
  396. flashsize:$00010000;
  397. srambase:$20000000;
  398. sramsize:$00004000
  399. ),
  400. // ct_lm3s6110,
  401. (
  402. controllertypestr:'LM3S6110';
  403. controllerunitstr:'LM3FURY';
  404. interruptvectors:72;
  405. flashbase:$00000000;
  406. flashsize:$00010000;
  407. srambase:$20000000;
  408. sramsize:$00004000
  409. ),
  410. { TI - 128K Flash, 32K SRAM devices }
  411. // ct_lm3s1601,
  412. (
  413. controllertypestr:'LM3S1601';
  414. controllerunitstr:'LM3FURY';
  415. interruptvectors:72;
  416. flashbase:$00000000;
  417. flashsize:$00020000;
  418. srambase:$20000000;
  419. sramsize:$00008000
  420. ),
  421. // ct_lm3s1608,
  422. (
  423. controllertypestr:'LM3S1608';
  424. controllerunitstr:'LM3FURY';
  425. interruptvectors:72;
  426. flashbase:$00000000;
  427. flashsize:$00020000;
  428. srambase:$20000000;
  429. sramsize:$00008000
  430. ),
  431. // ct_lm3s1620,
  432. (
  433. controllertypestr:'LM3S1620';
  434. controllerunitstr:'LM3FURY';
  435. interruptvectors:72;
  436. flashbase:$00000000;
  437. flashsize:$00020000;
  438. srambase:$20000000;
  439. sramsize:$00008000
  440. ),
  441. // ct_lm3s1635,
  442. (
  443. controllertypestr:'LM3S1635';
  444. controllerunitstr:'LM3FURY';
  445. interruptvectors:72;
  446. flashbase:$00000000;
  447. flashsize:$00020000;
  448. srambase:$20000000;
  449. sramsize:$00008000
  450. ),
  451. // ct_lm3s1636,
  452. (
  453. controllertypestr:'LM3S1636';
  454. controllerunitstr:'LM3FURY';
  455. interruptvectors:72;
  456. flashbase:$00000000;
  457. flashsize:$00020000;
  458. srambase:$20000000;
  459. sramsize:$00008000
  460. ),
  461. // ct_lm3s1637,
  462. (
  463. controllertypestr:'LM3S1637';
  464. controllerunitstr:'LM3FURY';
  465. interruptvectors:72;
  466. flashbase:$00000000;
  467. flashsize:$00020000;
  468. srambase:$20000000;
  469. sramsize:$00008000
  470. ),
  471. // ct_lm3s1651,
  472. (
  473. controllertypestr:'LM3S1651';
  474. controllerunitstr:'LM3FURY';
  475. interruptvectors:72;
  476. flashbase:$00000000;
  477. flashsize:$00020000;
  478. srambase:$20000000;
  479. sramsize:$00008000
  480. ),
  481. // ct_lm3s2601,
  482. (
  483. controllertypestr:'LM3S2601';
  484. controllerunitstr:'LM3FURY';
  485. interruptvectors:72;
  486. flashbase:$00000000;
  487. flashsize:$00020000;
  488. srambase:$20000000;
  489. sramsize:$00008000
  490. ),
  491. // ct_lm3s2608,
  492. (
  493. controllertypestr:'LM3S2608';
  494. controllerunitstr:'LM3FURY';
  495. interruptvectors:72;
  496. flashbase:$00000000;
  497. flashsize:$00020000;
  498. srambase:$20000000;
  499. sramsize:$00008000
  500. ),
  501. // ct_lm3s2620,
  502. (
  503. controllertypestr:'LM3S2620';
  504. controllerunitstr:'LM3FURY';
  505. interruptvectors:72;
  506. flashbase:$00000000;
  507. flashsize:$00020000;
  508. srambase:$20000000;
  509. sramsize:$00008000
  510. ),
  511. // ct_lm3s2637,
  512. (
  513. controllertypestr:'LM3S2637';
  514. controllerunitstr:'LM3FURY';
  515. interruptvectors:72;
  516. flashbase:$00000000;
  517. flashsize:$00020000;
  518. srambase:$20000000;
  519. sramsize:$00008000
  520. ),
  521. // ct_lm3s2651,
  522. (
  523. controllertypestr:'LM3S2651';
  524. controllerunitstr:'LM3FURY';
  525. interruptvectors:72;
  526. flashbase:$00000000;
  527. flashsize:$00020000;
  528. srambase:$20000000;
  529. sramsize:$00008000
  530. ),
  531. // ct_lm3s6610,
  532. (
  533. controllertypestr:'LM3S6610';
  534. controllerunitstr:'LM3FURY';
  535. interruptvectors:72;
  536. flashbase:$00000000;
  537. flashsize:$00020000;
  538. srambase:$20000000;
  539. sramsize:$00008000
  540. ),
  541. // ct_lm3s6611,
  542. (
  543. controllertypestr:'LM3S6611';
  544. controllerunitstr:'LM3FURY';
  545. interruptvectors:72;
  546. flashbase:$00000000;
  547. flashsize:$00020000;
  548. srambase:$20000000;
  549. sramsize:$00008000
  550. ),
  551. // ct_lm3s6618,
  552. (
  553. controllertypestr:'LM3S6618';
  554. controllerunitstr:'LM3FURY';
  555. interruptvectors:72;
  556. flashbase:$00000000;
  557. flashsize:$00020000;
  558. srambase:$20000000;
  559. sramsize:$00008000
  560. ),
  561. // ct_lm3s6633,
  562. (
  563. controllertypestr:'LM3S6633';
  564. controllerunitstr:'LM3FURY';
  565. interruptvectors:72;
  566. flashbase:$00000000;
  567. flashsize:$00020000;
  568. srambase:$20000000;
  569. sramsize:$00008000
  570. ),
  571. // ct_lm3s6637,
  572. (
  573. controllertypestr:'LM3S6637';
  574. controllerunitstr:'LM3FURY';
  575. interruptvectors:72;
  576. flashbase:$00000000;
  577. flashsize:$00020000;
  578. srambase:$20000000;
  579. sramsize:$00008000
  580. ),
  581. // ct_lm3s8630,
  582. (
  583. controllertypestr:'LM3S8630';
  584. controllerunitstr:'LM3FURY';
  585. interruptvectors:72;
  586. flashbase:$00000000;
  587. flashsize:$00020000;
  588. srambase:$20000000;
  589. sramsize:$00008000
  590. ),
  591. { TI - 256K Flash, 64K SRAM devices }
  592. // ct_lm3s1911,
  593. (
  594. controllertypestr:'LM3S1911';
  595. controllerunitstr:'LM3FURY';
  596. interruptvectors:72;
  597. flashbase:$00000000;
  598. flashsize:$00040000;
  599. srambase:$20000000;
  600. sramsize:$00010000
  601. ),
  602. // ct_lm3s1918,
  603. (
  604. controllertypestr:'LM3S1918';
  605. controllerunitstr:'LM3FURY';
  606. interruptvectors:72;
  607. flashbase:$00000000;
  608. flashsize:$00040000;
  609. srambase:$20000000;
  610. sramsize:$00010000
  611. ),
  612. // ct_lm3s1937,
  613. (
  614. controllertypestr:'LM3S1937';
  615. controllerunitstr:'LM3FURY';
  616. interruptvectors:72;
  617. flashbase:$00000000;
  618. flashsize:$00040000;
  619. srambase:$20000000;
  620. sramsize:$00010000
  621. ),
  622. // ct_lm3s1958,
  623. (
  624. controllertypestr:'LM3S1958';
  625. controllerunitstr:'LM3FURY';
  626. interruptvectors:72;
  627. flashbase:$00000000;
  628. flashsize:$00040000;
  629. srambase:$20000000;
  630. sramsize:$00010000
  631. ),
  632. // ct_lm3s1960,
  633. (
  634. controllertypestr:'LM3S1960';
  635. controllerunitstr:'LM3FURY';
  636. interruptvectors:72;
  637. flashbase:$00000000;
  638. flashsize:$00040000;
  639. srambase:$20000000;
  640. sramsize:$00010000
  641. ),
  642. // ct_lm3s1968,
  643. (
  644. controllertypestr:'LM3S1968';
  645. controllerunitstr:'LM3FURY';
  646. interruptvectors:72;
  647. flashbase:$00000000;
  648. flashsize:$00040000;
  649. srambase:$20000000;
  650. sramsize:$00010000
  651. ),
  652. // ct_lm3s1969,
  653. (
  654. controllertypestr:'LM3S1969';
  655. controllerunitstr:'LM3FURY';
  656. interruptvectors:72;
  657. flashbase:$00000000;
  658. flashsize:$00040000;
  659. srambase:$20000000;
  660. sramsize:$00010000
  661. ),
  662. // ct_lm3s2911,
  663. (
  664. controllertypestr:'LM3S2911';
  665. controllerunitstr:'LM3FURY';
  666. interruptvectors:72;
  667. flashbase:$00000000;
  668. flashsize:$00040000;
  669. srambase:$20000000;
  670. sramsize:$00010000
  671. ),
  672. // ct_lm3s2918,
  673. (
  674. controllertypestr:'LM3S2918';
  675. controllerunitstr:'LM3FURY';
  676. interruptvectors:72;
  677. flashbase:$00000000;
  678. flashsize:$00040000;
  679. srambase:$20000000;
  680. sramsize:$00010000
  681. ),
  682. // ct_lm3s2919,
  683. (
  684. controllertypestr:'LM3S2919';
  685. controllerunitstr:'LM3FURY';
  686. interruptvectors:72;
  687. flashbase:$00000000;
  688. flashsize:$00040000;
  689. srambase:$20000000;
  690. sramsize:$00010000
  691. ),
  692. // ct_lm3s2939,
  693. (
  694. controllertypestr:'LM3S2939';
  695. controllerunitstr:'LM3FURY';
  696. interruptvectors:72;
  697. flashbase:$00000000;
  698. flashsize:$00040000;
  699. srambase:$20000000;
  700. sramsize:$00010000
  701. ),
  702. // ct_lm3s2948,
  703. (
  704. controllertypestr:'LM3S2948';
  705. controllerunitstr:'LM3FURY';
  706. interruptvectors:72;
  707. flashbase:$00000000;
  708. flashsize:$00040000;
  709. srambase:$20000000;
  710. sramsize:$00010000
  711. ),
  712. // ct_lm3s2950,
  713. (
  714. controllertypestr:'LM3S2950';
  715. controllerunitstr:'LM3FURY';
  716. interruptvectors:72;
  717. flashbase:$00000000;
  718. flashsize:$00040000;
  719. srambase:$20000000;
  720. sramsize:$00010000
  721. ),
  722. // ct_lm3s2965,
  723. (
  724. controllertypestr:'LM3S2965';
  725. controllerunitstr:'LM3FURY';
  726. interruptvectors:72;
  727. flashbase:$00000000;
  728. flashsize:$00040000;
  729. srambase:$20000000;
  730. sramsize:$00010000
  731. ),
  732. // ct_lm3s6911,
  733. (
  734. controllertypestr:'LM3S6911';
  735. controllerunitstr:'LM3FURY';
  736. interruptvectors:72;
  737. flashbase:$00000000;
  738. flashsize:$00040000;
  739. srambase:$20000000;
  740. sramsize:$00010000
  741. ),
  742. // ct_lm3s6918,
  743. (
  744. controllertypestr:'LM3S6918';
  745. controllerunitstr:'LM3FURY';
  746. interruptvectors:72;
  747. flashbase:$00000000;
  748. flashsize:$00040000;
  749. srambase:$20000000;
  750. sramsize:$00010000
  751. ),
  752. // ct_lm3s6938,
  753. (
  754. controllertypestr:'LM3S6938';
  755. controllerunitstr:'LM3FURY';
  756. interruptvectors:72;
  757. flashbase:$00000000;
  758. flashsize:$00040000;
  759. srambase:$20000000;
  760. sramsize:$00010000
  761. ),
  762. // ct_lm3s6950,
  763. (
  764. controllertypestr:'LM3S6950';
  765. controllerunitstr:'LM3FURY';
  766. interruptvectors:72;
  767. flashbase:$00000000;
  768. flashsize:$00040000;
  769. srambase:$20000000;
  770. sramsize:$00010000
  771. ),
  772. // ct_lm3s6952,
  773. (
  774. controllertypestr:'LM3S6952';
  775. controllerunitstr:'LM3FURY';
  776. interruptvectors:72;
  777. flashbase:$00000000;
  778. flashsize:$00040000;
  779. srambase:$20000000;
  780. sramsize:$00010000
  781. ),
  782. // ct_lm3s6965,
  783. (
  784. controllertypestr:'LM3S6965';
  785. controllerunitstr:'LM3FURY';
  786. interruptvectors:72;
  787. flashbase:$00000000;
  788. flashsize:$00040000;
  789. srambase:$20000000;
  790. sramsize:$00010000
  791. ),
  792. // ct_lm3s8930,
  793. (
  794. controllertypestr:'LM3S8930';
  795. controllerunitstr:'LM3FURY';
  796. interruptvectors:72;
  797. flashbase:$00000000;
  798. flashsize:$00040000;
  799. srambase:$20000000;
  800. sramsize:$00010000
  801. ),
  802. // ct_lm3s8933,
  803. (
  804. controllertypestr:'LM3S8933';
  805. controllerunitstr:'LM3FURY';
  806. interruptvectors:72;
  807. flashbase:$00000000;
  808. flashsize:$00040000;
  809. srambase:$20000000;
  810. sramsize:$00010000
  811. ),
  812. // ct_lm3s8938,
  813. (
  814. controllertypestr:'LM3S8938';
  815. controllerunitstr:'LM3FURY';
  816. interruptvectors:72;
  817. flashbase:$00000000;
  818. flashsize:$00040000;
  819. srambase:$20000000;
  820. sramsize:$00010000
  821. ),
  822. // ct_lm3s8962,
  823. (
  824. controllertypestr:'LM3S8962';
  825. controllerunitstr:'LM3FURY';
  826. interruptvectors:72;
  827. flashbase:$00000000;
  828. flashsize:$00040000;
  829. srambase:$20000000;
  830. sramsize:$00010000
  831. ),
  832. // ct_lm3s8970,
  833. (
  834. controllertypestr:'LM3S8970';
  835. controllerunitstr:'LM3FURY';
  836. interruptvectors:72;
  837. flashbase:$00000000;
  838. flashsize:$00040000;
  839. srambase:$20000000;
  840. sramsize:$00010000
  841. ),
  842. // ct_lm3s8971,
  843. (
  844. controllertypestr:'LM3S8971';
  845. controllerunitstr:'LM3FURY';
  846. interruptvectors:72;
  847. flashbase:$00000000;
  848. flashsize:$00040000;
  849. srambase:$20000000;
  850. sramsize:$00010000
  851. ),
  852. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  853. // ct_lm3s5951,
  854. (
  855. controllertypestr:'LM3S5951';
  856. controllerunitstr:'LM3TEMPEST';
  857. interruptvectors:72;
  858. flashbase:$00000000;
  859. flashsize:$00040000;
  860. srambase:$20000000;
  861. sramsize:$00010000
  862. ),
  863. // ct_lm3s5956,
  864. (
  865. controllertypestr:'LM3S5956';
  866. controllerunitstr:'LM3TEMPEST';
  867. interruptvectors:72;
  868. flashbase:$00000000;
  869. flashsize:$00040000;
  870. srambase:$20000000;
  871. sramsize:$00010000
  872. ),
  873. // ct_lm3s1b21,
  874. (
  875. controllertypestr:'LM3S1B21';
  876. controllerunitstr:'LM3TEMPEST';
  877. interruptvectors:72;
  878. flashbase:$00000000;
  879. flashsize:$00040000;
  880. srambase:$20000000;
  881. sramsize:$00010000
  882. ),
  883. // ct_lm3s2b93,
  884. (
  885. controllertypestr:'LM3S2B93';
  886. controllerunitstr:'LM3TEMPEST';
  887. interruptvectors:72;
  888. flashbase:$00000000;
  889. flashsize:$00040000;
  890. srambase:$20000000;
  891. sramsize:$00010000
  892. ),
  893. // ct_lm3s5b91,
  894. (
  895. controllertypestr:'LM3S5B91';
  896. controllerunitstr:'LM3TEMPEST';
  897. interruptvectors:72;
  898. flashbase:$00000000;
  899. flashsize:$00040000;
  900. srambase:$20000000;
  901. sramsize:$00010000
  902. ),
  903. // ct_lm3s9b81,
  904. (
  905. controllertypestr:'LM3S9B81';
  906. controllerunitstr:'LM3TEMPEST';
  907. interruptvectors:72;
  908. flashbase:$00000000;
  909. flashsize:$00040000;
  910. srambase:$20000000;
  911. sramsize:$00010000
  912. ),
  913. // ct_lm3s9b90,
  914. (
  915. controllertypestr:'LM3S9B90';
  916. controllerunitstr:'LM3TEMPEST';
  917. interruptvectors:72;
  918. flashbase:$00000000;
  919. flashsize:$00040000;
  920. srambase:$20000000;
  921. sramsize:$00010000
  922. ),
  923. // ct_lm3s9b92,
  924. (
  925. controllertypestr:'LM3S9B92';
  926. controllerunitstr:'LM3TEMPEST';
  927. interruptvectors:72;
  928. flashbase:$00000000;
  929. flashsize:$00040000;
  930. srambase:$20000000;
  931. sramsize:$00010000
  932. ),
  933. // ct_lm3s9b95,
  934. (
  935. controllertypestr:'LM3S9B95';
  936. controllerunitstr:'LM3TEMPEST';
  937. interruptvectors:72;
  938. flashbase:$00000000;
  939. flashsize:$00040000;
  940. srambase:$20000000;
  941. sramsize:$00010000
  942. ),
  943. // ct_lm3s9b96,
  944. (
  945. controllertypestr:'LM3S9B96';
  946. controllerunitstr:'LM3TEMPEST';
  947. interruptvectors:72;
  948. flashbase:$00000000;
  949. flashsize:$00040000;
  950. srambase:$20000000;
  951. sramsize:$00010000
  952. ),
  953. //ct_SC32442b,
  954. (
  955. controllertypestr:'SC32442B';
  956. controllerunitstr:'sc32442b';
  957. interruptvectors:7;
  958. flashbase:$00000000;
  959. flashsize:$00000000;
  960. srambase:$00000000;
  961. sramsize:$08000000
  962. ),
  963. // bare bones Thumb2
  964. (
  965. controllertypestr:'THUMB2_BARE';
  966. controllerunitstr:'THUMB2_BARE';
  967. interruptvectors:128;
  968. flashbase:$00000000;
  969. flashsize:$00100000;
  970. srambase:$20000000;
  971. sramsize:$00100000
  972. )
  973. );
  974. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16];
  975. { Supported optimizations, only used for information }
  976. supported_optimizerswitches = genericlevel1optimizerswitches+
  977. genericlevel2optimizerswitches+
  978. genericlevel3optimizerswitches-
  979. { no need to write info about those }
  980. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  981. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  982. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields];
  983. level1optimizerswitches = genericlevel1optimizerswitches;
  984. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  985. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse {,cs_opt_scheduler}];
  986. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  987. Implementation
  988. end.