| .. |
|
aoptcpu.pas
|
19c8abac0b
+ enable jump optimizer for i8086
|
12 lat temu |
|
aoptcpub.pas
|
19c8abac0b
+ enable jump optimizer for i8086
|
12 lat temu |
|
aoptcpud.pas
|
19c8abac0b
+ enable jump optimizer for i8086
|
12 lat temu |
|
cgcpu.pas
|
791cd932fd
+ support i8086 far data memory models in tcg8086.g_intf_wrapper
|
11 lat temu |
|
cpubase.inc
|
c48d572996
Implement support for saving and restoring address registers.
|
12 lat temu |
|
cpuinfo.pas
|
c003f934c5
* Included cs_opt_peephole into genericlevel1optimizerswitches, so it is re-enabled for all targets after r27106.
|
11 lat temu |
|
cpunode.pas
|
3cc8ff11e3
+ generate the stack segment for i8086 far data memory models from within fpc
|
11 lat temu |
|
cpupara.pas
|
3dfc6ac7e1
* fixed the passing of extended floating type parameters on i8086 for
|
11 lat temu |
|
cpupi.pas
|
c916105db8
- rm ti8086procinfo.allocate_got_register as it isn't used on the i8086
|
12 lat temu |
|
cputarg.pas
|
eff0894a66
all the extra i8086 units added
|
12 lat temu |
|
hlcgcpu.pas
|
24fcac9f87
+ added support for nested procvars in the i8086 far data memory models
|
11 lat temu |
|
i8086att.inc
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
|
11 lat temu |
|
i8086atts.inc
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
|
11 lat temu |
|
i8086int.inc
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
|
11 lat temu |
|
i8086nop.inc
|
842e027a9f
+ prove of concept how FMA4 could be supported in inline assembler
|
11 lat temu |
|
i8086op.inc
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
|
11 lat temu |
|
i8086prop.inc
|
dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
|
11 lat temu |
|
i8086tab.inc
|
842e027a9f
+ prove of concept how FMA4 could be supported in inline assembler
|
11 lat temu |
|
n8086add.pas
|
4ea551a0f7
* is_farpointer and is_hugepointer moved from defutil to symcpu
|
11 lat temu |
|
n8086cal.pas
|
8a606761cd
* don't push cs in ti8086callnode.extra_interrupt_code in the far code memory
|
11 lat temu |
|
n8086cnv.pas
|
e8b9d9bf41
* converted tcgtypeconvnode.second_nil_to_methodprocvar to the high level code
|
11 lat temu |
|
n8086con.pas
|
338c064beb
* moved x86-specific tpointerdef functionality to architecture-specific
|
11 lat temu |
|
n8086inl.pas
|
4ea551a0f7
* is_farpointer and is_hugepointer moved from defutil to symcpu
|
11 lat temu |
|
n8086ld.pas
|
f4a0c08736
* fixed nested access to parent local variables in i8086 far data memory models
|
11 lat temu |
|
n8086mat.pas
|
dc432918da
+ enabled the use of the DIV/IDIV instruction for 16-bit div/mod on i8086
|
11 lat temu |
|
n8086mem.pas
|
3164bf66f5
+ implemented correct [] indexing of huge pointers
|
11 lat temu |
|
n8086tcon.pas
|
4ea551a0f7
* is_farpointer and is_hugepointer moved from defutil to symcpu
|
11 lat temu |
|
n8086util.pas
|
1910177cf0
+ added heapmax support to the $M directive on i8086-msdos. It is currently
|
11 lat temu |
|
r8086ari.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086att.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086con.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086dwrf.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086int.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086iri.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086nasm.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086nor.inc
|
107a6f6552
* i8086 versions of i386*.inc and r386*.inc renamed to i8086*.inc and r8086*.inc
|
12 lat temu |
|
r8086nri.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086num.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086ot.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086rni.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086sri.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
r8086stab.inc
|
107a6f6552
* i8086 versions of i386*.inc and r386*.inc renamed to i8086*.inc and r8086*.inc
|
12 lat temu |
|
r8086std.inc
|
5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
12 lat temu |
|
ra8086att.pas
|
a04cbc09b0
* changed the default i8086 asmmode to Intel
|
12 lat temu |
|
ra8086int.pas
|
a04cbc09b0
* changed the default i8086 asmmode to Intel
|
12 lat temu |
|
rgcpu.pas
|
c9f8703679
+ set ref.segment to NR_SS for all temps/localvars on i8086. This allows the
|
11 lat temu |
|
symcpu.pas
|
94bcb9878a
* reimplemented r28329 in a different way, as suggested by Jonas
|
11 lat temu |
|
tgcpu.pas
|
c9f8703679
+ set ref.segment to NR_SS for all temps/localvars on i8086. This allows the
|
11 lat temu |
nickysn
94bcb9878a
* reimplemented r28329 in a different way, as suggested by Jonas