cpugas.pas 13 KB

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  1. {
  2. Copyright (c) 1999-2009 by Florian Klaempfl and David Zhang
  3. This unit implements an asmoutput class for MIPS assembly syntax
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit cpugas;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. cpubase, aasmbase, globtype,
  22. aasmtai, aasmcpu, assemble, aggas;
  23. type
  24. TMIPSGNUAssembler = class(TGNUassembler)
  25. nomacro, noreorder, noat : boolean;
  26. constructor create(smart: boolean); override;
  27. {# Constructs the command line for calling the assembler }
  28. function MakeCmdLine: TCmdStr; override;
  29. end;
  30. TMIPSInstrWriter = class(TCPUInstrWriter)
  31. procedure WriteInstruction(hp : tai);override;
  32. end;
  33. const
  34. use_std_regnames : boolean =
  35. {$ifndef USE_MIPS_GAS_REGS}
  36. true;
  37. {$else}
  38. false;
  39. {$endif}
  40. implementation
  41. uses
  42. cutils, systems, cpuinfo,
  43. verbose, itcpugas, cgbase, cgutils;
  44. function gas_std_regname(r:Tregister):string;
  45. var
  46. hr: tregister;
  47. begin
  48. { Double uses the same table as single }
  49. hr := r;
  50. case getsubreg(hr) of
  51. R_SUBFD:
  52. setsubreg(hr, R_SUBFS);
  53. R_SUBL, R_SUBW, R_SUBD, R_SUBQ:
  54. setsubreg(hr, R_SUBD);
  55. end;
  56. result:=std_regname(hr);
  57. end;
  58. function asm_regname(reg : TRegister) : string;
  59. begin
  60. if use_std_regnames then
  61. asm_regname:='$'+gas_std_regname(reg)
  62. else
  63. asm_regname:=gas_regname(reg);
  64. end;
  65. {****************************************************************************}
  66. { GNU MIPS Assembler writer }
  67. {****************************************************************************}
  68. constructor TMIPSGNUAssembler.create(smart: boolean);
  69. begin
  70. inherited create(smart);
  71. InstrWriter := TMIPSInstrWriter.create(self);
  72. nomacro:=false;
  73. noreorder:=false;
  74. noat:=false;
  75. end;
  76. function TMIPSGNUAssembler.MakeCmdLine: TCmdStr;
  77. begin
  78. result := Inherited MakeCmdLine;
  79. { ABI selection }
  80. Replace(result,'$ABI','-mabi='+abitypestr[mips_abi]);
  81. { ARCH selection }
  82. Replace(result,'$ARCH','-march='+lower(cputypestr[mips_cpu]));
  83. end;
  84. {****************************************************************************}
  85. { Helper routines for Instruction Writer }
  86. {****************************************************************************}
  87. function GetReferenceString(var ref: TReference): string;
  88. var
  89. reg: TRegister;
  90. regstr: string;
  91. begin
  92. result:='';
  93. if assigned(ref.symbol) then
  94. result:=ref.symbol.name;
  95. if (ref.offset<0) then
  96. result:=result+tostr(ref.offset)
  97. else if (ref.offset>0) then
  98. begin
  99. if assigned(ref.symbol) then
  100. result:=result+'+';
  101. result:=result+tostr(ref.offset);
  102. end;
  103. { either base or index may be present, but not both }
  104. reg:=ref.base;
  105. if (reg=NR_NO) then
  106. reg:=ref.index
  107. else if (ref.index<>NR_NO) then
  108. InternalError(2013013001);
  109. if (reg=NR_NO) then
  110. regstr:=''
  111. else
  112. regstr:='('+asm_regname(reg)+')';
  113. case ref.refaddr of
  114. addr_no,
  115. addr_full:
  116. if assigned(ref.symbol) and (reg<>NR_NO) then
  117. InternalError(2013013002)
  118. else
  119. begin
  120. result:=result+regstr;
  121. exit;
  122. end;
  123. addr_pic:
  124. result:='%got('+result;
  125. addr_high:
  126. result:='%hi('+result;
  127. addr_low:
  128. result:='%lo('+result;
  129. addr_pic_call16:
  130. result:='%call16('+result;
  131. addr_low_pic:
  132. result:='%got_lo('+result;
  133. addr_high_pic:
  134. result:='%got_hi('+result;
  135. addr_low_call:
  136. result:='%call_lo('+result;
  137. addr_high_call:
  138. result:='%call_hi('+result;
  139. else
  140. InternalError(2013013003);
  141. end;
  142. result:=result+')'+regstr;
  143. end;
  144. function getopstr(const Oper: TOper): string;
  145. begin
  146. with Oper do
  147. case typ of
  148. top_reg:
  149. getopstr := asm_regname(reg);
  150. top_const:
  151. getopstr := tostr(longint(val));
  152. top_ref:
  153. getopstr := getreferencestring(ref^);
  154. else
  155. internalerror(10001);
  156. end;
  157. end;
  158. function getopstr_4(const Oper: TOper): string;
  159. var
  160. tmpref: treference;
  161. begin
  162. with Oper do
  163. case typ of
  164. top_ref:
  165. begin
  166. tmpref := ref^;
  167. Inc(tmpref.offset, 4);
  168. getopstr_4 := getreferencestring(tmpref);
  169. end;
  170. else
  171. internalerror(2007050403);
  172. end;
  173. end;
  174. {
  175. function getnextfpreg(tmpfpu : shortstring) : shortstring;
  176. begin
  177. case length(tmpfpu) of
  178. 3:
  179. if (tmpfpu[3] = '9') then
  180. tmpfpu:='$f10'
  181. else
  182. tmpfpu[3] := succ(tmpfpu[3]);
  183. 4:
  184. if (tmpfpu[4] = '9') then
  185. tmpfpu:='$f20'
  186. else
  187. tmpfpu[4] := succ(tmpfpu[4]);
  188. else
  189. internalerror(20120531);
  190. end;
  191. getnextfpreg := tmpfpu;
  192. end;
  193. }
  194. function is_macro_instruction(ai : taicpu) : boolean;
  195. var
  196. op: tasmop;
  197. begin
  198. op:=ai.opcode;
  199. is_macro_instruction :=
  200. { 'seq', 'sge', 'sgeu', 'sgt', 'sgtu', 'sle', 'sleu', 'sne', }
  201. (op=A_SEQ) or (op = A_SGE) or (op=A_SGEU) or (op=A_SGT) or
  202. (op=A_SGTU) or (op=A_SLE) or (op=A_SLEU) or (op=A_SNE)
  203. { JAL is not here! See comments in TCGMIPS.a_call_name. }
  204. or (op=A_LA) or ((op=A_BC) and not (ai.condition in [C_EQ,C_NE])) {or (op=A_JAL)}
  205. or (op=A_REM) or (op=A_REMU)
  206. or (op=A_DIV) or (op=A_DIVU)
  207. { A_LI is only a macro if the immediate is not in thez 16-bit range }
  208. or (op=A_LI);
  209. end;
  210. procedure TMIPSInstrWriter.WriteInstruction(hp: Tai);
  211. var
  212. Op: TAsmOp;
  213. s,s1: string;
  214. i: integer;
  215. tmpfpu: string;
  216. tmpfpu_len: longint;
  217. r: TRegister;
  218. begin
  219. if hp.typ <> ait_instruction then
  220. exit;
  221. op := taicpu(hp).opcode;
  222. case op of
  223. A_P_SET_NOMIPS16:
  224. begin
  225. s := #9 + '.set' + #9 + 'nomips16';
  226. owner.AsmWriteLn(s);
  227. end;
  228. A_P_MASK,
  229. A_P_FMASK:
  230. begin
  231. s := #9 + gas_op2str[op] + #9'0x' + hexstr(taicpu(hp).oper[0]^.val,8)+ ',' + getopstr(taicpu(hp).oper[1]^) ;
  232. owner.AsmWriteLn(s);
  233. end;
  234. A_P_SET_MACRO:
  235. begin
  236. s := #9 + '.set' + #9 + 'macro';
  237. owner.AsmWriteLn(s);
  238. TMIPSGNUAssembler(owner).nomacro:=false;
  239. end;
  240. A_P_SET_REORDER:
  241. begin
  242. s := #9 + '.set' + #9 + 'reorder';
  243. owner.AsmWriteLn(s);
  244. TMIPSGNUAssembler(owner).noreorder:=false;
  245. end;
  246. A_P_SET_NOMACRO:
  247. begin
  248. s := #9 + '.set' + #9 + 'nomacro';
  249. owner.AsmWriteLn(s);
  250. TMIPSGNUAssembler(owner).nomacro:=true;
  251. end;
  252. A_P_SET_NOREORDER:
  253. begin
  254. s := #9 + '.set' + #9 + 'noreorder';
  255. owner.AsmWriteLn(s);
  256. TMIPSGNUAssembler(owner).noreorder:=true;
  257. end;
  258. A_P_SW:
  259. begin
  260. s := #9 + gas_op2str[A_SW] + #9 + getopstr(taicpu(hp).oper[0]^)+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  261. owner.AsmWriteLn(s);
  262. end;
  263. A_P_LW:
  264. begin
  265. s := #9 + gas_op2str[A_LW] + #9 + getopstr(taicpu(hp).oper[0]^)+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  266. owner.AsmWriteLn(s);
  267. end;
  268. A_LDC1:
  269. begin
  270. if (target_info.endian = endian_big) then
  271. begin
  272. s := #9 + gas_op2str[A_LDC1] + #9 + getopstr(taicpu(hp).oper[0]^)
  273. + ',' + getopstr(taicpu(hp).oper[1]^);
  274. end
  275. else
  276. begin
  277. tmpfpu := getopstr(taicpu(hp).oper[0]^);
  278. s := #9 + gas_op2str[A_LWC1] + #9 + tmpfpu + ',' + getopstr(taicpu(hp).oper[1]^); // + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  279. owner.AsmWriteLn(s);
  280. { bug if $f9/$f19
  281. tmpfpu_len := length(tmpfpu);
  282. tmpfpu[tmpfpu_len] := succ(tmpfpu[tmpfpu_len]);
  283. }
  284. r := taicpu(hp).oper[0]^.reg;
  285. setsupreg(r, getsupreg(r) + 1);
  286. tmpfpu := asm_regname(r);
  287. s := #9 + gas_op2str[A_LWC1] + #9 + tmpfpu + ',' + getopstr_4(taicpu(hp).oper[1]^); // + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  288. end;
  289. owner.AsmWriteLn(s);
  290. end;
  291. A_SDC1:
  292. begin
  293. if (target_info.endian = endian_big) then
  294. begin
  295. s := #9 + gas_op2str[A_SDC1] + #9 + getopstr(taicpu(hp).oper[0]^)
  296. + ',' + getopstr(taicpu(hp).oper[1]^);
  297. end
  298. else
  299. begin
  300. tmpfpu := getopstr(taicpu(hp).oper[0]^);
  301. s := #9 + gas_op2str[A_SWC1] + #9 + tmpfpu + ',' + getopstr(taicpu(hp).oper[1]^); //+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  302. owner.AsmWriteLn(s);
  303. {
  304. tmpfpu_len := length(tmpfpu);
  305. tmpfpu[tmpfpu_len] := succ(tmpfpu[tmpfpu_len]);
  306. }
  307. r := taicpu(hp).oper[0]^.reg;
  308. setsupreg(r, getsupreg(r) + 1);
  309. tmpfpu := asm_regname(r);
  310. s := #9 + gas_op2str[A_SWC1] + #9 + tmpfpu + ',' + getopstr_4(taicpu(hp).oper[1]^); //+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
  311. end;
  312. owner.AsmWriteLn(s);
  313. end;
  314. else
  315. begin
  316. if is_macro_instruction(taicpu(hp)) and TMIPSGNUAssembler(owner).nomacro then
  317. owner.AsmWriteln(#9'.set'#9'macro');
  318. s := #9 + gas_op2str[op] + cond2str[taicpu(hp).condition];
  319. if taicpu(hp).delayslot_annulled then
  320. s := s + ',a';
  321. if taicpu(hp).ops > 0 then
  322. begin
  323. s := s + #9 + getopstr(taicpu(hp).oper[0]^);
  324. for i := 1 to taicpu(hp).ops - 1 do
  325. s := s + ',' + getopstr(taicpu(hp).oper[i]^);
  326. end;
  327. owner.AsmWriteLn(s);
  328. if is_macro_instruction(taicpu(hp)) and TMIPSGNUAssembler(owner).nomacro then
  329. owner.AsmWriteln(#9'.set'#9'nomacro');
  330. end;
  331. end;
  332. end;
  333. const
  334. as_MIPSEL_as_info: tasminfo =
  335. (
  336. id: as_gas;
  337. idtxt: 'AS';
  338. asmbin: 'as';
  339. asmcmd: '$ABI $ARCH $NOWARN -EL $PIC -o $OBJ $ASM';
  340. supported_targets: [system_mipsel_linux];
  341. flags: [ af_needar, af_smartlink_sections];
  342. labelprefix: '.L';
  343. comment: '# ';
  344. dollarsign: '$';
  345. );
  346. as_MIPSEB_as_info: tasminfo =
  347. (
  348. id: as_gas;
  349. idtxt: 'AS';
  350. asmbin: 'as';
  351. asmcmd: '$ABI $ARCH $NOWARN -EB $PIC -o $OBJ $ASM';
  352. supported_targets: [system_mipseb_linux];
  353. flags: [ af_needar, af_smartlink_sections];
  354. labelprefix: '.L';
  355. comment: '# ';
  356. dollarsign: '$';
  357. );
  358. begin
  359. {$ifdef MIPSEL}
  360. RegisterAssembler(as_MIPSEL_as_info, TMIPSGNUAssembler);
  361. {$else MIPSEL}
  362. RegisterAssembler(as_MIPSEB_as_info, TMIPSGNUAssembler);
  363. {$endif MIPSEL}
  364. end.