aasmcpu.pas 72 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  4. Contains the abstract assembler implementation for the i386
  5. * Portions of this code was inspired by the NASM sources
  6. The Netwide Assembler is Copyright (c) 1996 Simon Tatham and
  7. Julian Hall. All rights reserved.
  8. This program is free software; you can redistribute it and/or modify
  9. it under the terms of the GNU General Public License as published by
  10. the Free Software Foundation; either version 2 of the License, or
  11. (at your option) any later version.
  12. This program is distributed in the hope that it will be useful,
  13. but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. GNU General Public License for more details.
  16. You should have received a copy of the GNU General Public License
  17. along with this program; if not, write to the Free Software
  18. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. ****************************************************************************
  20. }
  21. unit aasmcpu;
  22. {$i fpcdefs.inc}
  23. interface
  24. uses
  25. cclasses,globals,verbose,
  26. cpuinfo,cpubase,
  27. cgbase,
  28. symtype,symsym,
  29. aasmbase,aasmtai;
  30. const
  31. { "mov reg,reg" source operand number }
  32. O_MOV_SOURCE = 0;
  33. { "mov reg,reg" destination operand number }
  34. O_MOV_DEST = 1;
  35. { Operand types }
  36. OT_NONE = $00000000;
  37. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  38. OT_BITS16 = $00000002;
  39. OT_BITS32 = $00000004;
  40. OT_BITS64 = $00000008; { FPU only }
  41. OT_BITS80 = $00000010;
  42. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  43. OT_NEAR = $00000040;
  44. OT_SHORT = $00000080;
  45. OT_SIZE_MASK = $000000FF; { all the size attributes }
  46. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  47. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  48. OT_TO = $00000200; { operand is followed by a colon }
  49. { reverse effect in FADD, FSUB &c }
  50. OT_COLON = $00000400;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_IMM8 = $00002001;
  54. OT_IMM16 = $00002002;
  55. OT_IMM32 = $00002004;
  56. OT_IMM64 = $00002008;
  57. OT_IMM80 = $00002010;
  58. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  59. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  60. OT_REG8 = $00201001;
  61. OT_REG16 = $00201002;
  62. OT_REG32 = $00201004;
  63. OT_REG64 = $00201008;
  64. OT_MMXREG = $00201008; { MMX registers }
  65. OT_XMMREG = $00201010; { Katmai registers }
  66. OT_MEMORY = $00204000; { register number in 'basereg' }
  67. OT_MEM8 = $00204001;
  68. OT_MEM16 = $00204002;
  69. OT_MEM32 = $00204004;
  70. OT_MEM64 = $00204008;
  71. OT_MEM80 = $00204010;
  72. OT_FPUREG = $01000000; { floating point stack registers }
  73. OT_FPU0 = $01000800; { FPU stack register zero }
  74. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  75. { a mask for the following }
  76. OT_REG_ACCUM = $00211000; { FUNCTION_RETURN_REG: AL, AX or EAX }
  77. OT_REG_AL = $00211001; { REG_ACCUM | BITSxx }
  78. OT_REG_AX = $00211002; { ditto }
  79. OT_REG_EAX = $00211004; { and again }
  80. {$ifdef x86_64}
  81. OT_REG_RAX = $00211008;
  82. {$endif x86_64}
  83. OT_REG_COUNT = $00221000; { counter: CL, CX or ECX }
  84. OT_REG_CL = $00221001; { REG_COUNT | BITSxx }
  85. OT_REG_CX = $00221002; { ditto }
  86. OT_REG_ECX = $00221004; { another one }
  87. {$ifdef x86_64}
  88. OT_REG_RCX = $00221008;
  89. {$endif x86_64}
  90. OT_REG_DX = $00241002;
  91. OT_REG_EDX = $00241004;
  92. OT_REG_SREG = $00081002; { any segment register }
  93. OT_REG_CS = $01081002; { CS }
  94. OT_REG_DESS = $02081002; { DS, ES, SS (non-CS 86 registers) }
  95. OT_REG_FSGS = $04081002; { FS, GS (386 extended registers) }
  96. OT_REG_CDT = $00101004; { CRn, DRn and TRn }
  97. OT_REG_CREG = $08101004; { CRn }
  98. OT_REG_CR4 = $08101404; { CR4 (Pentium only) }
  99. OT_REG_DREG = $10101004; { DRn }
  100. OT_REG_TREG = $20101004; { TRn }
  101. OT_MEM_OFFS = $00604000; { special type of EA }
  102. { simple [address] offset }
  103. OT_ONENESS = $00800000; { special type of immediate operand }
  104. { so UNITY == IMMEDIATE | ONENESS }
  105. OT_UNITY = $00802000; { for shift/rotate instructions }
  106. { Size of the instruction table converted by nasmconv.pas }
  107. {$ifdef x86_64}
  108. instabentries = {$i x8664nop.inc}
  109. {$else x86_64}
  110. instabentries = {$i i386nop.inc}
  111. {$endif x86_64}
  112. maxinfolen = 8;
  113. type
  114. TOperandOrder = (op_intel,op_att);
  115. tinsentry=packed record
  116. opcode : tasmop;
  117. ops : byte;
  118. optypes : array[0..2] of longint;
  119. code : array[0..maxinfolen] of char;
  120. flags : longint;
  121. end;
  122. pinsentry=^tinsentry;
  123. { alignment for operator }
  124. tai_align = class(tai_align_abstract)
  125. reg : tregister;
  126. constructor create(b:byte);
  127. constructor create_op(b: byte; _op: byte);
  128. function calculatefillbuf(var buf : tfillbuffer):pchar;override;
  129. end;
  130. taicpu = class(taicpu_abstract)
  131. opsize : topsize;
  132. constructor op_none(op : tasmop);
  133. constructor op_none(op : tasmop;_size : topsize);
  134. constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  135. constructor op_const(op : tasmop;_size : topsize;_op1 : aword);
  136. constructor op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  137. constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  138. constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  139. constructor op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aword);
  140. constructor op_const_reg(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister);
  141. constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aword);
  142. constructor op_const_ref(op : tasmop;_size : topsize;_op1 : aword;const _op2 : treference);
  143. constructor op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  144. constructor op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  145. constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister;_op3 : tregister);
  146. constructor op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aword;const _op2 : treference;_op3 : tregister);
  147. constructor op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister; const _op3 : treference);
  148. constructor op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister;const _op3 : treference);
  149. { this is for Jmp instructions }
  150. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  151. constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  152. constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  153. constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  154. constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  155. procedure changeopsize(siz:topsize);
  156. function GetString:string;
  157. procedure CheckNonCommutativeOpcodes;
  158. private
  159. FOperandOrder : TOperandOrder;
  160. procedure init(_size : topsize); { this need to be called by all constructor }
  161. {$ifndef NOAG386BIN}
  162. public
  163. { the next will reset all instructions that can change in pass 2 }
  164. procedure ResetPass1;
  165. procedure ResetPass2;
  166. function CheckIfValid:boolean;
  167. function Pass1(offset:longint):longint;virtual;
  168. procedure Pass2(sec:TAsmObjectdata);virtual;
  169. procedure SetOperandOrder(order:TOperandOrder);
  170. function is_same_reg_move(regtype: Tregistertype):boolean;override;
  171. protected
  172. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  173. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  174. procedure ppubuildderefimploper(var o:toper);override;
  175. procedure ppuderefoper(var o:toper);override;
  176. private
  177. { next fields are filled in pass1, so pass2 is faster }
  178. inssize : shortint;
  179. insoffset : longint;
  180. LastInsOffset : longint; { need to be public to be reset }
  181. insentry : PInsEntry;
  182. function InsEnd:longint;
  183. procedure create_ot;
  184. function Matches(p:PInsEntry):longint;
  185. function calcsize(p:PInsEntry):longint;
  186. procedure gencode(sec:TAsmObjectData);
  187. function NeedAddrPrefix(opidx:byte):boolean;
  188. procedure Swapoperands;
  189. function FindInsentry:boolean;
  190. {$endif NOAG386BIN}
  191. end;
  192. procedure InitAsm;
  193. procedure DoneAsm;
  194. implementation
  195. uses
  196. cutils,
  197. itcpugas;
  198. {*****************************************************************************
  199. Instruction table
  200. *****************************************************************************}
  201. const
  202. {Instruction flags }
  203. IF_NONE = $00000000;
  204. IF_SM = $00000001; { size match first two operands }
  205. IF_SM2 = $00000002;
  206. IF_SB = $00000004; { unsized operands can't be non-byte }
  207. IF_SW = $00000008; { unsized operands can't be non-word }
  208. IF_SD = $00000010; { unsized operands can't be nondword }
  209. IF_AR0 = $00000020; { SB, SW, SD applies to argument 0 }
  210. IF_AR1 = $00000040; { SB, SW, SD applies to argument 1 }
  211. IF_AR2 = $00000060; { SB, SW, SD applies to argument 2 }
  212. IF_ARMASK = $00000060; { mask for unsized argument spec }
  213. IF_PRIV = $00000100; { it's a privileged instruction }
  214. IF_SMM = $00000200; { it's only valid in SMM }
  215. IF_PROT = $00000400; { it's protected mode only }
  216. IF_NOX86_64 = $00000800; { removed instruction in x86_64 }
  217. IF_UNDOC = $00001000; { it's an undocumented instruction }
  218. IF_FPU = $00002000; { it's an FPU instruction }
  219. IF_MMX = $00004000; { it's an MMX instruction }
  220. { it's a 3DNow! instruction }
  221. IF_3DNOW = $00008000;
  222. { it's a SSE (KNI, MMX2) instruction }
  223. IF_SSE = $00010000;
  224. { SSE2 instructions }
  225. IF_SSE2 = $00020000;
  226. { SSE3 instructions }
  227. IF_SSE3 = $00040000;
  228. { SSE64 instructions }
  229. IF_SSE64 = $00080000;
  230. { the mask for processor types }
  231. {IF_PMASK = longint($FF000000);}
  232. { the mask for disassembly "prefer" }
  233. {IF_PFMASK = longint($F001FF00);}
  234. IF_8086 = $00000000; { 8086 instruction }
  235. IF_186 = $01000000; { 186+ instruction }
  236. IF_286 = $02000000; { 286+ instruction }
  237. IF_386 = $03000000; { 386+ instruction }
  238. IF_486 = $04000000; { 486+ instruction }
  239. IF_PENT = $05000000; { Pentium instruction }
  240. IF_P6 = $06000000; { P6 instruction }
  241. IF_KATMAI = $07000000; { Katmai instructions }
  242. { Willamette instructions }
  243. IF_WILLAMETTE = $08000000;
  244. { Prescott instructions }
  245. IF_PRESCOTT = $09000000;
  246. IF_X86_64 = $0a000000;
  247. IF_CYRIX = $10000000; { Cyrix-specific instruction }
  248. IF_AMD = $20000000; { AMD-specific instruction }
  249. { added flags }
  250. IF_PRE = $40000000; { it's a prefix instruction }
  251. IF_PASS2 = longint($80000000); { if the instruction can change in a second pass }
  252. type
  253. TInsTabCache=array[TasmOp] of longint;
  254. PInsTabCache=^TInsTabCache;
  255. const
  256. {$ifdef x86_64}
  257. InsTab:array[0..instabentries-1] of TInsEntry={$i x8664tab.inc}
  258. {$else x86_64}
  259. InsTab:array[0..instabentries-1] of TInsEntry={$i i386tab.inc}
  260. {$endif x86_64}
  261. var
  262. InsTabCache : PInsTabCache;
  263. const
  264. {$ifdef x86_64}
  265. { Intel style operands ! }
  266. opsize_2_type:array[0..2,topsize] of longint=(
  267. (OT_NONE,
  268. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
  269. OT_BITS16,OT_BITS32,OT_BITS64,
  270. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  271. OT_BITS64,
  272. OT_NEAR,OT_FAR,OT_SHORT
  273. ),
  274. (OT_NONE,
  275. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,OT_BITS8,OT_BITS16,OT_BITS32,
  276. OT_BITS16,OT_BITS32,OT_BITS64,
  277. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  278. OT_BITS64,
  279. OT_NEAR,OT_FAR,OT_SHORT
  280. ),
  281. (OT_NONE,
  282. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,
  283. OT_BITS16,OT_BITS32,OT_BITS64,
  284. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  285. OT_BITS64,
  286. OT_NEAR,OT_FAR,OT_SHORT
  287. )
  288. );
  289. reg_ot_table : array[tregisterindex] of longint = (
  290. {$i r8664ot.inc}
  291. );
  292. {$else x86_64}
  293. { Intel style operands ! }
  294. opsize_2_type:array[0..2,topsize] of longint=(
  295. (OT_NONE,
  296. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  297. OT_BITS16,OT_BITS32,OT_BITS64,
  298. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  299. OT_BITS64,
  300. OT_NEAR,OT_FAR,OT_SHORT
  301. ),
  302. (OT_NONE,
  303. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  304. OT_BITS16,OT_BITS32,OT_BITS64,
  305. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  306. OT_BITS64,
  307. OT_NEAR,OT_FAR,OT_SHORT
  308. ),
  309. (OT_NONE,
  310. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  311. OT_BITS16,OT_BITS32,OT_BITS64,
  312. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  313. OT_BITS64,
  314. OT_NEAR,OT_FAR,OT_SHORT
  315. )
  316. );
  317. reg_ot_table : array[tregisterindex] of longint = (
  318. {$i r386ot.inc}
  319. );
  320. {$endif x86_64}
  321. {****************************************************************************
  322. TAI_ALIGN
  323. ****************************************************************************}
  324. constructor tai_align.create(b: byte);
  325. begin
  326. inherited create(b);
  327. reg:=NR_ECX;
  328. end;
  329. constructor tai_align.create_op(b: byte; _op: byte);
  330. begin
  331. inherited create_op(b,_op);
  332. reg:=NR_NO;
  333. end;
  334. function tai_align.calculatefillbuf(var buf : tfillbuffer):pchar;
  335. const
  336. alignarray:array[0..5] of string[8]=(
  337. #$8D#$B4#$26#$00#$00#$00#$00,
  338. #$8D#$B6#$00#$00#$00#$00,
  339. #$8D#$74#$26#$00,
  340. #$8D#$76#$00,
  341. #$89#$F6,
  342. #$90
  343. );
  344. var
  345. bufptr : pchar;
  346. j : longint;
  347. begin
  348. inherited calculatefillbuf(buf);
  349. if not use_op then
  350. begin
  351. bufptr:=pchar(@buf);
  352. while (fillsize>0) do
  353. begin
  354. for j:=0 to 5 do
  355. if (fillsize>=length(alignarray[j])) then
  356. break;
  357. move(alignarray[j][1],bufptr^,length(alignarray[j]));
  358. inc(bufptr,length(alignarray[j]));
  359. dec(fillsize,length(alignarray[j]));
  360. end;
  361. end;
  362. calculatefillbuf:=pchar(@buf);
  363. end;
  364. {*****************************************************************************
  365. Taicpu Constructors
  366. *****************************************************************************}
  367. procedure taicpu.changeopsize(siz:topsize);
  368. begin
  369. opsize:=siz;
  370. end;
  371. procedure taicpu.init(_size : topsize);
  372. begin
  373. { default order is att }
  374. FOperandOrder:=op_att;
  375. segprefix:=NR_NO;
  376. opsize:=_size;
  377. {$ifndef NOAG386BIN}
  378. insentry:=nil;
  379. LastInsOffset:=-1;
  380. InsOffset:=0;
  381. InsSize:=0;
  382. {$endif}
  383. end;
  384. constructor taicpu.op_none(op : tasmop);
  385. begin
  386. inherited create(op);
  387. init(S_NO);
  388. end;
  389. constructor taicpu.op_none(op : tasmop;_size : topsize);
  390. begin
  391. inherited create(op);
  392. init(_size);
  393. end;
  394. constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  395. begin
  396. inherited create(op);
  397. init(_size);
  398. ops:=1;
  399. loadreg(0,_op1);
  400. end;
  401. constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : aword);
  402. begin
  403. inherited create(op);
  404. init(_size);
  405. ops:=1;
  406. loadconst(0,_op1);
  407. end;
  408. constructor taicpu.op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  409. begin
  410. inherited create(op);
  411. init(_size);
  412. ops:=1;
  413. loadref(0,_op1);
  414. end;
  415. constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  416. begin
  417. inherited create(op);
  418. init(_size);
  419. ops:=2;
  420. loadreg(0,_op1);
  421. loadreg(1,_op2);
  422. end;
  423. constructor taicpu.op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aword);
  424. begin
  425. inherited create(op);
  426. init(_size);
  427. ops:=2;
  428. loadreg(0,_op1);
  429. loadconst(1,_op2);
  430. end;
  431. constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  432. begin
  433. inherited create(op);
  434. init(_size);
  435. ops:=2;
  436. loadreg(0,_op1);
  437. loadref(1,_op2);
  438. end;
  439. constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister);
  440. begin
  441. inherited create(op);
  442. init(_size);
  443. ops:=2;
  444. loadconst(0,_op1);
  445. loadreg(1,_op2);
  446. end;
  447. constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aword);
  448. begin
  449. inherited create(op);
  450. init(_size);
  451. ops:=2;
  452. loadconst(0,_op1);
  453. loadconst(1,_op2);
  454. end;
  455. constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : aword;const _op2 : treference);
  456. begin
  457. inherited create(op);
  458. init(_size);
  459. ops:=2;
  460. loadconst(0,_op1);
  461. loadref(1,_op2);
  462. end;
  463. constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  464. begin
  465. inherited create(op);
  466. init(_size);
  467. ops:=2;
  468. loadref(0,_op1);
  469. loadreg(1,_op2);
  470. end;
  471. constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  472. begin
  473. inherited create(op);
  474. init(_size);
  475. ops:=3;
  476. loadreg(0,_op1);
  477. loadreg(1,_op2);
  478. loadreg(2,_op3);
  479. end;
  480. constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister;_op3 : tregister);
  481. begin
  482. inherited create(op);
  483. init(_size);
  484. ops:=3;
  485. loadconst(0,_op1);
  486. loadreg(1,_op2);
  487. loadreg(2,_op3);
  488. end;
  489. constructor taicpu.op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  490. begin
  491. inherited create(op);
  492. init(_size);
  493. ops:=3;
  494. loadreg(0,_op1);
  495. loadreg(1,_op2);
  496. loadref(2,_op3);
  497. end;
  498. constructor taicpu.op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aword;const _op2 : treference;_op3 : tregister);
  499. begin
  500. inherited create(op);
  501. init(_size);
  502. ops:=3;
  503. loadconst(0,_op1);
  504. loadref(1,_op2);
  505. loadreg(2,_op3);
  506. end;
  507. constructor taicpu.op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aword;_op2 : tregister;const _op3 : treference);
  508. begin
  509. inherited create(op);
  510. init(_size);
  511. ops:=3;
  512. loadconst(0,_op1);
  513. loadreg(1,_op2);
  514. loadref(2,_op3);
  515. end;
  516. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  517. begin
  518. inherited create(op);
  519. init(_size);
  520. condition:=cond;
  521. ops:=1;
  522. loadsymbol(0,_op1,0);
  523. end;
  524. constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  525. begin
  526. inherited create(op);
  527. init(_size);
  528. ops:=1;
  529. loadsymbol(0,_op1,0);
  530. end;
  531. constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  532. begin
  533. inherited create(op);
  534. init(_size);
  535. ops:=1;
  536. loadsymbol(0,_op1,_op1ofs);
  537. end;
  538. constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  539. begin
  540. inherited create(op);
  541. init(_size);
  542. ops:=2;
  543. loadsymbol(0,_op1,_op1ofs);
  544. loadreg(1,_op2);
  545. end;
  546. constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  547. begin
  548. inherited create(op);
  549. init(_size);
  550. ops:=2;
  551. loadsymbol(0,_op1,_op1ofs);
  552. loadref(1,_op2);
  553. end;
  554. function taicpu.GetString:string;
  555. var
  556. i : longint;
  557. s : string;
  558. addsize : boolean;
  559. begin
  560. s:='['+std_op2str[opcode];
  561. for i:=0 to ops-1 do
  562. begin
  563. with oper[i]^ do
  564. begin
  565. if i=0 then
  566. s:=s+' '
  567. else
  568. s:=s+',';
  569. { type }
  570. addsize:=false;
  571. if (ot and OT_XMMREG)=OT_XMMREG then
  572. s:=s+'xmmreg'
  573. else
  574. if (ot and OT_MMXREG)=OT_MMXREG then
  575. s:=s+'mmxreg'
  576. else
  577. if (ot and OT_FPUREG)=OT_FPUREG then
  578. s:=s+'fpureg'
  579. else
  580. if (ot and OT_REGISTER)=OT_REGISTER then
  581. begin
  582. s:=s+'reg';
  583. addsize:=true;
  584. end
  585. else
  586. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  587. begin
  588. s:=s+'imm';
  589. addsize:=true;
  590. end
  591. else
  592. if (ot and OT_MEMORY)=OT_MEMORY then
  593. begin
  594. s:=s+'mem';
  595. addsize:=true;
  596. end
  597. else
  598. s:=s+'???';
  599. { size }
  600. if addsize then
  601. begin
  602. if (ot and OT_BITS8)<>0 then
  603. s:=s+'8'
  604. else
  605. if (ot and OT_BITS16)<>0 then
  606. s:=s+'16'
  607. else
  608. if (ot and OT_BITS32)<>0 then
  609. s:=s+'32'
  610. else
  611. s:=s+'??';
  612. { signed }
  613. if (ot and OT_SIGNED)<>0 then
  614. s:=s+'s';
  615. end;
  616. end;
  617. end;
  618. GetString:=s+']';
  619. end;
  620. procedure taicpu.Swapoperands;
  621. var
  622. p : POper;
  623. begin
  624. { Fix the operands which are in AT&T style and we need them in Intel style }
  625. case ops of
  626. 2 : begin
  627. { 0,1 -> 1,0 }
  628. p:=oper[0];
  629. oper[0]:=oper[1];
  630. oper[1]:=p;
  631. end;
  632. 3 : begin
  633. { 0,1,2 -> 2,1,0 }
  634. p:=oper[0];
  635. oper[0]:=oper[2];
  636. oper[2]:=p;
  637. end;
  638. end;
  639. end;
  640. procedure taicpu.SetOperandOrder(order:TOperandOrder);
  641. begin
  642. if FOperandOrder<>order then
  643. begin
  644. Swapoperands;
  645. FOperandOrder:=order;
  646. end;
  647. end;
  648. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  649. begin
  650. o.typ:=toptype(ppufile.getbyte);
  651. o.ot:=ppufile.getlongint;
  652. case o.typ of
  653. top_reg :
  654. ppufile.getdata(o.reg,sizeof(Tregister));
  655. top_ref :
  656. begin
  657. new(o.ref);
  658. ppufile.getdata(o.ref^.segment,sizeof(Tregister));
  659. ppufile.getdata(o.ref^.base,sizeof(Tregister));
  660. ppufile.getdata(o.ref^.index,sizeof(Tregister));
  661. o.ref^.scalefactor:=ppufile.getbyte;
  662. o.ref^.offset:=ppufile.getaint;
  663. o.ref^.symbol:=ppufile.getasmsymbol;
  664. o.ref^.relsymbol:=ppufile.getasmsymbol;
  665. end;
  666. top_const :
  667. o.val:=aword(ppufile.getaint);
  668. top_local :
  669. begin
  670. with o.localoper^ do
  671. begin
  672. ppufile.getderef(localsymderef);
  673. localsymofs:=ppufile.getaint;
  674. localindexreg:=tregister(ppufile.getlongint);
  675. localscale:=ppufile.getbyte;
  676. localgetoffset:=(ppufile.getbyte<>0);
  677. end;
  678. end;
  679. end;
  680. end;
  681. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  682. begin
  683. ppufile.putbyte(byte(o.typ));
  684. ppufile.putlongint(o.ot);
  685. case o.typ of
  686. top_reg :
  687. ppufile.putdata(o.reg,sizeof(Tregister));
  688. top_ref :
  689. begin
  690. ppufile.putdata(o.ref^.segment,sizeof(Tregister));
  691. ppufile.putdata(o.ref^.base,sizeof(Tregister));
  692. ppufile.putdata(o.ref^.index,sizeof(Tregister));
  693. ppufile.putbyte(o.ref^.scalefactor);
  694. ppufile.putaint(o.ref^.offset);
  695. ppufile.putasmsymbol(o.ref^.symbol);
  696. ppufile.putasmsymbol(o.ref^.relsymbol);
  697. end;
  698. top_const :
  699. ppufile.putaint(aint(o.val));
  700. top_local :
  701. begin
  702. with o.localoper^ do
  703. begin
  704. ppufile.putderef(localsymderef);
  705. ppufile.putaint(aint(localsymofs));
  706. ppufile.putlongint(longint(localindexreg));
  707. ppufile.putbyte(localscale);
  708. ppufile.putbyte(byte(localgetoffset));
  709. end;
  710. end;
  711. end;
  712. end;
  713. procedure taicpu.ppubuildderefimploper(var o:toper);
  714. begin
  715. case o.typ of
  716. top_local :
  717. o.localoper^.localsymderef.build(tvarsym(o.localoper^.localsym));
  718. end;
  719. end;
  720. procedure taicpu.ppuderefoper(var o:toper);
  721. begin
  722. case o.typ of
  723. top_ref :
  724. begin
  725. if assigned(o.ref^.symbol) then
  726. objectlibrary.derefasmsymbol(o.ref^.symbol);
  727. if assigned(o.ref^.relsymbol) then
  728. objectlibrary.derefasmsymbol(o.ref^.relsymbol);
  729. end;
  730. top_local :
  731. o.localoper^.localsym:=tvarsym(o.localoper^.localsymderef.resolve);
  732. end;
  733. end;
  734. procedure taicpu.CheckNonCommutativeOpcodes;
  735. begin
  736. { we need ATT order }
  737. SetOperandOrder(op_att);
  738. if (
  739. (ops=2) and
  740. (oper[0]^.typ=top_reg) and
  741. (oper[1]^.typ=top_reg) and
  742. { if the first is ST and the second is also a register
  743. it is necessarily ST1 .. ST7 }
  744. ((oper[0]^.reg=NR_ST) or
  745. (oper[0]^.reg=NR_ST0))
  746. ) or
  747. { ((ops=1) and
  748. (oper[0]^.typ=top_reg) and
  749. (oper[0]^.reg in [R_ST1..R_ST7])) or}
  750. (ops=0) then
  751. begin
  752. if opcode=A_FSUBR then
  753. opcode:=A_FSUB
  754. else if opcode=A_FSUB then
  755. opcode:=A_FSUBR
  756. else if opcode=A_FDIVR then
  757. opcode:=A_FDIV
  758. else if opcode=A_FDIV then
  759. opcode:=A_FDIVR
  760. else if opcode=A_FSUBRP then
  761. opcode:=A_FSUBP
  762. else if opcode=A_FSUBP then
  763. opcode:=A_FSUBRP
  764. else if opcode=A_FDIVRP then
  765. opcode:=A_FDIVP
  766. else if opcode=A_FDIVP then
  767. opcode:=A_FDIVRP;
  768. end;
  769. if (
  770. (ops=1) and
  771. (oper[0]^.typ=top_reg) and
  772. (getregtype(oper[0]^.reg)=R_FPUREGISTER) and
  773. (oper[0]^.reg<>NR_ST)
  774. ) then
  775. begin
  776. if opcode=A_FSUBRP then
  777. opcode:=A_FSUBP
  778. else if opcode=A_FSUBP then
  779. opcode:=A_FSUBRP
  780. else if opcode=A_FDIVRP then
  781. opcode:=A_FDIVP
  782. else if opcode=A_FDIVP then
  783. opcode:=A_FDIVRP;
  784. end;
  785. end;
  786. {*****************************************************************************
  787. Assembler
  788. *****************************************************************************}
  789. {$ifndef NOAG386BIN}
  790. type
  791. ea=packed record
  792. sib_present : boolean;
  793. bytes : byte;
  794. size : byte;
  795. modrm : byte;
  796. sib : byte;
  797. end;
  798. procedure taicpu.create_ot;
  799. {
  800. this function will also fix some other fields which only needs to be once
  801. }
  802. var
  803. i,l,relsize : longint;
  804. begin
  805. if ops=0 then
  806. exit;
  807. { update oper[].ot field }
  808. for i:=0 to ops-1 do
  809. with oper[i]^ do
  810. begin
  811. case typ of
  812. top_reg :
  813. begin
  814. ot:=reg_ot_table[findreg_by_number(reg)];
  815. end;
  816. top_ref :
  817. begin
  818. if ref^.refaddr=addr_no then
  819. begin
  820. { create ot field }
  821. if (ot and OT_SIZE_MASK)=0 then
  822. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  823. else
  824. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  825. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  826. ot:=ot or OT_MEM_OFFS;
  827. { fix scalefactor }
  828. if (ref^.index=NR_NO) then
  829. ref^.scalefactor:=0
  830. else
  831. if (ref^.scalefactor=0) then
  832. ref^.scalefactor:=1;
  833. end
  834. else
  835. begin
  836. l:=ref^.offset;
  837. if assigned(ref^.symbol) then
  838. inc(l,ref^.symbol.address);
  839. { when it is a forward jump we need to compensate the
  840. offset of the instruction since the previous time,
  841. because the symbol address is then still using the
  842. 'old-style' addressing.
  843. For backwards jumps this is not required because the
  844. address of the symbol is already adjusted to the
  845. new offset }
  846. if (l>InsOffset) and (LastInsOffset<>-1) then
  847. inc(l,InsOffset-LastInsOffset);
  848. { instruction size will then always become 2 (PFV) }
  849. relsize:=(InsOffset+2)-l;
  850. if (not assigned(ref^.symbol) or
  851. ((ref^.symbol.currbind<>AB_EXTERNAL) and (ref^.symbol.address<>0))) and
  852. (relsize>=-128) and (relsize<=127) then
  853. ot:=OT_IMM32 or OT_SHORT
  854. else
  855. ot:=OT_IMM32 or OT_NEAR;
  856. end;
  857. end;
  858. top_local :
  859. begin
  860. if (ot and OT_SIZE_MASK)=0 then
  861. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  862. else
  863. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  864. end;
  865. top_const :
  866. begin
  867. if (opsize<>S_W) and (longint(val)>=-128) and (val<=127) then
  868. ot:=OT_IMM8 or OT_SIGNED
  869. else
  870. ot:=OT_IMMEDIATE or opsize_2_type[i,opsize];
  871. end;
  872. top_none :
  873. begin
  874. { generated when there was an error in the
  875. assembler reader. It never happends when generating
  876. assembler }
  877. end;
  878. else
  879. internalerror(200402261);
  880. end;
  881. end;
  882. end;
  883. function taicpu.InsEnd:longint;
  884. begin
  885. InsEnd:=InsOffset+InsSize;
  886. end;
  887. function taicpu.Matches(p:PInsEntry):longint;
  888. { * IF_SM stands for Size Match: any operand whose size is not
  889. * explicitly specified by the template is `really' intended to be
  890. * the same size as the first size-specified operand.
  891. * Non-specification is tolerated in the input instruction, but
  892. * _wrong_ specification is not.
  893. *
  894. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  895. * three-operand instructions such as SHLD: it implies that the
  896. * first two operands must match in size, but that the third is
  897. * required to be _unspecified_.
  898. *
  899. * IF_SB invokes Size Byte: operands with unspecified size in the
  900. * template are really bytes, and so no non-byte specification in
  901. * the input instruction will be tolerated. IF_SW similarly invokes
  902. * Size Word, and IF_SD invokes Size Doubleword.
  903. *
  904. * (The default state if neither IF_SM nor IF_SM2 is specified is
  905. * that any operand with unspecified size in the template is
  906. * required to have unspecified size in the instruction too...)
  907. }
  908. var
  909. i,j,asize,oprs : longint;
  910. siz : array[0..2] of longint;
  911. begin
  912. Matches:=100;
  913. { Check the opcode and operands }
  914. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  915. begin
  916. Matches:=0;
  917. exit;
  918. end;
  919. { Check that no spurious colons or TOs are present }
  920. for i:=0 to p^.ops-1 do
  921. if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
  922. begin
  923. Matches:=0;
  924. exit;
  925. end;
  926. { Check that the operand flags all match up }
  927. for i:=0 to p^.ops-1 do
  928. begin
  929. if ((p^.optypes[i] and (not oper[i]^.ot)) or
  930. ((p^.optypes[i] and OT_SIZE_MASK) and
  931. ((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
  932. begin
  933. if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
  934. (oper[i]^.ot and OT_SIZE_MASK))<>0 then
  935. begin
  936. Matches:=0;
  937. exit;
  938. end
  939. else
  940. Matches:=1;
  941. end;
  942. end;
  943. { Check operand sizes }
  944. { as default an untyped size can get all the sizes, this is different
  945. from nasm, but else we need to do a lot checking which opcodes want
  946. size or not with the automatic size generation }
  947. asize:=longint($ffffffff);
  948. if (p^.flags and IF_SB)<>0 then
  949. asize:=OT_BITS8
  950. else if (p^.flags and IF_SW)<>0 then
  951. asize:=OT_BITS16
  952. else if (p^.flags and IF_SD)<>0 then
  953. asize:=OT_BITS32;
  954. if (p^.flags and IF_ARMASK)<>0 then
  955. begin
  956. siz[0]:=0;
  957. siz[1]:=0;
  958. siz[2]:=0;
  959. if (p^.flags and IF_AR0)<>0 then
  960. siz[0]:=asize
  961. else if (p^.flags and IF_AR1)<>0 then
  962. siz[1]:=asize
  963. else if (p^.flags and IF_AR2)<>0 then
  964. siz[2]:=asize;
  965. end
  966. else
  967. begin
  968. { we can leave because the size for all operands is forced to be
  969. the same
  970. but not if IF_SB IF_SW or IF_SD is set PM }
  971. if asize=-1 then
  972. exit;
  973. siz[0]:=asize;
  974. siz[1]:=asize;
  975. siz[2]:=asize;
  976. end;
  977. if (p^.flags and (IF_SM or IF_SM2))<>0 then
  978. begin
  979. if (p^.flags and IF_SM2)<>0 then
  980. oprs:=2
  981. else
  982. oprs:=p^.ops;
  983. for i:=0 to oprs-1 do
  984. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  985. begin
  986. for j:=0 to oprs-1 do
  987. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  988. break;
  989. end;
  990. end
  991. else
  992. oprs:=2;
  993. { Check operand sizes }
  994. for i:=0 to p^.ops-1 do
  995. begin
  996. if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
  997. ((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
  998. { Immediates can always include smaller size }
  999. ((oper[i]^.ot and OT_IMMEDIATE)=0) and
  1000. (((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
  1001. Matches:=2;
  1002. end;
  1003. end;
  1004. procedure taicpu.ResetPass1;
  1005. begin
  1006. { we need to reset everything here, because the choosen insentry
  1007. can be invalid for a new situation where the previously optimized
  1008. insentry is not correct }
  1009. InsEntry:=nil;
  1010. InsSize:=0;
  1011. LastInsOffset:=-1;
  1012. end;
  1013. procedure taicpu.ResetPass2;
  1014. begin
  1015. { we are here in a second pass, check if the instruction can be optimized }
  1016. if assigned(InsEntry) and
  1017. ((InsEntry^.flags and IF_PASS2)<>0) then
  1018. begin
  1019. InsEntry:=nil;
  1020. InsSize:=0;
  1021. end;
  1022. LastInsOffset:=-1;
  1023. end;
  1024. function taicpu.CheckIfValid:boolean;
  1025. begin
  1026. result:=FindInsEntry;
  1027. end;
  1028. function taicpu.FindInsentry:boolean;
  1029. var
  1030. i : longint;
  1031. begin
  1032. result:=false;
  1033. { Things which may only be done once, not when a second pass is done to
  1034. optimize }
  1035. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1036. begin
  1037. { We need intel style operands }
  1038. SetOperandOrder(op_intel);
  1039. { create the .ot fields }
  1040. create_ot;
  1041. { set the file postion }
  1042. aktfilepos:=fileinfo;
  1043. end
  1044. else
  1045. begin
  1046. { we've already an insentry so it's valid }
  1047. result:=true;
  1048. exit;
  1049. end;
  1050. { Lookup opcode in the table }
  1051. InsSize:=-1;
  1052. i:=instabcache^[opcode];
  1053. if i=-1 then
  1054. begin
  1055. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1056. exit;
  1057. end;
  1058. insentry:=@instab[i];
  1059. while (insentry^.opcode=opcode) do
  1060. begin
  1061. if matches(insentry)=100 then
  1062. begin
  1063. result:=true;
  1064. exit;
  1065. end;
  1066. inc(i);
  1067. insentry:=@instab[i];
  1068. end;
  1069. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1070. { No instruction found, set insentry to nil and inssize to -1 }
  1071. insentry:=nil;
  1072. inssize:=-1;
  1073. end;
  1074. function taicpu.Pass1(offset:longint):longint;
  1075. begin
  1076. Pass1:=0;
  1077. { Save the old offset and set the new offset }
  1078. InsOffset:=Offset;
  1079. { Error? }
  1080. if (Insentry=nil) and (InsSize=-1) then
  1081. exit;
  1082. { set the file postion }
  1083. aktfilepos:=fileinfo;
  1084. { Get InsEntry }
  1085. if FindInsEntry then
  1086. begin
  1087. { Calculate instruction size }
  1088. InsSize:=calcsize(insentry);
  1089. if segprefix<>NR_NO then
  1090. inc(InsSize);
  1091. { Fix opsize if size if forced }
  1092. if (insentry^.flags and (IF_SB or IF_SW or IF_SD))<>0 then
  1093. begin
  1094. if (insentry^.flags and IF_ARMASK)=0 then
  1095. begin
  1096. if (insentry^.flags and IF_SB)<>0 then
  1097. begin
  1098. if opsize=S_NO then
  1099. opsize:=S_B;
  1100. end
  1101. else if (insentry^.flags and IF_SW)<>0 then
  1102. begin
  1103. if opsize=S_NO then
  1104. opsize:=S_W;
  1105. end
  1106. else if (insentry^.flags and IF_SD)<>0 then
  1107. begin
  1108. if opsize=S_NO then
  1109. opsize:=S_L;
  1110. end;
  1111. end;
  1112. end;
  1113. LastInsOffset:=InsOffset;
  1114. Pass1:=InsSize;
  1115. exit;
  1116. end;
  1117. LastInsOffset:=-1;
  1118. end;
  1119. procedure taicpu.Pass2(sec:TAsmObjectData);
  1120. var
  1121. c : longint;
  1122. begin
  1123. { error in pass1 ? }
  1124. if insentry=nil then
  1125. exit;
  1126. aktfilepos:=fileinfo;
  1127. { Segment override }
  1128. if (segprefix<>NR_NO) then
  1129. begin
  1130. case segprefix of
  1131. NR_CS : c:=$2e;
  1132. NR_DS : c:=$3e;
  1133. NR_ES : c:=$26;
  1134. NR_FS : c:=$64;
  1135. NR_GS : c:=$65;
  1136. NR_SS : c:=$36;
  1137. end;
  1138. sec.writebytes(c,1);
  1139. { fix the offset for GenNode }
  1140. inc(InsOffset);
  1141. end;
  1142. { Generate the instruction }
  1143. GenCode(sec);
  1144. end;
  1145. function taicpu.needaddrprefix(opidx:byte):boolean;
  1146. begin
  1147. needaddrprefix:=false;
  1148. if (OT_MEMORY and (not oper[opidx]^.ot))=0 then
  1149. begin
  1150. if (
  1151. (oper[opidx]^.ref^.index<>NR_NO) and
  1152. (getsubreg(oper[opidx]^.ref^.index)<>R_SUBD)
  1153. ) or
  1154. (
  1155. (oper[opidx]^.ref^.base<>NR_NO) and
  1156. (getsubreg(oper[opidx]^.ref^.base)<>R_SUBD)
  1157. ) then
  1158. needaddrprefix:=true;
  1159. end;
  1160. end;
  1161. function regval(r:Tregister):byte;
  1162. const
  1163. {$ifdef x86_64}
  1164. opcode_table:array[tregisterindex] of tregisterindex = (
  1165. {$i r8664op.inc}
  1166. );
  1167. {$else x86_64}
  1168. opcode_table:array[tregisterindex] of tregisterindex = (
  1169. {$i r386op.inc}
  1170. );
  1171. {$endif x86_64}
  1172. var
  1173. regidx : tregisterindex;
  1174. begin
  1175. regidx:=findreg_by_number(r);
  1176. if regidx<>0 then
  1177. result:=opcode_table[regidx]
  1178. else
  1179. begin
  1180. Message1(asmw_e_invalid_register,generic_regname(r));
  1181. result:=0;
  1182. end;
  1183. end;
  1184. function process_ea(const input:toper;var output:ea;rfield:longint):boolean;
  1185. var
  1186. sym : tasmsymbol;
  1187. md,s,rv : byte;
  1188. base,index,scalefactor,
  1189. o : longint;
  1190. ir,br : Tregister;
  1191. isub,bsub : tsubregister;
  1192. begin
  1193. process_ea:=false;
  1194. {Register ?}
  1195. if (input.typ=top_reg) then
  1196. begin
  1197. rv:=regval(input.reg);
  1198. output.sib_present:=false;
  1199. output.bytes:=0;
  1200. output.modrm:=$c0 or (rfield shl 3) or rv;
  1201. output.size:=1;
  1202. process_ea:=true;
  1203. exit;
  1204. end;
  1205. {No register, so memory reference.}
  1206. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
  1207. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  1208. internalerror(200301081);
  1209. ir:=input.ref^.index;
  1210. br:=input.ref^.base;
  1211. isub:=getsubreg(ir);
  1212. bsub:=getsubreg(br);
  1213. s:=input.ref^.scalefactor;
  1214. o:=input.ref^.offset;
  1215. sym:=input.ref^.symbol;
  1216. { it's direct address }
  1217. if (br=NR_NO) and (ir=NR_NO) then
  1218. begin
  1219. { it's a pure offset }
  1220. output.sib_present:=false;
  1221. output.bytes:=4;
  1222. output.modrm:=5 or (rfield shl 3);
  1223. end
  1224. else
  1225. { it's an indirection }
  1226. begin
  1227. { 16 bit address? }
  1228. if ((ir<>NR_NO) and (isub<>R_SUBD)) or
  1229. ((br<>NR_NO) and (bsub<>R_SUBD)) then
  1230. message(asmw_e_16bit_not_supported);
  1231. {$ifdef OPTEA}
  1232. { make single reg base }
  1233. if (br=NR_NO) and (s=1) then
  1234. begin
  1235. br:=ir;
  1236. ir:=NR_NO;
  1237. end;
  1238. { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX }
  1239. if (br=NR_NO) and
  1240. (((s=2) and (ir<>NR_ESP)) or
  1241. (s=3) or (s=5) or (s=9)) then
  1242. begin
  1243. br:=ir;
  1244. dec(s);
  1245. end;
  1246. { swap ESP into base if scalefactor is 1 }
  1247. if (s=1) and (ir=NR_ESP) then
  1248. begin
  1249. ir:=br;
  1250. br:=NR_ESP;
  1251. end;
  1252. {$endif OPTEA}
  1253. { wrong, for various reasons }
  1254. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1255. exit;
  1256. { base }
  1257. case br of
  1258. NR_EAX : base:=0;
  1259. NR_ECX : base:=1;
  1260. NR_EDX : base:=2;
  1261. NR_EBX : base:=3;
  1262. NR_ESP : base:=4;
  1263. NR_NO,
  1264. NR_EBP : base:=5;
  1265. NR_ESI : base:=6;
  1266. NR_EDI : base:=7;
  1267. else
  1268. exit;
  1269. end;
  1270. { index }
  1271. case ir of
  1272. NR_EAX : index:=0;
  1273. NR_ECX : index:=1;
  1274. NR_EDX : index:=2;
  1275. NR_EBX : index:=3;
  1276. NR_NO : index:=4;
  1277. NR_EBP : index:=5;
  1278. NR_ESI : index:=6;
  1279. NR_EDI : index:=7;
  1280. else
  1281. exit;
  1282. end;
  1283. case s of
  1284. 0,
  1285. 1 : scalefactor:=0;
  1286. 2 : scalefactor:=1;
  1287. 4 : scalefactor:=2;
  1288. 8 : scalefactor:=3;
  1289. else
  1290. exit;
  1291. end;
  1292. if (br=NR_NO) or
  1293. ((br<>NR_EBP) and (o=0) and (sym=nil)) then
  1294. md:=0
  1295. else
  1296. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1297. md:=1
  1298. else
  1299. md:=2;
  1300. if (br=NR_NO) or (md=2) then
  1301. output.bytes:=4
  1302. else
  1303. output.bytes:=md;
  1304. { SIB needed ? }
  1305. if (ir=NR_NO) and (br<>NR_ESP) then
  1306. begin
  1307. output.sib_present:=false;
  1308. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  1309. end
  1310. else
  1311. begin
  1312. output.sib_present:=true;
  1313. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  1314. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1315. end;
  1316. end;
  1317. if output.sib_present then
  1318. output.size:=2+output.bytes
  1319. else
  1320. output.size:=1+output.bytes;
  1321. process_ea:=true;
  1322. end;
  1323. function taicpu.calcsize(p:PInsEntry):longint;
  1324. var
  1325. codes : pchar;
  1326. c : byte;
  1327. len : longint;
  1328. ea_data : ea;
  1329. begin
  1330. len:=0;
  1331. codes:=@p^.code;
  1332. repeat
  1333. c:=ord(codes^);
  1334. inc(codes);
  1335. case c of
  1336. 0 :
  1337. break;
  1338. 1,2,3 :
  1339. begin
  1340. inc(codes,c);
  1341. inc(len,c);
  1342. end;
  1343. 8,9,10 :
  1344. begin
  1345. inc(codes);
  1346. inc(len);
  1347. end;
  1348. 4,5,6,7 :
  1349. begin
  1350. if opsize=S_W then
  1351. inc(len,2)
  1352. else
  1353. inc(len);
  1354. end;
  1355. 15,
  1356. 12,13,14,
  1357. 16,17,18,
  1358. 20,21,22,
  1359. 40,41,42 :
  1360. inc(len);
  1361. 24,25,26,
  1362. 31,
  1363. 48,49,50 :
  1364. inc(len,2);
  1365. 28,29,30, { we don't have 16 bit immediates code }
  1366. 32,33,34,
  1367. 52,53,54,
  1368. 56,57,58 :
  1369. inc(len,4);
  1370. 192,193,194 :
  1371. if NeedAddrPrefix(c-192) then
  1372. inc(len);
  1373. 208,
  1374. 210 :
  1375. inc(len);
  1376. 200,
  1377. 201,
  1378. 202,
  1379. 209,
  1380. 211,
  1381. 217,218: ;
  1382. 219,220 :
  1383. inc(len);
  1384. 216 :
  1385. begin
  1386. inc(codes);
  1387. inc(len);
  1388. end;
  1389. 224,225,226 :
  1390. begin
  1391. InternalError(777002);
  1392. end;
  1393. else
  1394. begin
  1395. if (c>=64) and (c<=191) then
  1396. begin
  1397. if not process_ea(oper[(c shr 3) and 7]^, ea_data, 0) then
  1398. Message(asmw_e_invalid_effective_address)
  1399. else
  1400. inc(len,ea_data.size);
  1401. end
  1402. else
  1403. InternalError(777003);
  1404. end;
  1405. end;
  1406. until false;
  1407. calcsize:=len;
  1408. end;
  1409. procedure taicpu.GenCode(sec:TAsmObjectData);
  1410. {
  1411. * the actual codes (C syntax, i.e. octal):
  1412. * \0 - terminates the code. (Unless it's a literal of course.)
  1413. * \1, \2, \3 - that many literal bytes follow in the code stream
  1414. * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  1415. * (POP is never used for CS) depending on operand 0
  1416. * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
  1417. * on operand 0
  1418. * \10, \11, \12 - a literal byte follows in the code stream, to be added
  1419. * to the register value of operand 0, 1 or 2
  1420. * \17 - encodes the literal byte 0. (Some compilers don't take
  1421. * kindly to a zero byte in the _middle_ of a compile time
  1422. * string constant, so I had to put this hack in.)
  1423. * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
  1424. * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
  1425. * \24, \25, \26 - an unsigned byte immediate operand, from operand 0, 1 or 2
  1426. * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
  1427. * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
  1428. * assembly mode or the address-size override on the operand
  1429. * \37 - a word constant, from the _segment_ part of operand 0
  1430. * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
  1431. * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
  1432. * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
  1433. * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
  1434. * assembly mode or the address-size override on the operand
  1435. * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
  1436. * \1ab - a ModRM, calculated on EA in operand a, with the spare
  1437. * field the register value of operand b.
  1438. * \2ab - a ModRM, calculated on EA in operand a, with the spare
  1439. * field equal to digit b.
  1440. * \30x - might be an 0x67 byte, depending on the address size of
  1441. * the memory reference in operand x.
  1442. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
  1443. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
  1444. * \312 - indicates fixed 64-bit address size, i.e. optional 0x48.
  1445. * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
  1446. * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
  1447. * \322 - indicates fixed 64-bit operand size, i.e. optional 0x48.
  1448. * \323 - indicates that this instruction is only valid when the
  1449. * operand size is the default (instruction to disassembler,
  1450. * generates no code in the assembler)
  1451. * \330 - a literal byte follows in the code stream, to be added
  1452. * to the condition code value of the instruction.
  1453. * \340 - reserve <operand 0> bytes of uninitialised storage.
  1454. * Operand 0 had better be a segmentless constant.
  1455. }
  1456. var
  1457. currval : longint;
  1458. currsym : tasmsymbol;
  1459. procedure getvalsym(opidx:longint);
  1460. begin
  1461. case oper[opidx]^.typ of
  1462. top_ref :
  1463. begin
  1464. currval:=oper[opidx]^.ref^.offset;
  1465. currsym:=oper[opidx]^.ref^.symbol;
  1466. end;
  1467. top_const :
  1468. begin
  1469. currval:=longint(oper[opidx]^.val);
  1470. currsym:=nil;
  1471. end;
  1472. else
  1473. Message(asmw_e_immediate_or_reference_expected);
  1474. end;
  1475. end;
  1476. const
  1477. CondVal:array[TAsmCond] of byte=($0,
  1478. $7, $3, $2, $6, $2, $4, $F, $D, $C, $E, $6, $2,
  1479. $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
  1480. $0, $A, $A, $B, $8, $4);
  1481. var
  1482. c : byte;
  1483. pb,
  1484. codes : pchar;
  1485. bytes : array[0..3] of byte;
  1486. rfield,
  1487. data,s,opidx : longint;
  1488. ea_data : ea;
  1489. begin
  1490. {$ifdef EXTDEBUG}
  1491. { safety check }
  1492. if sec.sects[sec.currsec].datasize<>insoffset then
  1493. internalerror(200130121);
  1494. {$endif EXTDEBUG}
  1495. { load data to write }
  1496. codes:=insentry^.code;
  1497. { Force word push/pop for registers }
  1498. if (opsize=S_W) and ((codes[0]=#4) or (codes[0]=#6) or
  1499. ((codes[0]=#1) and ((codes[2]=#5) or (codes[2]=#7)))) then
  1500. begin
  1501. bytes[0]:=$66;
  1502. sec.writebytes(bytes,1);
  1503. end;
  1504. repeat
  1505. c:=ord(codes^);
  1506. inc(codes);
  1507. case c of
  1508. 0 :
  1509. break;
  1510. 1,2,3 :
  1511. begin
  1512. sec.writebytes(codes^,c);
  1513. inc(codes,c);
  1514. end;
  1515. 4,6 :
  1516. begin
  1517. case oper[0]^.reg of
  1518. NR_CS:
  1519. bytes[0]:=$e;
  1520. NR_NO,
  1521. NR_DS:
  1522. bytes[0]:=$1e;
  1523. NR_ES:
  1524. bytes[0]:=$6;
  1525. NR_SS:
  1526. bytes[0]:=$16;
  1527. else
  1528. internalerror(777004);
  1529. end;
  1530. if c=4 then
  1531. inc(bytes[0]);
  1532. sec.writebytes(bytes,1);
  1533. end;
  1534. 5,7 :
  1535. begin
  1536. case oper[0]^.reg of
  1537. NR_FS:
  1538. bytes[0]:=$a0;
  1539. NR_GS:
  1540. bytes[0]:=$a8;
  1541. else
  1542. internalerror(777005);
  1543. end;
  1544. if c=5 then
  1545. inc(bytes[0]);
  1546. sec.writebytes(bytes,1);
  1547. end;
  1548. 8,9,10 :
  1549. begin
  1550. bytes[0]:=ord(codes^)+regval(oper[c-8]^.reg);
  1551. inc(codes);
  1552. sec.writebytes(bytes,1);
  1553. end;
  1554. 15 :
  1555. begin
  1556. bytes[0]:=0;
  1557. sec.writebytes(bytes,1);
  1558. end;
  1559. 12,13,14 :
  1560. begin
  1561. getvalsym(c-12);
  1562. if (currval<-128) or (currval>127) then
  1563. Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
  1564. if assigned(currsym) then
  1565. sec.writereloc(currval,1,currsym,RELOC_ABSOLUTE)
  1566. else
  1567. sec.writebytes(currval,1);
  1568. end;
  1569. 16,17,18 :
  1570. begin
  1571. getvalsym(c-16);
  1572. if (currval<-256) or (currval>255) then
  1573. Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
  1574. if assigned(currsym) then
  1575. sec.writereloc(currval,1,currsym,RELOC_ABSOLUTE)
  1576. else
  1577. sec.writebytes(currval,1);
  1578. end;
  1579. 20,21,22 :
  1580. begin
  1581. getvalsym(c-20);
  1582. if (currval<0) or (currval>255) then
  1583. Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
  1584. if assigned(currsym) then
  1585. sec.writereloc(currval,1,currsym,RELOC_ABSOLUTE)
  1586. else
  1587. sec.writebytes(currval,1);
  1588. end;
  1589. 24,25,26 :
  1590. begin
  1591. getvalsym(c-24);
  1592. if (currval<-65536) or (currval>65535) then
  1593. Message2(asmw_e_value_exceeds_bounds,'word',tostr(currval));
  1594. if assigned(currsym) then
  1595. sec.writereloc(currval,2,currsym,RELOC_ABSOLUTE)
  1596. else
  1597. sec.writebytes(currval,2);
  1598. end;
  1599. 28,29,30 :
  1600. begin
  1601. getvalsym(c-28);
  1602. if assigned(currsym) then
  1603. sec.writereloc(currval,4,currsym,RELOC_ABSOLUTE)
  1604. else
  1605. sec.writebytes(currval,4);
  1606. end;
  1607. 32,33,34 :
  1608. begin
  1609. getvalsym(c-32);
  1610. if assigned(currsym) then
  1611. sec.writereloc(currval,4,currsym,RELOC_ABSOLUTE)
  1612. else
  1613. sec.writebytes(currval,4);
  1614. end;
  1615. 40,41,42 :
  1616. begin
  1617. getvalsym(c-40);
  1618. data:=currval-insend;
  1619. if assigned(currsym) then
  1620. inc(data,currsym.address);
  1621. if (data>127) or (data<-128) then
  1622. Message1(asmw_e_short_jmp_out_of_range,tostr(data));
  1623. sec.writebytes(data,1);
  1624. end;
  1625. 52,53,54 :
  1626. begin
  1627. getvalsym(c-52);
  1628. if assigned(currsym) then
  1629. sec.writereloc(currval,4,currsym,RELOC_RELATIVE)
  1630. else
  1631. sec.writereloc(currval-insend,4,nil,RELOC_ABSOLUTE)
  1632. end;
  1633. 56,57,58 :
  1634. begin
  1635. getvalsym(c-56);
  1636. if assigned(currsym) then
  1637. sec.writereloc(currval,4,currsym,RELOC_RELATIVE)
  1638. else
  1639. sec.writereloc(currval-insend,4,nil,RELOC_ABSOLUTE)
  1640. end;
  1641. 192,193,194 :
  1642. begin
  1643. if NeedAddrPrefix(c-192) then
  1644. begin
  1645. bytes[0]:=$67;
  1646. sec.writebytes(bytes,1);
  1647. end;
  1648. end;
  1649. 200 :
  1650. begin
  1651. bytes[0]:=$67;
  1652. sec.writebytes(bytes,1);
  1653. end;
  1654. 208 :
  1655. begin
  1656. bytes[0]:=$66;
  1657. sec.writebytes(bytes,1);
  1658. end;
  1659. 210 :
  1660. begin
  1661. bytes[0]:=$48;
  1662. sec.writebytes(bytes,1);
  1663. end;
  1664. 216 :
  1665. begin
  1666. bytes[0]:=ord(codes^)+condval[condition];
  1667. inc(codes);
  1668. sec.writebytes(bytes,1);
  1669. end;
  1670. 201,
  1671. 202,
  1672. 209,
  1673. 211,
  1674. 217,218 :
  1675. begin
  1676. { these are dissambler hints or 32 bit prefixes which
  1677. are not needed }
  1678. end;
  1679. 219 :
  1680. begin
  1681. bytes[0]:=$f3;
  1682. sec.writebytes(bytes,1);
  1683. end;
  1684. 220 :
  1685. begin
  1686. bytes[0]:=$f2;
  1687. sec.writebytes(bytes,1);
  1688. end;
  1689. 31,
  1690. 48,49,50,
  1691. 224,225,226 :
  1692. begin
  1693. InternalError(777006);
  1694. end
  1695. else
  1696. begin
  1697. if (c>=64) and (c<=191) then
  1698. begin
  1699. if (c<127) then
  1700. begin
  1701. if (oper[c and 7]^.typ=top_reg) then
  1702. rfield:=regval(oper[c and 7]^.reg)
  1703. else
  1704. rfield:=regval(oper[c and 7]^.ref^.base);
  1705. end
  1706. else
  1707. rfield:=c and 7;
  1708. opidx:=(c shr 3) and 7;
  1709. if not process_ea(oper[opidx]^,ea_data,rfield) then
  1710. Message(asmw_e_invalid_effective_address);
  1711. pb:=@bytes;
  1712. pb^:=chr(ea_data.modrm);
  1713. inc(pb);
  1714. if ea_data.sib_present then
  1715. begin
  1716. pb^:=chr(ea_data.sib);
  1717. inc(pb);
  1718. end;
  1719. s:=pb-pchar(@bytes);
  1720. sec.writebytes(bytes,s);
  1721. case ea_data.bytes of
  1722. 0 : ;
  1723. 1 :
  1724. begin
  1725. if (oper[opidx]^.ot and OT_MEMORY)=OT_MEMORY then
  1726. sec.writereloc(oper[opidx]^.ref^.offset,1,oper[opidx]^.ref^.symbol,RELOC_ABSOLUTE)
  1727. else
  1728. begin
  1729. bytes[0]:=oper[opidx]^.ref^.offset;
  1730. sec.writebytes(bytes,1);
  1731. end;
  1732. inc(s);
  1733. end;
  1734. 2,4 :
  1735. begin
  1736. sec.writereloc(oper[opidx]^.ref^.offset,ea_data.bytes,
  1737. oper[opidx]^.ref^.symbol,RELOC_ABSOLUTE);
  1738. inc(s,ea_data.bytes);
  1739. end;
  1740. end;
  1741. end
  1742. else
  1743. InternalError(777007);
  1744. end;
  1745. end;
  1746. until false;
  1747. end;
  1748. {$endif NOAG386BIN}
  1749. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  1750. begin
  1751. result:=(regtype = R_INTREGISTER) and
  1752. (ops=2) and
  1753. (oper[0]^.typ=top_reg) and
  1754. (oper[1]^.typ=top_reg) and
  1755. (oper[0]^.reg=oper[1]^.reg) and
  1756. ((opcode=A_MOV) or (opcode=A_XCHG));
  1757. end;
  1758. {*****************************************************************************
  1759. Instruction table
  1760. *****************************************************************************}
  1761. procedure BuildInsTabCache;
  1762. {$ifndef NOAG386BIN}
  1763. var
  1764. i : longint;
  1765. {$endif}
  1766. begin
  1767. {$ifndef NOAG386BIN}
  1768. new(instabcache);
  1769. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  1770. i:=0;
  1771. while (i<InsTabEntries) do
  1772. begin
  1773. if InsTabCache^[InsTab[i].OPcode]=-1 then
  1774. InsTabCache^[InsTab[i].OPcode]:=i;
  1775. inc(i);
  1776. end;
  1777. {$endif NOAG386BIN}
  1778. end;
  1779. procedure InitAsm;
  1780. begin
  1781. {$ifndef NOAG386BIN}
  1782. if not assigned(instabcache) then
  1783. BuildInsTabCache;
  1784. {$endif NOAG386BIN}
  1785. end;
  1786. procedure DoneAsm;
  1787. begin
  1788. {$ifndef NOAG386BIN}
  1789. if assigned(instabcache) then
  1790. begin
  1791. dispose(instabcache);
  1792. instabcache:=nil;
  1793. end;
  1794. {$endif NOAG386BIN}
  1795. end;
  1796. end.
  1797. {
  1798. $Log$
  1799. Revision 1.53 2004-03-04 17:25:38 peter
  1800. * top_none in create_ot, it is used in error situations
  1801. Revision 1.52 2004/02/27 10:21:05 florian
  1802. * top_symbol killed
  1803. + refaddr to treference added
  1804. + refsymbol to treference added
  1805. * top_local stuff moved to an extra record to save memory
  1806. + aint introduced
  1807. * tppufile.get/putint64/aint implemented
  1808. Revision 1.51 2004/02/09 22:14:17 peter
  1809. * more x86_64 parameter fixes
  1810. * tparalocation.lochigh is now used to indicate if registerhigh
  1811. is used and what the type is
  1812. Revision 1.50 2004/02/08 23:10:21 jonas
  1813. * taicpu.is_same_reg_move() now gets a regtype parameter so it only
  1814. removes moves of that particular register type. This is necessary so
  1815. we don't remove the live_start instruction of a register before it
  1816. has been processed
  1817. Revision 1.49 2004/02/08 20:15:43 jonas
  1818. - removed taicpu.is_reg_move because it's not used anymore
  1819. + support tracking fpu register moves by rgobj for the ppc
  1820. Revision 1.48 2004/02/05 18:28:37 peter
  1821. * x86_64 fixes for opsize
  1822. Revision 1.47 2004/02/03 21:21:23 peter
  1823. * real fix for the short jmp out of range problem. Only forward jumps
  1824. needs an offset correction. For backward jumps both the address of
  1825. the symbol and the instruction are already updated so no correction
  1826. is required.
  1827. Revision 1.46 2004/01/26 16:12:28 daniel
  1828. * reginfo now also only allocated during register allocation
  1829. * third round of gdb cleanups: kick out most of concatstabto
  1830. Revision 1.45 2004/01/15 14:01:32 florian
  1831. + x86 instruction tables for x86-64 extended
  1832. Revision 1.44 2004/01/12 16:37:59 peter
  1833. * moved spilling code from taicpu to rg
  1834. Revision 1.43 2003/12/26 14:02:30 peter
  1835. * sparc updates
  1836. * use registertype in spill_register
  1837. Revision 1.42 2003/12/25 12:01:35 florian
  1838. + possible sse2 unit usage for double calculations
  1839. * some sse2 assembler issues fixed
  1840. Revision 1.41 2003/12/25 01:07:09 florian
  1841. + $fputype directive support
  1842. + single data type operations with sse unit
  1843. * fixed more x86-64 stuff
  1844. Revision 1.40 2003/12/15 21:25:49 peter
  1845. * reg allocations for imaginary register are now inserted just
  1846. before reg allocation
  1847. * tregister changed to enum to allow compile time check
  1848. * fixed several tregister-tsuperregister errors
  1849. Revision 1.39 2003/12/14 20:24:28 daniel
  1850. * Register allocator speed optimizations
  1851. - Worklist no longer a ringbuffer
  1852. - No find operations are left
  1853. - Simplify now done in constant time
  1854. - unusedregs is now a Tsuperregisterworklist
  1855. - Microoptimizations
  1856. Revision 1.38 2003/11/12 16:05:40 florian
  1857. * assembler readers OOPed
  1858. + typed currency constants
  1859. + typed 128 bit float constants if the CPU supports it
  1860. Revision 1.37 2003/10/30 19:59:00 peter
  1861. * support scalefactor for opr_local
  1862. * support reference with opr_local set, fixes tw2631
  1863. Revision 1.36 2003/10/29 15:40:20 peter
  1864. * support indexing and offset retrieval for locals
  1865. Revision 1.35 2003/10/23 14:44:07 peter
  1866. * splitted buildderef and buildderefimpl to fix interface crc
  1867. calculation
  1868. Revision 1.34 2003/10/22 20:40:00 peter
  1869. * write derefdata in a separate ppu entry
  1870. Revision 1.33 2003/10/21 15:15:36 peter
  1871. * taicpu_abstract.oper[] changed to pointers
  1872. Revision 1.32 2003/10/17 14:38:32 peter
  1873. * 64k registers supported
  1874. * fixed some memory leaks
  1875. Revision 1.31 2003/10/09 21:31:37 daniel
  1876. * Register allocator splitted, ans abstract now
  1877. Revision 1.30 2003/10/01 20:34:50 peter
  1878. * procinfo unit contains tprocinfo
  1879. * cginfo renamed to cgbase
  1880. * moved cgmessage to verbose
  1881. * fixed ppc and sparc compiles
  1882. Revision 1.29 2003/09/29 20:58:56 peter
  1883. * optimized releasing of registers
  1884. Revision 1.28 2003/09/28 21:49:30 peter
  1885. * fixed invalid opcode handling in spill registers
  1886. Revision 1.27 2003/09/28 13:37:07 peter
  1887. * give error for wrong register number
  1888. Revision 1.26 2003/09/24 21:15:49 florian
  1889. * fixed make cycle
  1890. Revision 1.25 2003/09/24 17:12:36 florian
  1891. * x86-64 adaptions
  1892. Revision 1.24 2003/09/23 17:56:06 peter
  1893. * locals and paras are allocated in the code generation
  1894. * tvarsym.localloc contains the location of para/local when
  1895. generating code for the current procedure
  1896. Revision 1.23 2003/09/14 14:22:51 daniel
  1897. * Fixed incorrect movzx spilling
  1898. Revision 1.22 2003/09/12 20:25:17 daniel
  1899. * Add BTR to destination memory location check in spilling
  1900. Revision 1.21 2003/09/10 19:14:31 daniel
  1901. * Failed attempt to restore broken fastspill functionality
  1902. Revision 1.20 2003/09/10 11:23:09 marco
  1903. * fix from peter for bts reg32,mem32 problem
  1904. Revision 1.19 2003/09/09 12:54:45 florian
  1905. * x86 instruction table updated to nasm 0.98.37:
  1906. - sse3 aka prescott support
  1907. - small fixes
  1908. Revision 1.18 2003/09/07 22:09:35 peter
  1909. * preparations for different default calling conventions
  1910. * various RA fixes
  1911. Revision 1.17 2003/09/03 15:55:02 peter
  1912. * NEWRA branch merged
  1913. Revision 1.16.2.4 2003/08/31 15:46:26 peter
  1914. * more updates for tregister
  1915. Revision 1.16.2.3 2003/08/29 17:29:00 peter
  1916. * next batch of updates
  1917. Revision 1.16.2.2 2003/08/28 18:35:08 peter
  1918. * tregister changed to cardinal
  1919. Revision 1.16.2.1 2003/08/27 19:55:54 peter
  1920. * first tregister patch
  1921. Revision 1.16 2003/08/21 17:20:19 peter
  1922. * first spill the registers of top_ref before spilling top_reg
  1923. Revision 1.15 2003/08/21 14:48:36 peter
  1924. * fix reg-supreg range check error
  1925. Revision 1.14 2003/08/20 16:52:01 daniel
  1926. * Some old register convention code removed
  1927. * A few changes to eliminate a few lines of code
  1928. Revision 1.13 2003/08/20 09:07:00 daniel
  1929. * New register coding now mandatory, some more convert_registers calls
  1930. removed.
  1931. Revision 1.12 2003/08/20 07:48:04 daniel
  1932. * Made internal assembler use new register coding
  1933. Revision 1.11 2003/08/19 13:58:33 daniel
  1934. * Corrected a comment.
  1935. Revision 1.10 2003/08/15 14:44:20 daniel
  1936. * Fixed newra compilation
  1937. Revision 1.9 2003/08/11 21:18:20 peter
  1938. * start of sparc support for newra
  1939. Revision 1.8 2003/08/09 18:56:54 daniel
  1940. * cs_regalloc renamed to cs_regvars to avoid confusion with register
  1941. allocator
  1942. * Some preventive changes to i386 spillinh code
  1943. Revision 1.7 2003/07/06 15:31:21 daniel
  1944. * Fixed register allocator. *Lots* of fixes.
  1945. Revision 1.6 2003/06/14 14:53:50 jonas
  1946. * fixed newra cycle for x86
  1947. * added constants for indicating source and destination operands of the
  1948. "move reg,reg" instruction to aasmcpu (and use those in rgobj)
  1949. Revision 1.5 2003/06/03 13:01:59 daniel
  1950. * Register allocator finished
  1951. Revision 1.4 2003/05/30 23:57:08 peter
  1952. * more sparc cleanup
  1953. * accumulator removed, splitted in function_return_reg (called) and
  1954. function_result_reg (caller)
  1955. Revision 1.3 2003/05/22 21:33:31 peter
  1956. * removed some unit dependencies
  1957. Revision 1.2 2002/04/25 16:12:09 florian
  1958. * fixed more problems with cpubase and x86-64
  1959. Revision 1.1 2003/04/25 12:43:40 florian
  1960. * merged i386/aasmcpu and x86_64/aasmcpu to x86/aasmcpu
  1961. Revision 1.18 2003/04/25 12:04:31 florian
  1962. * merged agx64att and ag386att to x86/agx86att
  1963. Revision 1.17 2003/04/22 14:33:38 peter
  1964. * removed some notes/hints
  1965. Revision 1.16 2003/04/22 10:09:35 daniel
  1966. + Implemented the actual register allocator
  1967. + Scratch registers unavailable when new register allocator used
  1968. + maybe_save/maybe_restore unavailable when new register allocator used
  1969. Revision 1.15 2003/03/26 12:50:54 armin
  1970. * avoid problems with the ide in init/dome
  1971. Revision 1.14 2003/03/08 08:59:07 daniel
  1972. + $define newra will enable new register allocator
  1973. + getregisterint will return imaginary registers with $newra
  1974. + -sr switch added, will skip register allocation so you can see
  1975. the direct output of the code generator before register allocation
  1976. Revision 1.13 2003/02/25 07:41:54 daniel
  1977. * Properly fixed reversed operands bug
  1978. Revision 1.12 2003/02/19 22:00:15 daniel
  1979. * Code generator converted to new register notation
  1980. - Horribily outdated todo.txt removed
  1981. Revision 1.11 2003/01/09 20:40:59 daniel
  1982. * Converted some code in cgx86.pas to new register numbering
  1983. Revision 1.10 2003/01/08 18:43:57 daniel
  1984. * Tregister changed into a record
  1985. Revision 1.9 2003/01/05 13:36:53 florian
  1986. * x86-64 compiles
  1987. + very basic support for float128 type (x86-64 only)
  1988. Revision 1.8 2002/11/17 16:31:58 carl
  1989. * memory optimization (3-4%) : cleanup of tai fields,
  1990. cleanup of tdef and tsym fields.
  1991. * make it work for m68k
  1992. Revision 1.7 2002/11/15 01:58:54 peter
  1993. * merged changes from 1.0.7 up to 04-11
  1994. - -V option for generating bug report tracing
  1995. - more tracing for option parsing
  1996. - errors for cdecl and high()
  1997. - win32 import stabs
  1998. - win32 records<=8 are returned in eax:edx (turned off by default)
  1999. - heaptrc update
  2000. - more info for temp management in .s file with EXTDEBUG
  2001. Revision 1.6 2002/10/31 13:28:32 pierre
  2002. * correct last wrong fix for tw2158
  2003. Revision 1.5 2002/10/30 17:10:00 pierre
  2004. * merge of fix for tw2158 bug
  2005. Revision 1.4 2002/08/15 19:10:36 peter
  2006. * first things tai,tnode storing in ppu
  2007. Revision 1.3 2002/08/13 18:01:52 carl
  2008. * rename swatoperands to swapoperands
  2009. + m68k first compilable version (still needs a lot of testing):
  2010. assembler generator, system information , inline
  2011. assembler reader.
  2012. Revision 1.2 2002/07/20 11:57:59 florian
  2013. * types.pas renamed to defbase.pas because D6 contains a types
  2014. unit so this would conflicts if D6 programms are compiled
  2015. + Willamette/SSE2 instructions to assembler added
  2016. Revision 1.1 2002/07/01 18:46:29 peter
  2017. * internal linker
  2018. * reorganized aasm layer
  2019. }