cpuinfo.pas 24 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv5,
  28. cpu_armv6,
  29. cpu_armv7,
  30. cpu_armv7m,
  31. cpu_cortexm3
  32. );
  33. Const
  34. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv5];
  35. cpu_thumb = [];
  36. cpu_thumb2 = [cpu_armv7m,cpu_cortexm3];
  37. Type
  38. tfputype =
  39. (fpu_none,
  40. fpu_soft,
  41. fpu_libgcc,
  42. fpu_fpa,
  43. fpu_fpa10,
  44. fpu_fpa11,
  45. fpu_vfpv2,
  46. fpu_vfpv3
  47. );
  48. tcontrollertype =
  49. (ct_none,
  50. { Phillips }
  51. ct_lpc2114,
  52. ct_lpc2124,
  53. ct_lpc2194,
  54. { ATMEL }
  55. ct_at91sam7s256,
  56. ct_at91sam7se256,
  57. ct_at91sam7x256,
  58. ct_at91sam7xc256,
  59. { STMicroelectronics }
  60. ct_stm32f103rb,
  61. ct_stm32f103re,
  62. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  63. ct_lm3s1110,
  64. ct_lm3s1133,
  65. ct_lm3s1138,
  66. ct_lm3s1150,
  67. ct_lm3s1162,
  68. ct_lm3s1165,
  69. ct_lm3s1166,
  70. ct_lm3s2110,
  71. ct_lm3s2139,
  72. ct_lm3s6100,
  73. ct_lm3s6110,
  74. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  75. ct_lm3s1601,
  76. ct_lm3s1608,
  77. ct_lm3s1620,
  78. ct_lm3s1635,
  79. ct_lm3s1636,
  80. ct_lm3s1637,
  81. ct_lm3s1651,
  82. ct_lm3s2601,
  83. ct_lm3s2608,
  84. ct_lm3s2620,
  85. ct_lm3s2637,
  86. ct_lm3s2651,
  87. ct_lm3s6610,
  88. ct_lm3s6611,
  89. ct_lm3s6618,
  90. ct_lm3s6633,
  91. ct_lm3s6637,
  92. ct_lm3s8630,
  93. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  94. ct_lm3s1911,
  95. ct_lm3s1918,
  96. ct_lm3s1937,
  97. ct_lm3s1958,
  98. ct_lm3s1960,
  99. ct_lm3s1968,
  100. ct_lm3s1969,
  101. ct_lm3s2911,
  102. ct_lm3s2918,
  103. ct_lm3s2919,
  104. ct_lm3s2939,
  105. ct_lm3s2948,
  106. ct_lm3s2950,
  107. ct_lm3s2965,
  108. ct_lm3s6911,
  109. ct_lm3s6918,
  110. ct_lm3s6938,
  111. ct_lm3s6950,
  112. ct_lm3s6952,
  113. ct_lm3s6965,
  114. ct_lm3s8930,
  115. ct_lm3s8933,
  116. ct_lm3s8938,
  117. ct_lm3s8962,
  118. ct_lm3s8970,
  119. ct_lm3s8971,
  120. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  121. ct_lm3s5951,
  122. ct_lm3s5956,
  123. ct_lm3s1b21,
  124. ct_lm3s2b93,
  125. ct_lm3s5b91,
  126. ct_lm3s9b81,
  127. ct_lm3s9b90,
  128. ct_lm3s9b92,
  129. ct_lm3s9b95,
  130. ct_lm3s9b96,
  131. // generic Thumb2 target
  132. ct_thumb2bare
  133. );
  134. Const
  135. {# Size of native extended floating point type }
  136. extended_size = 12;
  137. {# Size of a multimedia register }
  138. mmreg_size = 16;
  139. { target cpu string (used by compiler options) }
  140. target_cpu_string = 'arm';
  141. { calling conventions supported by the code generator }
  142. supported_calling_conventions : tproccalloptions = [
  143. pocall_internproc,
  144. pocall_safecall,
  145. pocall_stdcall,
  146. { same as stdcall only different name mangling }
  147. pocall_cdecl,
  148. { same as stdcall only different name mangling }
  149. pocall_cppdecl,
  150. { same as stdcall but floating point numbers are handled like equal sized integers }
  151. pocall_softfloat,
  152. { same as stdcall (requires that all const records are passed by
  153. reference, but that's already done for stdcall) }
  154. pocall_mwpascal,
  155. { used for interrupt handling }
  156. pocall_interrupt
  157. ];
  158. cputypestr : array[tcputype] of string[8] = ('',
  159. 'ARMV3',
  160. 'ARMV4',
  161. 'ARMV5',
  162. 'ARMV6',
  163. 'ARMV7',
  164. 'ARMV7M',
  165. 'CORTEXM3'
  166. );
  167. fputypestr : array[tfputype] of string[6] = ('',
  168. 'SOFT',
  169. 'LIBGCC',
  170. 'FPA',
  171. 'FPA10',
  172. 'FPA11',
  173. 'VFPV2',
  174. 'VFPV3'
  175. );
  176. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  177. ((
  178. controllertypestr:'';
  179. controllerunitstr:'';
  180. interruptvectors:0;
  181. flashbase:0;
  182. flashsize:0;
  183. srambase:0;
  184. sramsize:0
  185. ),
  186. (
  187. controllertypestr:'LPC2114';
  188. controllerunitstr:'LPC21x4';
  189. interruptvectors:8;
  190. flashbase:$00000000;
  191. flashsize:$00040000;
  192. srambase:$40000000;
  193. sramsize:$00004000
  194. ),
  195. (
  196. controllertypestr:'LPC2124';
  197. controllerunitstr:'LPC21x4';
  198. interruptvectors:8;
  199. flashbase:$00000000;
  200. flashsize:$00040000;
  201. srambase:$40000000;
  202. sramsize:$00004000
  203. ),
  204. (
  205. controllertypestr:'LPC2194';
  206. controllerunitstr:'LPC21x4';
  207. interruptvectors:8;
  208. flashbase:$00000000;
  209. flashsize:$00040000;
  210. srambase:$40000000;
  211. sramsize:$00004000
  212. ),
  213. (
  214. controllertypestr:'AT91SAM7S256';
  215. controllerunitstr:'AT91SAM7x256';
  216. interruptvectors:8;
  217. flashbase:$00000000;
  218. flashsize:$00040000;
  219. srambase:$00200000;
  220. sramsize:$00010000
  221. ),
  222. (
  223. controllertypestr:'AT91SAM7SE256';
  224. controllerunitstr:'AT91SAM7x256';
  225. interruptvectors:8;
  226. flashbase:$00000000;
  227. flashsize:$00040000;
  228. srambase:$00200000;
  229. sramsize:$00010000
  230. ),
  231. (
  232. controllertypestr:'AT91SAM7X256';
  233. controllerunitstr:'AT91SAM7x256';
  234. interruptvectors:8;
  235. flashbase:$00000000;
  236. flashsize:$00040000;
  237. srambase:$00200000;
  238. sramsize:$00010000
  239. ),
  240. (
  241. controllertypestr:'AT91SAM7XC256';
  242. controllerunitstr:'AT91SAM7x256';
  243. interruptvectors:8;
  244. flashbase:$00000000;
  245. flashsize:$00040000;
  246. srambase:$00200000;
  247. sramsize:$00010000
  248. ),
  249. // ct_stm32f103rb,
  250. (
  251. controllertypestr:'STM32F103RB';
  252. controllerunitstr:'STM32F103';
  253. interruptvectors:12;
  254. flashbase:$08000000;
  255. flashsize:$00020000;
  256. srambase:$20000000;
  257. sramsize:$00005000
  258. ),
  259. // ct_stm32f103re,
  260. (
  261. controllertypestr:'STM32F103RE';
  262. controllerunitstr:'STM32F103';
  263. interruptvectors:12;
  264. flashbase:$08000000;
  265. flashsize:$00080000;
  266. srambase:$20000000;
  267. sramsize:$00010000
  268. ),
  269. { TI - 64 K Flash, 16 K SRAM Devices }
  270. // ct_lm3s1110,
  271. (
  272. controllertypestr:'LM3S1110';
  273. controllerunitstr:'LM3FURY';
  274. interruptvectors:72;
  275. flashbase:$00000000;
  276. flashsize:$00010000;
  277. srambase:$20000000;
  278. sramsize:$00004000
  279. ),
  280. // ct_lm3s1133,
  281. (
  282. controllertypestr:'LM3S1133';
  283. controllerunitstr:'LM3FURY';
  284. interruptvectors:72;
  285. flashbase:$00000000;
  286. flashsize:$00010000;
  287. srambase:$20000000;
  288. sramsize:$00004000
  289. ),
  290. // ct_lm3s1138,
  291. (
  292. controllertypestr:'LM3S1138';
  293. controllerunitstr:'LM3FURY';
  294. interruptvectors:72;
  295. flashbase:$00000000;
  296. flashsize:$00010000;
  297. srambase:$20000000;
  298. sramsize:$00004000
  299. ),
  300. // ct_lm3s1150,
  301. (
  302. controllertypestr:'LM3S1150';
  303. controllerunitstr:'LM3FURY';
  304. interruptvectors:72;
  305. flashbase:$00000000;
  306. flashsize:$00010000;
  307. srambase:$20000000;
  308. sramsize:$00004000
  309. ),
  310. // ct_lm3s1162,
  311. (
  312. controllertypestr:'LM3S1162';
  313. controllerunitstr:'LM3FURY';
  314. interruptvectors:72;
  315. flashbase:$00000000;
  316. flashsize:$00010000;
  317. srambase:$20000000;
  318. sramsize:$00004000
  319. ),
  320. // ct_lm3s1165,
  321. (
  322. controllertypestr:'LM3S1165';
  323. controllerunitstr:'LM3FURY';
  324. interruptvectors:72;
  325. flashbase:$00000000;
  326. flashsize:$00010000;
  327. srambase:$20000000;
  328. sramsize:$00004000
  329. ),
  330. // ct_lm3s1166,
  331. (
  332. controllertypestr:'LM3S1166';
  333. controllerunitstr:'LM3FURY';
  334. interruptvectors:72;
  335. flashbase:$00000000;
  336. flashsize:$00010000;
  337. srambase:$20000000;
  338. sramsize:$00004000
  339. ),
  340. // ct_lm3s2110,
  341. (
  342. controllertypestr:'LM3S2110';
  343. controllerunitstr:'LM3FURY';
  344. interruptvectors:72;
  345. flashbase:$00000000;
  346. flashsize:$00010000;
  347. srambase:$20000000;
  348. sramsize:$00004000
  349. ),
  350. // ct_lm3s2139,
  351. (
  352. controllertypestr:'LM3S2139';
  353. controllerunitstr:'LM3FURY';
  354. interruptvectors:72;
  355. flashbase:$00000000;
  356. flashsize:$00010000;
  357. srambase:$20000000;
  358. sramsize:$00004000
  359. ),
  360. // ct_lm3s6100,
  361. (
  362. controllertypestr:'LM3S6100';
  363. controllerunitstr:'LM3FURY';
  364. interruptvectors:72;
  365. flashbase:$00000000;
  366. flashsize:$00010000;
  367. srambase:$20000000;
  368. sramsize:$00004000
  369. ),
  370. // ct_lm3s6110,
  371. (
  372. controllertypestr:'LM3S6110';
  373. controllerunitstr:'LM3FURY';
  374. interruptvectors:72;
  375. flashbase:$00000000;
  376. flashsize:$00010000;
  377. srambase:$20000000;
  378. sramsize:$00004000
  379. ),
  380. { TI - 128K Flash, 32K SRAM devices }
  381. // ct_lm3s1601,
  382. (
  383. controllertypestr:'LM3S1601';
  384. controllerunitstr:'LM3FURY';
  385. interruptvectors:72;
  386. flashbase:$00000000;
  387. flashsize:$00020000;
  388. srambase:$20000000;
  389. sramsize:$00008000
  390. ),
  391. // ct_lm3s1608,
  392. (
  393. controllertypestr:'LM3S1608';
  394. controllerunitstr:'LM3FURY';
  395. interruptvectors:72;
  396. flashbase:$00000000;
  397. flashsize:$00020000;
  398. srambase:$20000000;
  399. sramsize:$00008000
  400. ),
  401. // ct_lm3s1620,
  402. (
  403. controllertypestr:'LM3S1620';
  404. controllerunitstr:'LM3FURY';
  405. interruptvectors:72;
  406. flashbase:$00000000;
  407. flashsize:$00020000;
  408. srambase:$20000000;
  409. sramsize:$00008000
  410. ),
  411. // ct_lm3s1635,
  412. (
  413. controllertypestr:'LM3S1635';
  414. controllerunitstr:'LM3FURY';
  415. interruptvectors:72;
  416. flashbase:$00000000;
  417. flashsize:$00020000;
  418. srambase:$20000000;
  419. sramsize:$00008000
  420. ),
  421. // ct_lm3s1636,
  422. (
  423. controllertypestr:'LM3S1636';
  424. controllerunitstr:'LM3FURY';
  425. interruptvectors:72;
  426. flashbase:$00000000;
  427. flashsize:$00020000;
  428. srambase:$20000000;
  429. sramsize:$00008000
  430. ),
  431. // ct_lm3s1637,
  432. (
  433. controllertypestr:'LM3S1637';
  434. controllerunitstr:'LM3FURY';
  435. interruptvectors:72;
  436. flashbase:$00000000;
  437. flashsize:$00020000;
  438. srambase:$20000000;
  439. sramsize:$00008000
  440. ),
  441. // ct_lm3s1651,
  442. (
  443. controllertypestr:'LM3S1651';
  444. controllerunitstr:'LM3FURY';
  445. interruptvectors:72;
  446. flashbase:$00000000;
  447. flashsize:$00020000;
  448. srambase:$20000000;
  449. sramsize:$00008000
  450. ),
  451. // ct_lm3s2601,
  452. (
  453. controllertypestr:'LM3S2601';
  454. controllerunitstr:'LM3FURY';
  455. interruptvectors:72;
  456. flashbase:$00000000;
  457. flashsize:$00020000;
  458. srambase:$20000000;
  459. sramsize:$00008000
  460. ),
  461. // ct_lm3s2608,
  462. (
  463. controllertypestr:'LM3S2608';
  464. controllerunitstr:'LM3FURY';
  465. interruptvectors:72;
  466. flashbase:$00000000;
  467. flashsize:$00020000;
  468. srambase:$20000000;
  469. sramsize:$00008000
  470. ),
  471. // ct_lm3s2620,
  472. (
  473. controllertypestr:'LM3S2620';
  474. controllerunitstr:'LM3FURY';
  475. interruptvectors:72;
  476. flashbase:$00000000;
  477. flashsize:$00020000;
  478. srambase:$20000000;
  479. sramsize:$00008000
  480. ),
  481. // ct_lm3s2637,
  482. (
  483. controllertypestr:'LM3S2637';
  484. controllerunitstr:'LM3FURY';
  485. interruptvectors:72;
  486. flashbase:$00000000;
  487. flashsize:$00020000;
  488. srambase:$20000000;
  489. sramsize:$00008000
  490. ),
  491. // ct_lm3s2651,
  492. (
  493. controllertypestr:'LM3S2651';
  494. controllerunitstr:'LM3FURY';
  495. interruptvectors:72;
  496. flashbase:$00000000;
  497. flashsize:$00020000;
  498. srambase:$20000000;
  499. sramsize:$00008000
  500. ),
  501. // ct_lm3s6610,
  502. (
  503. controllertypestr:'LM3S6610';
  504. controllerunitstr:'LM3FURY';
  505. interruptvectors:72;
  506. flashbase:$00000000;
  507. flashsize:$00020000;
  508. srambase:$20000000;
  509. sramsize:$00008000
  510. ),
  511. // ct_lm3s6611,
  512. (
  513. controllertypestr:'LM3S6611';
  514. controllerunitstr:'LM3FURY';
  515. interruptvectors:72;
  516. flashbase:$00000000;
  517. flashsize:$00020000;
  518. srambase:$20000000;
  519. sramsize:$00008000
  520. ),
  521. // ct_lm3s6618,
  522. (
  523. controllertypestr:'LM3S6618';
  524. controllerunitstr:'LM3FURY';
  525. interruptvectors:72;
  526. flashbase:$00000000;
  527. flashsize:$00020000;
  528. srambase:$20000000;
  529. sramsize:$00008000
  530. ),
  531. // ct_lm3s6633,
  532. (
  533. controllertypestr:'LM3S6633';
  534. controllerunitstr:'LM3FURY';
  535. interruptvectors:72;
  536. flashbase:$00000000;
  537. flashsize:$00020000;
  538. srambase:$20000000;
  539. sramsize:$00008000
  540. ),
  541. // ct_lm3s6637,
  542. (
  543. controllertypestr:'LM3S6637';
  544. controllerunitstr:'LM3FURY';
  545. interruptvectors:72;
  546. flashbase:$00000000;
  547. flashsize:$00020000;
  548. srambase:$20000000;
  549. sramsize:$00008000
  550. ),
  551. // ct_lm3s8630,
  552. (
  553. controllertypestr:'LM3S8630';
  554. controllerunitstr:'LM3FURY';
  555. interruptvectors:72;
  556. flashbase:$00000000;
  557. flashsize:$00020000;
  558. srambase:$20000000;
  559. sramsize:$00008000
  560. ),
  561. { TI - 256K Flash, 64K SRAM devices }
  562. // ct_lm3s1911,
  563. (
  564. controllertypestr:'LM3S1911';
  565. controllerunitstr:'LM3FURY';
  566. interruptvectors:72;
  567. flashbase:$00000000;
  568. flashsize:$00040000;
  569. srambase:$20000000;
  570. sramsize:$00010000
  571. ),
  572. // ct_lm3s1918,
  573. (
  574. controllertypestr:'LM3S1918';
  575. controllerunitstr:'LM3FURY';
  576. interruptvectors:72;
  577. flashbase:$00000000;
  578. flashsize:$00040000;
  579. srambase:$20000000;
  580. sramsize:$00010000
  581. ),
  582. // ct_lm3s1937,
  583. (
  584. controllertypestr:'LM3S1937';
  585. controllerunitstr:'LM3FURY';
  586. interruptvectors:72;
  587. flashbase:$00000000;
  588. flashsize:$00040000;
  589. srambase:$20000000;
  590. sramsize:$00010000
  591. ),
  592. // ct_lm3s1958,
  593. (
  594. controllertypestr:'LM3S1958';
  595. controllerunitstr:'LM3FURY';
  596. interruptvectors:72;
  597. flashbase:$00000000;
  598. flashsize:$00040000;
  599. srambase:$20000000;
  600. sramsize:$00010000
  601. ),
  602. // ct_lm3s1960,
  603. (
  604. controllertypestr:'LM3S1960';
  605. controllerunitstr:'LM3FURY';
  606. interruptvectors:72;
  607. flashbase:$00000000;
  608. flashsize:$00040000;
  609. srambase:$20000000;
  610. sramsize:$00010000
  611. ),
  612. // ct_lm3s1968,
  613. (
  614. controllertypestr:'LM3S1968';
  615. controllerunitstr:'LM3FURY';
  616. interruptvectors:72;
  617. flashbase:$00000000;
  618. flashsize:$00040000;
  619. srambase:$20000000;
  620. sramsize:$00010000
  621. ),
  622. // ct_lm3s1969,
  623. (
  624. controllertypestr:'LM3S1969';
  625. controllerunitstr:'LM3FURY';
  626. interruptvectors:72;
  627. flashbase:$00000000;
  628. flashsize:$00040000;
  629. srambase:$20000000;
  630. sramsize:$00010000
  631. ),
  632. // ct_lm3s2911,
  633. (
  634. controllertypestr:'LM3S2911';
  635. controllerunitstr:'LM3FURY';
  636. interruptvectors:72;
  637. flashbase:$00000000;
  638. flashsize:$00040000;
  639. srambase:$20000000;
  640. sramsize:$00010000
  641. ),
  642. // ct_lm3s2918,
  643. (
  644. controllertypestr:'LM3S2918';
  645. controllerunitstr:'LM3FURY';
  646. interruptvectors:72;
  647. flashbase:$00000000;
  648. flashsize:$00040000;
  649. srambase:$20000000;
  650. sramsize:$00010000
  651. ),
  652. // ct_lm3s2919,
  653. (
  654. controllertypestr:'LM3S2919';
  655. controllerunitstr:'LM3FURY';
  656. interruptvectors:72;
  657. flashbase:$00000000;
  658. flashsize:$00040000;
  659. srambase:$20000000;
  660. sramsize:$00010000
  661. ),
  662. // ct_lm3s2939,
  663. (
  664. controllertypestr:'LM3S2939';
  665. controllerunitstr:'LM3FURY';
  666. interruptvectors:72;
  667. flashbase:$00000000;
  668. flashsize:$00040000;
  669. srambase:$20000000;
  670. sramsize:$00010000
  671. ),
  672. // ct_lm3s2948,
  673. (
  674. controllertypestr:'LM3S2948';
  675. controllerunitstr:'LM3FURY';
  676. interruptvectors:72;
  677. flashbase:$00000000;
  678. flashsize:$00040000;
  679. srambase:$20000000;
  680. sramsize:$00010000
  681. ),
  682. // ct_lm3s2950,
  683. (
  684. controllertypestr:'LM3S2950';
  685. controllerunitstr:'LM3FURY';
  686. interruptvectors:72;
  687. flashbase:$00000000;
  688. flashsize:$00040000;
  689. srambase:$20000000;
  690. sramsize:$00010000
  691. ),
  692. // ct_lm3s2965,
  693. (
  694. controllertypestr:'LM3S2965';
  695. controllerunitstr:'LM3FURY';
  696. interruptvectors:72;
  697. flashbase:$00000000;
  698. flashsize:$00040000;
  699. srambase:$20000000;
  700. sramsize:$00010000
  701. ),
  702. // ct_lm3s6911,
  703. (
  704. controllertypestr:'LM3S6911';
  705. controllerunitstr:'LM3FURY';
  706. interruptvectors:72;
  707. flashbase:$00000000;
  708. flashsize:$00040000;
  709. srambase:$20000000;
  710. sramsize:$00010000
  711. ),
  712. // ct_lm3s6918,
  713. (
  714. controllertypestr:'LM3S6918';
  715. controllerunitstr:'LM3FURY';
  716. interruptvectors:72;
  717. flashbase:$00000000;
  718. flashsize:$00040000;
  719. srambase:$20000000;
  720. sramsize:$00010000
  721. ),
  722. // ct_lm3s6938,
  723. (
  724. controllertypestr:'LM3S6938';
  725. controllerunitstr:'LM3FURY';
  726. interruptvectors:72;
  727. flashbase:$00000000;
  728. flashsize:$00040000;
  729. srambase:$20000000;
  730. sramsize:$00010000
  731. ),
  732. // ct_lm3s6950,
  733. (
  734. controllertypestr:'LM3S6950';
  735. controllerunitstr:'LM3FURY';
  736. interruptvectors:72;
  737. flashbase:$00000000;
  738. flashsize:$00040000;
  739. srambase:$20000000;
  740. sramsize:$00010000
  741. ),
  742. // ct_lm3s6952,
  743. (
  744. controllertypestr:'LM3S6952';
  745. controllerunitstr:'LM3FURY';
  746. interruptvectors:72;
  747. flashbase:$00000000;
  748. flashsize:$00040000;
  749. srambase:$20000000;
  750. sramsize:$00010000
  751. ),
  752. // ct_lm3s6965,
  753. (
  754. controllertypestr:'LM3S6965';
  755. controllerunitstr:'LM3FURY';
  756. interruptvectors:72;
  757. flashbase:$00000000;
  758. flashsize:$00040000;
  759. srambase:$20000000;
  760. sramsize:$00010000
  761. ),
  762. // ct_lm3s8930,
  763. (
  764. controllertypestr:'LM3S8930';
  765. controllerunitstr:'LM3FURY';
  766. interruptvectors:72;
  767. flashbase:$00000000;
  768. flashsize:$00040000;
  769. srambase:$20000000;
  770. sramsize:$00010000
  771. ),
  772. // ct_lm3s8933,
  773. (
  774. controllertypestr:'LM3S8933';
  775. controllerunitstr:'LM3FURY';
  776. interruptvectors:72;
  777. flashbase:$00000000;
  778. flashsize:$00040000;
  779. srambase:$20000000;
  780. sramsize:$00010000
  781. ),
  782. // ct_lm3s8938,
  783. (
  784. controllertypestr:'LM3S8938';
  785. controllerunitstr:'LM3FURY';
  786. interruptvectors:72;
  787. flashbase:$00000000;
  788. flashsize:$00040000;
  789. srambase:$20000000;
  790. sramsize:$00010000
  791. ),
  792. // ct_lm3s8962,
  793. (
  794. controllertypestr:'LM3S8962';
  795. controllerunitstr:'LM3FURY';
  796. interruptvectors:72;
  797. flashbase:$00000000;
  798. flashsize:$00040000;
  799. srambase:$20000000;
  800. sramsize:$00010000
  801. ),
  802. // ct_lm3s8970,
  803. (
  804. controllertypestr:'LM3S8970';
  805. controllerunitstr:'LM3FURY';
  806. interruptvectors:72;
  807. flashbase:$00000000;
  808. flashsize:$00040000;
  809. srambase:$20000000;
  810. sramsize:$00010000
  811. ),
  812. // ct_lm3s8971,
  813. (
  814. controllertypestr:'LM3S8971';
  815. controllerunitstr:'LM3FURY';
  816. interruptvectors:72;
  817. flashbase:$00000000;
  818. flashsize:$00040000;
  819. srambase:$20000000;
  820. sramsize:$00010000
  821. ),
  822. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  823. // ct_lm3s5951,
  824. (
  825. controllertypestr:'LM3S5951';
  826. controllerunitstr:'LM3TEMPEST';
  827. interruptvectors:72;
  828. flashbase:$00000000;
  829. flashsize:$00040000;
  830. srambase:$20000000;
  831. sramsize:$00010000
  832. ),
  833. // ct_lm3s5956,
  834. (
  835. controllertypestr:'LM3S5956';
  836. controllerunitstr:'LM3TEMPEST';
  837. interruptvectors:72;
  838. flashbase:$00000000;
  839. flashsize:$00040000;
  840. srambase:$20000000;
  841. sramsize:$00010000
  842. ),
  843. // ct_lm3s1b21,
  844. (
  845. controllertypestr:'LM3S1B21';
  846. controllerunitstr:'LM3TEMPEST';
  847. interruptvectors:72;
  848. flashbase:$00000000;
  849. flashsize:$00040000;
  850. srambase:$20000000;
  851. sramsize:$00010000
  852. ),
  853. // ct_lm3s2b93,
  854. (
  855. controllertypestr:'LM3S2B93';
  856. controllerunitstr:'LM3TEMPEST';
  857. interruptvectors:72;
  858. flashbase:$00000000;
  859. flashsize:$00040000;
  860. srambase:$20000000;
  861. sramsize:$00010000
  862. ),
  863. // ct_lm3s5b91,
  864. (
  865. controllertypestr:'LM3S5B91';
  866. controllerunitstr:'LM3TEMPEST';
  867. interruptvectors:72;
  868. flashbase:$00000000;
  869. flashsize:$00040000;
  870. srambase:$20000000;
  871. sramsize:$00010000
  872. ),
  873. // ct_lm3s9b81,
  874. (
  875. controllertypestr:'LM3S9B81';
  876. controllerunitstr:'LM3TEMPEST';
  877. interruptvectors:72;
  878. flashbase:$00000000;
  879. flashsize:$00040000;
  880. srambase:$20000000;
  881. sramsize:$00010000
  882. ),
  883. // ct_lm3s9b90,
  884. (
  885. controllertypestr:'LM3S9B90';
  886. controllerunitstr:'LM3TEMPEST';
  887. interruptvectors:72;
  888. flashbase:$00000000;
  889. flashsize:$00040000;
  890. srambase:$20000000;
  891. sramsize:$00010000
  892. ),
  893. // ct_lm3s9b92,
  894. (
  895. controllertypestr:'LM3S9B92';
  896. controllerunitstr:'LM3TEMPEST';
  897. interruptvectors:72;
  898. flashbase:$00000000;
  899. flashsize:$00040000;
  900. srambase:$20000000;
  901. sramsize:$00010000
  902. ),
  903. // ct_lm3s9b95,
  904. (
  905. controllertypestr:'LM3S9B95';
  906. controllerunitstr:'LM3TEMPEST';
  907. interruptvectors:72;
  908. flashbase:$00000000;
  909. flashsize:$00040000;
  910. srambase:$20000000;
  911. sramsize:$00010000
  912. ),
  913. // ct_lm3s9b96,
  914. (
  915. controllertypestr:'LM3S9B96';
  916. controllerunitstr:'LM3TEMPEST';
  917. interruptvectors:72;
  918. flashbase:$00000000;
  919. flashsize:$00040000;
  920. srambase:$20000000;
  921. sramsize:$00010000
  922. ),
  923. // bare bones Thumb2
  924. (
  925. controllertypestr:'THUMB2_BARE';
  926. controllerunitstr:'THUMB2_BARE';
  927. interruptvectors:128;
  928. flashbase:$00000000;
  929. flashsize:$00100000;
  930. srambase:$20000000;
  931. sramsize:$00100000
  932. )
  933. );
  934. vfp_scalar = [fpu_vfpv2,fpu_vfpv3];
  935. { Supported optimizations, only used for information }
  936. supported_optimizerswitches = genericlevel1optimizerswitches+
  937. genericlevel2optimizerswitches+
  938. genericlevel3optimizerswitches-
  939. { no need to write info about those }
  940. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  941. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  942. cs_opt_stackframe,cs_opt_nodecse];
  943. level1optimizerswitches = genericlevel1optimizerswitches;
  944. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  945. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  946. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  947. Implementation
  948. end.