popt386.pas 98 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. Interface
  20. Uses Aasm;
  21. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  22. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  23. Implementation
  24. Uses
  25. globtype,systems,
  26. globals,verbose,hcodegen,
  27. {$ifdef finaldestdebug}
  28. cobjects,
  29. {$endif finaldestdebug}
  30. cpubase,cpuasm,DAOpt386,tgeni386;
  31. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  32. Begin
  33. reg := reg32(reg);
  34. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  35. RegUsedAfterInstruction :=
  36. (Reg in UsedRegs) and
  37. (not(getNextInstruction(p,p)) or
  38. not(regLoadedWithNewValue(reg,false,p)));
  39. End;
  40. function doFpuLoadStoreOpt(asmL: paasmoutput; var p: pai): boolean;
  41. { returns true if a "continue" should be done after this optimization }
  42. var hp1, hp2: pai;
  43. begin
  44. doFpuLoadStoreOpt := false;
  45. if (paicpu(p)^.oper[0].typ = top_ref) and
  46. getNextInstruction(p, hp1) and
  47. (hp1^.typ = ait_instruction) and
  48. (((paicpu(hp1)^.opcode = A_FLD) and
  49. (paicpu(p)^.opcode = A_FSTP)) or
  50. ((paicpu(p)^.opcode = A_FISTP) and
  51. (paicpu(hp1)^.opcode = A_FILD))) and
  52. (paicpu(hp1)^.oper[0].typ = top_ref) and
  53. (paicpu(hp1)^.opsize = Paicpu(p)^.opsize) and
  54. refsEqual(paicpu(p)^.oper[0].ref^, paicpu(hp1)^.oper[0].ref^) then
  55. begin
  56. if getNextInstruction(hp1, hp2) and
  57. (hp2^.typ = ait_instruction) and
  58. ((paicpu(hp2)^.opcode = A_LEAVE) or
  59. (paicpu(hp2)^.opcode = A_RET)) and
  60. (paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) and
  61. (paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) and
  62. (paicpu(p)^.oper[0].ref^.Index = R_NO) then
  63. begin
  64. asmL^.remove(p);
  65. asmL^.remove(hp1);
  66. dispose(p, done);
  67. dispose(hp1, done);
  68. p := hp2;
  69. removeLastDeallocForFuncRes(asmL, p);
  70. doFPULoadStoreOpt := true;
  71. end
  72. else
  73. { fst can't store an extended value! }
  74. if (paicpu(p)^.opsize <> S_FX) and
  75. (paicpu(p)^.opsize <> S_IQ) then
  76. begin
  77. if (paicpu(p)^.opcode = A_FSTP) then
  78. paicpu(p)^.opcode := A_FST
  79. else Paicpu(p)^.opcode := A_FIST;
  80. asmL^.remove(hp1);
  81. dispose(hp1, done)
  82. end
  83. end;
  84. end;
  85. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  86. {First pass of peepholeoptimizations}
  87. Var
  88. l : longint;
  89. p,hp1,hp2 : pai;
  90. hp3,hp4: pai;
  91. TmpRef: TReference;
  92. UsedRegs, TmpUsedRegs: TRegSet;
  93. TmpBool1, TmpBool2: Boolean;
  94. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  95. {skips all labels and returns the next "real" instruction}
  96. Begin
  97. While assigned(hp^.next) and
  98. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  99. hp := pai(hp^.next);
  100. If assigned(hp^.next) Then
  101. Begin
  102. SkipLabels := True;
  103. hp2 := pai(hp^.next)
  104. End
  105. Else
  106. Begin
  107. hp2 := hp;
  108. SkipLabels := False
  109. End;
  110. End;
  111. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  112. {traces sucessive jumps to their final destination and sets it, e.g.
  113. je l1 je l3
  114. <code> <code>
  115. l1: becomes l1:
  116. je l2 je l3
  117. <code> <code>
  118. l2: l2:
  119. jmp l3 jmp l3}
  120. Var p1, p2: pai;
  121. l: pasmlabel;
  122. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  123. Begin
  124. FindAnyLabel := false;
  125. While assigned(hp^.next) and
  126. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  127. hp := pai(hp^.next);
  128. If assigned(hp^.next) and
  129. (pai(hp^.next)^.typ = ait_label) Then
  130. Begin
  131. FindAnyLabel := true;
  132. l := pai_label(hp^.next)^.l;
  133. End
  134. End;
  135. Begin
  136. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  137. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  138. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  139. Begin
  140. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  141. SkipLabels(p1,p1);
  142. If (pai(p1)^.typ = ait_instruction) and
  143. (paicpu(p1)^.is_jmp) Then
  144. If { the next instruction after the label where the jump hp arrives}
  145. { is unconditional or of the same type as hp, so continue }
  146. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  147. { the next instruction after the label where the jump hp arrives}
  148. { is the opposite of hp (so this one is never taken), but after }
  149. { that one there is a branch that will be taken, so perform a }
  150. { little hack: set p1 equal to this instruction (that's what the}
  151. { last SkipLabels is for, only works with short bool evaluation)}
  152. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  153. SkipLabels(p1,p2) and
  154. (p2^.typ = ait_instruction) and
  155. (paicpu(p2)^.is_jmp) and
  156. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  157. SkipLabels(p1,p1)) Then
  158. Begin
  159. GetFinalDestination(asml, paicpu(p1));
  160. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  161. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  162. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  163. End
  164. Else
  165. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  166. if not FindAnyLabel(p1,l) then
  167. begin
  168. {$ifdef finaldestdebug}
  169. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  170. strpnew('previous label inserted'))));
  171. {$endif finaldestdebug}
  172. getlabel(l);
  173. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  174. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  175. hp^.oper[0].sym := l;
  176. inc(l^.refs);
  177. { this won't work, since the new label isn't in the labeltable }
  178. { so it will fail the rangecheck. Labeltable should become a }
  179. { hashtable to support this: }
  180. { GetFinalDestination(asml, hp); }
  181. end
  182. else
  183. begin
  184. {$ifdef finaldestdebug}
  185. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  186. strpnew('next label reused'))));
  187. {$endif finaldestdebug}
  188. inc(l^.refs);
  189. hp^.oper[0].sym := l;
  190. GetFinalDestination(asml, hp);
  191. end;
  192. End;
  193. End;
  194. Function DoSubAddOpt(var p: Pai): Boolean;
  195. Begin
  196. DoSubAddOpt := False;
  197. If GetLastInstruction(p, hp1) And
  198. (hp1^.typ = ait_instruction) And
  199. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  200. Case Paicpu(hp1)^.opcode Of
  201. A_DEC:
  202. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  203. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  204. Begin
  205. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  206. AsmL^.Remove(hp1);
  207. Dispose(hp1, Done)
  208. End;
  209. A_SUB:
  210. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  211. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  212. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  213. Begin
  214. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  215. AsmL^.Remove(hp1);
  216. Dispose(hp1, Done)
  217. End;
  218. A_ADD:
  219. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  220. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  221. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  222. Begin
  223. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  224. AsmL^.Remove(hp1);
  225. Dispose(hp1, Done);
  226. If (Paicpu(p)^.oper[0].val = 0) Then
  227. Begin
  228. hp1 := Pai(p^.next);
  229. AsmL^.Remove(p);
  230. Dispose(p, Done);
  231. If Not GetLastInstruction(hp1, p) Then
  232. p := hp1;
  233. DoSubAddOpt := True;
  234. End
  235. End;
  236. End;
  237. End;
  238. Begin
  239. P := BlockStart;
  240. UsedRegs := [];
  241. While (P <> BlockEnd) Do
  242. Begin
  243. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  244. Case P^.Typ Of
  245. ait_instruction:
  246. Begin
  247. { Handle Jmp Optimizations }
  248. if Paicpu(p)^.is_jmp then
  249. begin
  250. {the following if-block removes all code between a jmp and the next label,
  251. because it can never be executed}
  252. If (paicpu(p)^.opcode = A_JMP) Then
  253. Begin
  254. While GetNextInstruction(p, hp1) and
  255. ((hp1^.typ <> ait_label) or
  256. { skip unused labels, they're not referenced anywhere }
  257. labelCanBeSkipped(pai_label(hp1))) Do
  258. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  259. Begin
  260. AsmL^.Remove(hp1);
  261. Dispose(hp1, done);
  262. End;
  263. End;
  264. If GetNextInstruction(p, hp1) then
  265. Begin
  266. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  267. Begin
  268. hp2:=pai(hp1^.next);
  269. asml^.remove(p);
  270. dispose(p,done);
  271. p:=hp2;
  272. continue;
  273. end
  274. Else
  275. Begin
  276. if hp1^.typ = ait_label then
  277. SkipLabels(hp1,hp1);
  278. If (pai(hp1)^.typ=ait_instruction) and
  279. (paicpu(hp1)^.opcode=A_JMP) and
  280. GetNextInstruction(hp1, hp2) And
  281. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  282. Then
  283. Begin
  284. if paicpu(p)^.opcode=A_Jcc then
  285. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  286. else
  287. begin
  288. If (LabDif <> 0) Then
  289. GetFinalDestination(asml, paicpu(p));
  290. p:=pai(p^.next);
  291. continue;
  292. end;
  293. Dec(pai_label(hp2)^.l^.refs);
  294. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  295. Inc(paicpu(p)^.oper[0].sym^.refs);
  296. asml^.remove(hp1);
  297. dispose(hp1,done);
  298. If (LabDif <> 0) Then
  299. GetFinalDestination(asml, paicpu(p));
  300. end
  301. else
  302. If (LabDif <> 0) Then
  303. GetFinalDestination(asml, paicpu(p));
  304. end;
  305. end;
  306. end
  307. else
  308. { All other optimizes }
  309. begin
  310. For l := 0 to 2 Do
  311. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  312. With Paicpu(p)^.oper[l].ref^ Do
  313. Begin
  314. If (base = R_NO) And
  315. (index <> R_NO) And
  316. (scalefactor in [0,1])
  317. Then
  318. Begin
  319. base := index;
  320. index := R_NO
  321. End
  322. End;
  323. Case Paicpu(p)^.opcode Of
  324. A_AND:
  325. Begin
  326. If (Paicpu(p)^.oper[0].typ = top_const) And
  327. (Paicpu(p)^.oper[1].typ = top_reg) And
  328. GetNextInstruction(p, hp1) And
  329. (Pai(hp1)^.typ = ait_instruction) And
  330. (Paicpu(hp1)^.opcode = A_AND) And
  331. (Paicpu(hp1)^.oper[0].typ = top_const) And
  332. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  333. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  334. Then
  335. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  336. Begin
  337. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  338. AsmL^.Remove(hp1);
  339. Dispose(hp1, Done)
  340. End
  341. Else
  342. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  343. jump, but only if it's a conditional jump (PFV) }
  344. If (Paicpu(p)^.oper[1].typ = top_reg) And
  345. GetNextInstruction(p, hp1) And
  346. (hp1^.typ = ait_instruction) And
  347. (Paicpu(hp1)^.is_jmp) and
  348. (Paicpu(hp1)^.opcode<>A_JMP) and
  349. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  350. Paicpu(p)^.opcode := A_TEST;
  351. End;
  352. A_CMP:
  353. Begin
  354. If (Paicpu(p)^.oper[0].typ = top_const) And
  355. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  356. (Paicpu(p)^.oper[0].val = 0) Then
  357. If GetNextInstruction(p, hp1) And
  358. (hp1^.typ = ait_instruction) And
  359. (Paicpu(hp1)^.is_jmp) and
  360. (paicpu(hp1)^.opcode=A_Jcc) and
  361. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  362. GetNextInstruction(hp1,hp2) and
  363. (hp2^.typ = ait_instruction) and
  364. (Paicpu(hp2)^.opcode = A_DEC) And
  365. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  366. GetNextInstruction(hp2, hp3) And
  367. (hp3^.typ = ait_instruction) and
  368. (Paicpu(hp3)^.is_jmp) and
  369. (Paicpu(hp3)^.opcode = A_JMP) And
  370. GetNextInstruction(hp3, hp4) And
  371. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  372. Then
  373. Begin
  374. Paicpu(hp2)^.Opcode := A_SUB;
  375. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  376. Paicpu(hp2)^.LoadConst(0,1);
  377. Paicpu(hp2)^.ops:=2;
  378. Paicpu(hp3)^.Opcode := A_Jcc;
  379. Case paicpu(hp1)^.condition of
  380. C_LE: Paicpu(hp3)^.condition := C_GE;
  381. C_BE: Paicpu(hp3)^.condition := C_AE;
  382. End;
  383. AsmL^.Remove(p);
  384. AsmL^.Remove(hp1);
  385. Dispose(p, Done);
  386. Dispose(hp1, Done);
  387. p := hp2;
  388. continue;
  389. End
  390. Else
  391. {change "cmp $0, %reg" to "test %reg, %reg"}
  392. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  393. Begin
  394. Paicpu(p)^.opcode := A_TEST;
  395. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  396. End;
  397. End;
  398. A_FLD:
  399. Begin
  400. If (Paicpu(p)^.oper[0].typ = top_reg) And
  401. GetNextInstruction(p, hp1) And
  402. (hp1^.typ = Ait_Instruction) And
  403. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  404. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  405. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  406. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  407. { change to
  408. fld reg fxxx reg,st
  409. fxxxp st, st1 (hp1)
  410. Remark: non commutative operations must be reversed!
  411. }
  412. begin
  413. Case Paicpu(hp1)^.opcode Of
  414. A_FMULP,A_FADDP,
  415. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  416. begin
  417. Case Paicpu(hp1)^.opcode Of
  418. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  419. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  420. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  421. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  422. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  423. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  424. End;
  425. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  426. Paicpu(hp1)^.oper[1].reg := R_ST;
  427. AsmL^.Remove(p);
  428. Dispose(p, Done);
  429. p := hp1;
  430. Continue;
  431. end;
  432. end;
  433. end
  434. else
  435. If (Paicpu(p)^.oper[0].typ = top_ref) And
  436. GetNextInstruction(p, hp2) And
  437. (hp2^.typ = Ait_Instruction) And
  438. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  439. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  440. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  441. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  442. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  443. If GetLastInstruction(p, hp1) And
  444. (hp1^.typ = Ait_Instruction) And
  445. ((Paicpu(hp1)^.opcode = A_FLD) Or
  446. (Paicpu(hp1)^.opcode = A_FST)) And
  447. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  448. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  449. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  450. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  451. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  452. { change to
  453. fld/fst mem1 (hp1) fld/fst mem1
  454. fld mem1 (p) fadd/
  455. faddp/ fmul st, st
  456. fmulp st, st1 (hp2) }
  457. Begin
  458. AsmL^.Remove(p);
  459. Dispose(p, Done);
  460. p := hp1;
  461. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  462. Paicpu(hp2)^.opcode := A_FADD
  463. Else
  464. Paicpu(hp2)^.opcode := A_FMUL;
  465. Paicpu(hp2)^.oper[1].reg := R_ST;
  466. End
  467. Else
  468. { change to
  469. fld/fst mem1 (hp1) fld/fst mem1
  470. fld mem1 (p) fld st}
  471. Begin
  472. Paicpu(p)^.changeopsize(S_FL);
  473. Paicpu(p)^.loadreg(0,R_ST);
  474. End
  475. Else
  476. Begin
  477. Case Paicpu(hp2)^.opcode Of
  478. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  479. { change to
  480. fld/fst mem1 (hp1) fld/fst mem1
  481. fld mem2 (p) fxxx mem2
  482. fxxxp st, st1 (hp2) }
  483. Begin
  484. Case Paicpu(hp2)^.opcode Of
  485. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  486. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  487. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  488. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  489. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  490. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  491. End;
  492. AsmL^.Remove(hp2);
  493. Dispose(hp2, Done)
  494. End
  495. End
  496. End
  497. End;
  498. A_FSTP,A_FISTP:
  499. if doFpuLoadStoreOpt(asmL,p) then
  500. continue;
  501. A_IMUL:
  502. {changes certain "imul const, %reg"'s to lea sequences}
  503. Begin
  504. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  505. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  506. (Paicpu(p)^.opsize = S_L) Then
  507. If (Paicpu(p)^.oper[0].val = 1) Then
  508. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  509. {remove "imul $1, reg"}
  510. Begin
  511. hp1 := Pai(p^.Next);
  512. AsmL^.Remove(p);
  513. Dispose(p, Done);
  514. p := hp1;
  515. Continue;
  516. End
  517. Else
  518. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  519. Begin
  520. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  521. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  522. Dispose(p, Done);
  523. p := hp1;
  524. End
  525. Else If
  526. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  527. (Paicpu(p)^.oper[2].typ = Top_None)) And
  528. (aktoptprocessor < ClassP6) And
  529. (Paicpu(p)^.oper[0].val <= 12) And
  530. Not(CS_LittleSize in aktglobalswitches) And
  531. (Not(GetNextInstruction(p, hp1)) Or
  532. {GetNextInstruction(p, hp1) And}
  533. Not((Pai(hp1)^.typ = ait_instruction) And
  534. ((paicpu(hp1)^.opcode=A_Jcc) and
  535. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  536. Then
  537. Begin
  538. Reset_reference(tmpref);
  539. Case Paicpu(p)^.oper[0].val Of
  540. 3: Begin
  541. {imul 3, reg1, reg2 to
  542. lea (reg1,reg1,2), reg2
  543. imul 3, reg1 to
  544. lea (reg1,reg1,2), reg1}
  545. TmpRef.base := Paicpu(p)^.oper[1].reg;
  546. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  547. TmpRef.ScaleFactor := 2;
  548. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  549. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  550. Else
  551. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  552. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  553. Dispose(p, Done);
  554. p := hp1;
  555. End;
  556. 5: Begin
  557. {imul 5, reg1, reg2 to
  558. lea (reg1,reg1,4), reg2
  559. imul 5, reg1 to
  560. lea (reg1,reg1,4), reg1}
  561. TmpRef.base := Paicpu(p)^.oper[1].reg;
  562. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  563. TmpRef.ScaleFactor := 4;
  564. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  565. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  566. Else
  567. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  568. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  569. Dispose(p, Done);
  570. p := hp1;
  571. End;
  572. 6: Begin
  573. {imul 6, reg1, reg2 to
  574. lea (,reg1,2), reg2
  575. lea (reg2,reg1,4), reg2
  576. imul 6, reg1 to
  577. lea (reg1,reg1,2), reg1
  578. add reg1, reg1}
  579. If (aktoptprocessor <= Class386)
  580. Then
  581. Begin
  582. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  583. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  584. Then
  585. Begin
  586. TmpRef.base := Paicpu(p)^.oper[2].reg;
  587. TmpRef.ScaleFactor := 4;
  588. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  589. End
  590. Else
  591. Begin
  592. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  593. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  594. End;
  595. InsertLLItem(AsmL,p, p^.next, hp1);
  596. Reset_reference(tmpref);
  597. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  598. TmpRef.ScaleFactor := 2;
  599. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  600. Then
  601. Begin
  602. TmpRef.base := R_NO;
  603. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  604. Paicpu(p)^.oper[2].reg));
  605. End
  606. Else
  607. Begin
  608. TmpRef.base := Paicpu(p)^.oper[1].reg;
  609. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  610. End;
  611. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  612. Dispose(p, Done);
  613. p := Pai(hp1^.next);
  614. End
  615. End;
  616. 9: Begin
  617. {imul 9, reg1, reg2 to
  618. lea (reg1,reg1,8), reg2
  619. imul 9, reg1 to
  620. lea (reg1,reg1,8), reg1}
  621. TmpRef.base := Paicpu(p)^.oper[1].reg;
  622. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  623. TmpRef.ScaleFactor := 8;
  624. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  625. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  626. Else
  627. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  628. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  629. Dispose(p, Done);
  630. p := hp1;
  631. End;
  632. 10: Begin
  633. {imul 10, reg1, reg2 to
  634. lea (reg1,reg1,4), reg2
  635. add reg2, reg2
  636. imul 10, reg1 to
  637. lea (reg1,reg1,4), reg1
  638. add reg1, reg1}
  639. If (aktoptprocessor <= Class386) Then
  640. Begin
  641. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  642. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  643. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  644. Else
  645. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  646. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  647. InsertLLItem(AsmL,p, p^.next, hp1);
  648. TmpRef.base := Paicpu(p)^.oper[1].reg;
  649. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  650. TmpRef.ScaleFactor := 4;
  651. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  652. Then
  653. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  654. Else
  655. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  656. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  657. Dispose(p, Done);
  658. p := Pai(hp1^.next);
  659. End
  660. End;
  661. 12: Begin
  662. {imul 12, reg1, reg2 to
  663. lea (,reg1,4), reg2
  664. lea (,reg1,8) reg2
  665. imul 12, reg1 to
  666. lea (reg1,reg1,2), reg1
  667. lea (,reg1,4), reg1}
  668. If (aktoptprocessor <= Class386)
  669. Then
  670. Begin
  671. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  672. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  673. Begin
  674. TmpRef.base := Paicpu(p)^.oper[2].reg;
  675. TmpRef.ScaleFactor := 8;
  676. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  677. End
  678. Else
  679. Begin
  680. TmpRef.base := R_NO;
  681. TmpRef.ScaleFactor := 4;
  682. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  683. End;
  684. InsertLLItem(AsmL,p, p^.next, hp1);
  685. Reset_reference(tmpref);
  686. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  687. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  688. Begin
  689. TmpRef.base := R_NO;
  690. TmpRef.ScaleFactor := 4;
  691. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  692. End
  693. Else
  694. Begin
  695. TmpRef.base := Paicpu(p)^.oper[1].reg;
  696. TmpRef.ScaleFactor := 2;
  697. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  698. End;
  699. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  700. Dispose(p, Done);
  701. p := Pai(hp1^.next);
  702. End
  703. End
  704. End;
  705. End;
  706. End;
  707. A_LEA:
  708. Begin
  709. {removes seg register prefixes from LEA operations, as they
  710. don't do anything}
  711. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  712. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  713. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  714. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  715. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  716. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  717. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  718. Then
  719. Begin
  720. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  721. Paicpu(p)^.oper[1].reg));
  722. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  723. Dispose(p, Done);
  724. p := hp1;
  725. Continue;
  726. End
  727. Else
  728. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  729. Begin
  730. hp1 := Pai(p^.Next);
  731. AsmL^.Remove(p);
  732. Dispose(p, Done);
  733. p := hp1;
  734. Continue;
  735. End
  736. else
  737. with Paicpu(p)^.oper[0].ref^ do
  738. if (Base = Paicpu(p)^.oper[1].reg) then
  739. begin
  740. l := offset+offsetfixup;
  741. case l of
  742. 1,-1:
  743. begin
  744. if l = 1 then
  745. paicpu(p)^.opcode := A_INC
  746. else paicpu(p)^.opcode := A_DEC;
  747. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  748. paicpu(p)^.ops := 1;
  749. end;
  750. else
  751. begin
  752. paicpu(p)^.opcode := A_ADD;
  753. paicpu(p)^.loadconst(0,offset+offsetfixup);
  754. end;
  755. end;
  756. end;
  757. End;
  758. A_MOV:
  759. Begin
  760. TmpUsedRegs := UsedRegs;
  761. If (Paicpu(p)^.oper[1].typ = top_reg) And
  762. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  763. GetNextInstruction(p, hp1) And
  764. (Pai(hp1)^.typ = ait_instruction) And
  765. (Paicpu(hp1)^.opcode = A_MOV) And
  766. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  767. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  768. Then
  769. {we have "mov x, %treg; mov %treg, y}
  770. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  771. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  772. Case Paicpu(p)^.oper[0].typ Of
  773. top_reg:
  774. Begin
  775. { change "mov %reg, %treg; mov %treg, y"
  776. to "mov %reg, y" }
  777. Paicpu(p)^.LoadOper(1,Paicpu(hp1)^.oper[1]);
  778. AsmL^.Remove(hp1);
  779. Dispose(hp1, Done);
  780. continue;
  781. End;
  782. top_ref:
  783. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  784. Begin
  785. { change "mov mem, %treg; mov %treg, %reg"
  786. to "mov mem, %reg" }
  787. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  788. AsmL^.Remove(hp1);
  789. Dispose(hp1, Done);
  790. continue;
  791. End;
  792. End
  793. Else
  794. Else
  795. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  796. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  797. penalty}
  798. If (Paicpu(p)^.oper[0].typ = top_reg) And
  799. (Paicpu(p)^.oper[1].typ = top_reg) And
  800. GetNextInstruction(p,hp1) And
  801. (Pai(hp1)^.typ = ait_instruction) And
  802. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  803. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  804. Then
  805. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  806. Begin
  807. If ((Paicpu(hp1)^.opcode = A_OR) Or
  808. (Paicpu(hp1)^.opcode = A_TEST)) And
  809. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  810. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  811. Then
  812. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  813. Begin
  814. TmpUsedRegs := UsedRegs;
  815. { reg1 will be used after the first instruction, }
  816. { so update the allocation info }
  817. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  818. If GetNextInstruction(hp1, hp2) And
  819. (hp2^.typ = ait_instruction) And
  820. paicpu(hp2)^.is_jmp and
  821. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  822. Then
  823. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  824. "test %reg1, %reg1; jxx"}
  825. Begin
  826. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  827. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  828. AsmL^.Remove(p);
  829. Dispose(p, done);
  830. p := hp1;
  831. continue
  832. End
  833. Else
  834. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  835. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  836. Begin
  837. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  838. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  839. End;
  840. End
  841. { Else
  842. If (Paicpu(p^.next)^.opcode
  843. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  844. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  845. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  846. End
  847. Else
  848. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  849. x >= RetOffset) as it doesn't do anything (it writes either to a
  850. parameter or to the temporary storage room for the function
  851. result)}
  852. If GetNextInstruction(p, hp1) And
  853. (Pai(hp1)^.typ = ait_instruction)
  854. Then
  855. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  856. (Paicpu(hp1)^.opcode = A_RET)) And
  857. (Paicpu(p)^.oper[1].typ = top_ref) And
  858. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  859. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  860. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  861. (Paicpu(p)^.oper[0].typ = top_reg)
  862. Then
  863. Begin
  864. AsmL^.Remove(p);
  865. Dispose(p, done);
  866. p := hp1;
  867. RemoveLastDeallocForFuncRes(asmL,p);
  868. End
  869. Else
  870. If (Paicpu(p)^.oper[0].typ = top_reg) And
  871. (Paicpu(p)^.oper[1].typ = top_ref) And
  872. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  873. (Paicpu(hp1)^.opcode = A_CMP) And
  874. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  875. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  876. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  877. begin
  878. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  879. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  880. end;
  881. { Next instruction is also a MOV ? }
  882. If GetNextInstruction(p, hp1) And
  883. (pai(hp1)^.typ = ait_instruction) and
  884. (Paicpu(hp1)^.opcode = A_MOV) and
  885. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  886. Then
  887. Begin
  888. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  889. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  890. Then
  891. {mov reg1, mem1 or mov mem1, reg1
  892. mov mem2, reg2 mov reg2, mem2}
  893. Begin
  894. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  895. {mov reg1, mem1 or mov mem1, reg1
  896. mov mem2, reg1 mov reg2, mem1}
  897. Begin
  898. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  899. { Removes the second statement from
  900. mov reg1, mem1/reg2
  901. mov mem1/reg2, reg1 }
  902. Begin
  903. if (paicpu(p)^.oper[0].typ = top_reg) then
  904. AllocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  905. AsmL^.remove(hp1);
  906. Dispose(hp1,done);
  907. End
  908. Else
  909. Begin
  910. TmpUsedRegs := UsedRegs;
  911. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  912. If (Paicpu(p)^.oper[0].typ = top_reg) And
  913. { mov reg1, mem1
  914. mov mem2, reg1 }
  915. GetNextInstruction(hp1, hp2) And
  916. (hp2^.typ = ait_instruction) And
  917. (Paicpu(hp2)^.opcode = A_CMP) And
  918. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  919. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  920. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  921. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  922. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  923. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  924. { change to
  925. mov reg1, mem1 mov reg1, mem1
  926. mov mem2, reg1 cmp reg1, mem2
  927. cmp mem1, reg1 }
  928. Begin
  929. AsmL^.Remove(hp2);
  930. Dispose(hp2, Done);
  931. Paicpu(hp1)^.opcode := A_CMP;
  932. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  933. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  934. End;
  935. End;
  936. End
  937. Else
  938. Begin
  939. tmpUsedRegs := UsedRegs;
  940. If GetNextInstruction(hp1, hp2) And
  941. (Paicpu(p)^.oper[0].typ = top_ref) And
  942. (Paicpu(p)^.oper[1].typ = top_reg) And
  943. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  944. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  945. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  946. (Pai(hp2)^.typ = ait_instruction) And
  947. (Paicpu(hp2)^.opcode = A_MOV) And
  948. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  949. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  950. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  951. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  952. If not regInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^) and
  953. (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  954. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  955. { mov mem1, %edi
  956. mov %edi, mem2
  957. mov mem2, reg2
  958. to:
  959. mov mem1, reg2
  960. mov reg2, mem2}
  961. Begin
  962. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  963. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  964. AsmL^.Remove(hp2);
  965. Dispose(hp2,Done);
  966. End
  967. Else
  968. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  969. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  970. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  971. Then
  972. { mov mem1, reg1 mov mem1, reg1
  973. mov reg1, mem2 mov reg1, mem2
  974. mov mem2, reg2 mov mem2, reg1
  975. to: to:
  976. mov mem1, reg1 mov mem1, reg1
  977. mov mem1, reg2 mov reg1, mem2
  978. mov reg1, mem2
  979. or (if mem1 depends on reg1
  980. and/or if mem2 depends on reg2)
  981. to:
  982. mov mem1, reg1
  983. mov reg1, mem2
  984. mov reg1, reg2
  985. }
  986. Begin
  987. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  988. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  989. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  990. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  991. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  992. if (paicpu(p)^.oper[0].ref^.base in (usableregs+[R_EDI])) then
  993. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.base,p,hp2);
  994. if (paicpu(p)^.oper[0].ref^.index in (usableregs+[R_EDI])) then
  995. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.index,p,hp2);
  996. End
  997. Else
  998. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  999. begin
  1000. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg);
  1001. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  1002. end
  1003. else
  1004. begin
  1005. asmL^.Remove(hp2);
  1006. dispose(hp2, done);
  1007. end
  1008. End;
  1009. End
  1010. Else
  1011. (* {movl [mem1],reg1
  1012. movl [mem1],reg2
  1013. to:
  1014. movl [mem1],reg1
  1015. movl reg1,reg2 }
  1016. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1017. (Paicpu(p)^.oper[1].typ = top_reg) and
  1018. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1019. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1020. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1021. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1022. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1023. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1024. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1025. Else*)
  1026. { movl const1,[mem1]
  1027. movl [mem1],reg1
  1028. to:
  1029. movl const1,reg1
  1030. movl reg1,[mem1] }
  1031. If (Paicpu(p)^.oper[0].typ = top_const) and
  1032. (Paicpu(p)^.oper[1].typ = top_ref) and
  1033. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1034. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1035. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1036. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1037. Begin
  1038. allocregbetween(asml,Paicpu(hp1)^.oper[1].reg,p,hp1);
  1039. { allocregbetween doesn't insert this because at }
  1040. { this time, no regalloc info is available in }
  1041. { the optinfo field, so do it manually (JM) }
  1042. hp2 := new(paiRegalloc,alloc(Paicpu(hp1)^.oper[1].reg));
  1043. insertllitem(asml,p^.previous,p,hp2);
  1044. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1045. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1046. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1047. End
  1048. End;
  1049. End;
  1050. A_MOVZX:
  1051. Begin
  1052. {removes superfluous And's after movzx's}
  1053. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1054. GetNextInstruction(p, hp1) And
  1055. (Pai(hp1)^.typ = ait_instruction) And
  1056. (Paicpu(hp1)^.opcode = A_AND) And
  1057. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1058. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1059. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1060. Then
  1061. Case Paicpu(p)^.opsize Of
  1062. S_BL, S_BW:
  1063. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1064. Begin
  1065. AsmL^.Remove(hp1);
  1066. Dispose(hp1, Done);
  1067. End;
  1068. S_WL:
  1069. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1070. Begin
  1071. AsmL^.Remove(hp1);
  1072. Dispose(hp1, Done);
  1073. End;
  1074. End;
  1075. {changes some movzx constructs to faster synonims (all examples
  1076. are given with eax/ax, but are also valid for other registers)}
  1077. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1078. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1079. Case Paicpu(p)^.opsize of
  1080. S_BW:
  1081. Begin
  1082. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1083. Not(CS_LittleSize In aktglobalswitches)
  1084. Then
  1085. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1086. Begin
  1087. Paicpu(p)^.opcode := A_AND;
  1088. Paicpu(p)^.changeopsize(S_W);
  1089. Paicpu(p)^.LoadConst(0,$ff);
  1090. End
  1091. Else
  1092. If GetNextInstruction(p, hp1) And
  1093. (Pai(hp1)^.typ = ait_instruction) And
  1094. (Paicpu(hp1)^.opcode = A_AND) And
  1095. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1096. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1097. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1098. Then
  1099. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1100. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1101. Begin
  1102. Paicpu(p)^.opcode := A_MOV;
  1103. Paicpu(p)^.changeopsize(S_W);
  1104. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1105. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1106. End;
  1107. End;
  1108. S_BL:
  1109. Begin
  1110. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1111. Not(CS_LittleSize in aktglobalswitches)
  1112. Then
  1113. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1114. Begin
  1115. Paicpu(p)^.opcode := A_AND;
  1116. Paicpu(p)^.changeopsize(S_L);
  1117. Paicpu(p)^.loadconst(0,$ff)
  1118. End
  1119. Else
  1120. If GetNextInstruction(p, hp1) And
  1121. (Pai(hp1)^.typ = ait_instruction) And
  1122. (Paicpu(hp1)^.opcode = A_AND) And
  1123. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1124. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1125. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1126. Then
  1127. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1128. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1129. Begin
  1130. Paicpu(p)^.opcode := A_MOV;
  1131. Paicpu(p)^.changeopsize(S_L);
  1132. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1133. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1134. End
  1135. End;
  1136. S_WL:
  1137. Begin
  1138. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1139. Not(CS_LittleSize In aktglobalswitches)
  1140. Then
  1141. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1142. Begin
  1143. Paicpu(p)^.opcode := A_AND;
  1144. Paicpu(p)^.changeopsize(S_L);
  1145. Paicpu(p)^.LoadConst(0,$ffff);
  1146. End
  1147. Else
  1148. If GetNextInstruction(p, hp1) And
  1149. (Pai(hp1)^.typ = ait_instruction) And
  1150. (Paicpu(hp1)^.opcode = A_AND) And
  1151. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1152. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1153. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1154. Then
  1155. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1156. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1157. Begin
  1158. Paicpu(p)^.opcode := A_MOV;
  1159. Paicpu(p)^.changeopsize(S_L);
  1160. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1161. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1162. End;
  1163. End;
  1164. End
  1165. Else
  1166. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1167. Begin
  1168. If GetNextInstruction(p, hp1) And
  1169. (Pai(hp1)^.typ = ait_instruction) And
  1170. (Paicpu(hp1)^.opcode = A_AND) And
  1171. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1172. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1173. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1174. Begin
  1175. Paicpu(p)^.opcode := A_MOV;
  1176. Case Paicpu(p)^.opsize Of
  1177. S_BL:
  1178. Begin
  1179. Paicpu(p)^.changeopsize(S_L);
  1180. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1181. End;
  1182. S_WL:
  1183. Begin
  1184. Paicpu(p)^.changeopsize(S_L);
  1185. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1186. End;
  1187. S_BW:
  1188. Begin
  1189. Paicpu(p)^.changeopsize(S_W);
  1190. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1191. End;
  1192. End;
  1193. End;
  1194. End;
  1195. End;
  1196. A_POP:
  1197. Begin
  1198. {$ifdef go32v2}
  1199. { Transform a series of pop/pop/pop/push/push/push to }
  1200. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1201. { because I'm not sure whether they can cope with }
  1202. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1203. { such a problem when using esp as frame pointer (JM) }
  1204. if (Paicpu(p)^.oper[0].typ = top_reg) then
  1205. begin
  1206. hp1 := p;
  1207. hp2 := p;
  1208. l := 0;
  1209. while getNextInstruction(hp1,hp1) and
  1210. (hp1^.typ = ait_instruction) and
  1211. (paicpu(hp1)^.opcode = A_POP) and
  1212. (paicpu(hp1)^.oper[0].typ = top_reg) do
  1213. begin
  1214. hp2 := hp1;
  1215. inc(l,4);
  1216. end;
  1217. getLastInstruction(p,hp3);
  1218. l1 := 0;
  1219. while (hp2 <> hp3) and
  1220. assigned(hp1) and
  1221. (hp1^.typ = ait_instruction) and
  1222. (paicpu(hp1)^.opcode = A_PUSH) and
  1223. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1224. (paicpu(hp1)^.oper[0].reg = paicpu(hp2)^.oper[0].reg) do
  1225. begin
  1226. { change it to a two op operation }
  1227. paicpu(hp2)^.oper[1].typ:=top_none;
  1228. paicpu(hp2)^.ops:=2;
  1229. paicpu(hp2)^.opcode := A_MOV;
  1230. paicpu(hp2)^.Loadoper(1,paicpu(hp1)^.oper[0]);
  1231. reset_reference(tmpref);
  1232. tmpRef.base := stack_pointer;
  1233. tmpRef.offset := l;
  1234. paicpu(hp2)^.loadRef(0,newReference(tmpRef));
  1235. hp4 := hp1;
  1236. getNextInstruction(hp1,hp1);
  1237. asmL^.remove(hp4);
  1238. dispose(hp4,done);
  1239. getLastInstruction(hp2,hp2);
  1240. dec(l,4);
  1241. inc(l1);
  1242. end;
  1243. if l <> -4 then
  1244. begin
  1245. inc(l,4);
  1246. for l1 := l1 downto 1 do
  1247. begin
  1248. getNextInstruction(hp2,hp2);
  1249. dec(paicpu(hp2)^.oper[0].ref^.offset,l);
  1250. end
  1251. end
  1252. end
  1253. {$else go32v2}
  1254. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1255. GetNextInstruction(p, hp1) And
  1256. (pai(hp1)^.typ=ait_instruction) and
  1257. (Paicpu(hp1)^.opcode=A_PUSH) and
  1258. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1259. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1260. Begin
  1261. { change it to a two op operation }
  1262. Paicpu(p)^.oper[1].typ:=top_none;
  1263. Paicpu(p)^.ops:=2;
  1264. Paicpu(p)^.opcode := A_MOV;
  1265. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1266. Reset_reference(tmpref);
  1267. TmpRef.base := R_ESP;
  1268. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1269. AsmL^.Remove(hp1);
  1270. Dispose(hp1, Done)
  1271. End;
  1272. {$endif go32v2}
  1273. end;
  1274. A_PUSH:
  1275. Begin
  1276. If (Paicpu(p)^.opsize = S_W) And
  1277. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1278. GetNextInstruction(p, hp1) And
  1279. (Pai(hp1)^.typ = ait_instruction) And
  1280. (Paicpu(hp1)^.opcode = A_PUSH) And
  1281. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1282. (Paicpu(hp1)^.opsize = S_W) Then
  1283. Begin
  1284. Paicpu(p)^.changeopsize(S_L);
  1285. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1286. AsmL^.Remove(hp1);
  1287. Dispose(hp1, Done)
  1288. End;
  1289. End;
  1290. A_SHL, A_SAL:
  1291. Begin
  1292. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1293. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1294. (Paicpu(p)^.opsize = S_L) And
  1295. (Paicpu(p)^.oper[0].val <= 3)
  1296. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1297. Then
  1298. Begin
  1299. TmpBool1 := True; {should we check the next instruction?}
  1300. TmpBool2 := False; {have we found an add/sub which could be
  1301. integrated in the lea?}
  1302. Reset_reference(tmpref);
  1303. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1304. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1305. While TmpBool1 And
  1306. GetNextInstruction(p, hp1) And
  1307. (Pai(hp1)^.typ = ait_instruction) And
  1308. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1309. (Paicpu(hp1)^.opcode = A_SUB)) And
  1310. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1311. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1312. Begin
  1313. TmpBool1 := False;
  1314. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1315. Then
  1316. Begin
  1317. TmpBool1 := True;
  1318. TmpBool2 := True;
  1319. If Paicpu(hp1)^.opcode = A_ADD Then
  1320. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1321. Else
  1322. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1323. AsmL^.Remove(hp1);
  1324. Dispose(hp1, Done);
  1325. End
  1326. Else
  1327. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1328. (Paicpu(hp1)^.opcode = A_ADD) And
  1329. (TmpRef.base = R_NO) Then
  1330. Begin
  1331. TmpBool1 := True;
  1332. TmpBool2 := True;
  1333. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1334. AsmL^.Remove(hp1);
  1335. Dispose(hp1, Done);
  1336. End;
  1337. End;
  1338. If TmpBool2 Or
  1339. ((aktoptprocessor < ClassP6) And
  1340. (Paicpu(p)^.oper[0].val <= 3) And
  1341. Not(CS_LittleSize in aktglobalswitches))
  1342. Then
  1343. Begin
  1344. If Not(TmpBool2) And
  1345. (Paicpu(p)^.oper[0].val = 1)
  1346. Then
  1347. Begin
  1348. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1349. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1350. End
  1351. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1352. Paicpu(p)^.oper[1].reg));
  1353. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1354. Dispose(p, Done);
  1355. p := hp1;
  1356. End;
  1357. End
  1358. Else
  1359. If (aktoptprocessor < ClassP6) And
  1360. (Paicpu(p)^.oper[0].typ = top_const) And
  1361. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1362. If (Paicpu(p)^.oper[0].val = 1)
  1363. Then
  1364. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1365. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1366. (unlike shl, which is only pairable in the U pipe)}
  1367. Begin
  1368. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1369. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1370. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1371. Dispose(p, done);
  1372. p := hp1;
  1373. End
  1374. Else If (Paicpu(p)^.opsize = S_L) and
  1375. (Paicpu(p)^.oper[0].val<= 3) Then
  1376. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1377. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1378. Begin
  1379. Reset_reference(tmpref);
  1380. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1381. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1382. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1383. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1384. Dispose(p, done);
  1385. p := hp1;
  1386. End
  1387. End;
  1388. A_SAR, A_SHR:
  1389. {changes the code sequence
  1390. shr/sar const1, x
  1391. shl const2, x
  1392. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1393. Begin
  1394. If GetNextInstruction(p, hp1) And
  1395. (pai(hp1)^.typ = ait_instruction) and
  1396. (Paicpu(hp1)^.opcode = A_SHL) and
  1397. (Paicpu(p)^.oper[0].typ = top_const) and
  1398. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1399. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1400. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1401. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1402. Then
  1403. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1404. Not(CS_LittleSize In aktglobalswitches)
  1405. Then
  1406. { shr/sar const1, %reg
  1407. shl const2, %reg
  1408. with const1 > const2 }
  1409. Begin
  1410. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1411. Paicpu(hp1)^.opcode := A_AND;
  1412. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1413. Case Paicpu(p)^.opsize Of
  1414. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1415. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1416. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1417. End;
  1418. End
  1419. Else
  1420. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1421. Not(CS_LittleSize In aktglobalswitches)
  1422. Then
  1423. { shr/sar const1, %reg
  1424. shl const2, %reg
  1425. with const1 < const2 }
  1426. Begin
  1427. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1428. Paicpu(p)^.opcode := A_AND;
  1429. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1430. Case Paicpu(p)^.opsize Of
  1431. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1432. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1433. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1434. End;
  1435. End
  1436. Else
  1437. { shr/sar const1, %reg
  1438. shl const2, %reg
  1439. with const1 = const2 }
  1440. if (Paicpu(p)^.oper[0].val = Paicpu(hp1)^.oper[0].val) then
  1441. Begin
  1442. Paicpu(p)^.opcode := A_AND;
  1443. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1444. Case Paicpu(p)^.opsize Of
  1445. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1446. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1447. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1448. End;
  1449. AsmL^.remove(hp1);
  1450. dispose(hp1, done);
  1451. End;
  1452. End;
  1453. A_SETcc :
  1454. { changes
  1455. setcc (funcres) setcc reg
  1456. movb (funcres), reg to leave/ret
  1457. leave/ret }
  1458. Begin
  1459. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1460. GetNextInstruction(p, hp1) And
  1461. GetNextInstruction(hp1, hp2) And
  1462. (hp2^.typ = ait_instruction) And
  1463. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1464. (Paicpu(hp2)^.opcode = A_RET)) And
  1465. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1466. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1467. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1468. (hp1^.typ = ait_instruction) And
  1469. (Paicpu(hp1)^.opcode = A_MOV) And
  1470. (Paicpu(hp1)^.opsize = S_B) And
  1471. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1472. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1473. Begin
  1474. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1475. AsmL^.Remove(hp1);
  1476. Dispose(hp1, Done)
  1477. End
  1478. End;
  1479. A_SUB:
  1480. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1481. { * change "sub/add const1, reg" or "dec reg" followed by
  1482. "sub const2, reg" to one "sub ..., reg" }
  1483. Begin
  1484. If (Paicpu(p)^.oper[0].typ = top_const) And
  1485. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1486. If (Paicpu(p)^.oper[0].val = 2) And
  1487. (Paicpu(p)^.oper[1].reg = R_ESP) and
  1488. { Don't do the sub/push optimization if the sub }
  1489. { comes from setting up the stack frame (JM) }
  1490. (not getLastInstruction(p,hp1) or
  1491. (hp1^.typ <> ait_instruction) or
  1492. (paicpu(hp1)^.opcode <> A_MOV) or
  1493. (paicpu(hp1)^.oper[0].typ <> top_reg) or
  1494. (paicpu(hp1)^.oper[0].reg <> R_ESP) or
  1495. (paicpu(hp1)^.oper[1].typ <> top_reg) or
  1496. (paicpu(hp1)^.oper[1].reg <> R_EBP)) then
  1497. Begin
  1498. hp1 := Pai(p^.next);
  1499. While Assigned(hp1) And
  1500. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1501. Not((Pai(hp1)^.typ = ait_instruction) And
  1502. ((Paicpu(hp1)^.opcode = A_CALL) or
  1503. (Paicpu(hp1)^.opcode = A_PUSH) or
  1504. ((Paicpu(hp1)^.opcode = A_MOV) And
  1505. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1506. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1507. hp1 := Pai(hp1^.next);
  1508. If Assigned(hp1) And
  1509. (Pai(hp1)^.typ = ait_instruction) And
  1510. (Paicpu(hp1)^.opcode = A_PUSH) And
  1511. (Paicpu(hp1)^.opsize = S_W)
  1512. Then
  1513. Begin
  1514. Paicpu(hp1)^.changeopsize(S_L);
  1515. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1516. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1517. hp1 := Pai(p^.next);
  1518. AsmL^.Remove(p);
  1519. Dispose(p, Done);
  1520. p := hp1;
  1521. Continue
  1522. End;
  1523. If DoSubAddOpt(p) Then continue;
  1524. End
  1525. Else If DoSubAddOpt(p) Then Continue
  1526. End;
  1527. A_XOR:
  1528. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1529. (Paicpu(p)^.oper[1].typ = top_reg) And
  1530. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1531. { temporarily change this to 'mov reg,0' to make it easier }
  1532. { for the CSE. Will be changed back in pass 2 }
  1533. begin
  1534. paicpu(p)^.opcode := A_MOV;
  1535. paicpu(p)^.loadconst(0,0);
  1536. end;
  1537. End;
  1538. end; { if is_jmp }
  1539. End;
  1540. { ait_label:
  1541. Begin
  1542. If labelCanBeSkipped(pai_label(p))
  1543. Then
  1544. Begin
  1545. hp1 := Pai(p^.next);
  1546. AsmL^.Remove(p);
  1547. Dispose(p, Done);
  1548. p := hp1;
  1549. Continue
  1550. End;
  1551. End;}
  1552. End;
  1553. p:=pai(p^.next);
  1554. end;
  1555. end;
  1556. function isFoldableArithOp(hp1: paicpu; reg: tregister): boolean;
  1557. begin
  1558. IsFoldableArithOp := False;
  1559. case hp1^.opcode of
  1560. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1561. isFoldableArithOp :=
  1562. (paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) and
  1563. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1564. (paicpu(hp1)^.oper[1].reg = reg);
  1565. A_INC,A_DEC:
  1566. isFoldableArithOp :=
  1567. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1568. (paicpu(hp1)^.oper[0].reg = reg);
  1569. end;
  1570. end;
  1571. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1572. function CanBeCMOV(p : pai) : boolean;
  1573. begin
  1574. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1575. (paicpu(p)^.opcode=A_MOV) and
  1576. (paicpu(p)^.opsize in [S_L,S_W]) and
  1577. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1578. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1579. end;
  1580. var
  1581. p,hp1,hp2: pai;
  1582. {$ifdef USECMOV}
  1583. l : longint;
  1584. condition : tasmcond;
  1585. hp3: pai;
  1586. {$endif USECMOV}
  1587. UsedRegs, TmpUsedRegs: TRegSet;
  1588. Begin
  1589. P := BlockStart;
  1590. UsedRegs := [];
  1591. While (P <> BlockEnd) Do
  1592. Begin
  1593. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1594. Case P^.Typ Of
  1595. Ait_Instruction:
  1596. Begin
  1597. Case Paicpu(p)^.opcode Of
  1598. A_CALL:
  1599. If (AktOptProcessor < ClassP6) And
  1600. GetNextInstruction(p, hp1) And
  1601. (hp1^.typ = ait_instruction) And
  1602. (paicpu(hp1)^.opcode = A_JMP) Then
  1603. Begin
  1604. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1605. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1606. InsertLLItem(AsmL, p^.previous, p, hp2);
  1607. Paicpu(p)^.opcode := A_JMP;
  1608. AsmL^.Remove(hp1);
  1609. Dispose(hp1, Done)
  1610. End;
  1611. {$ifdef USECMOV}
  1612. A_Jcc:
  1613. if (aktspecificoptprocessor=ClassP6) then
  1614. begin
  1615. { check for
  1616. jCC xxx
  1617. <several movs>
  1618. xxx:
  1619. }
  1620. l:=0;
  1621. GetNextInstruction(p, hp1);
  1622. while assigned(hp1) And
  1623. CanBeCMOV(hp1) do
  1624. begin
  1625. inc(l);
  1626. GetNextInstruction(hp1,hp1);
  1627. end;
  1628. if assigned(hp1) then
  1629. begin
  1630. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1631. begin
  1632. if (l<=4) and (l>0) then
  1633. begin
  1634. condition:=inverse_cond[paicpu(p)^.condition];
  1635. GetNextInstruction(p,hp1);
  1636. asml^.remove(p);
  1637. dispose(p,done);
  1638. p:=hp1;
  1639. repeat
  1640. paicpu(hp1)^.opcode:=A_CMOVcc;
  1641. paicpu(hp1)^.condition:=condition;
  1642. GetNextInstruction(hp1,hp1);
  1643. until not(assigned(hp1)) or
  1644. not(CanBeCMOV(hp1));
  1645. asml^.remove(hp1);
  1646. dispose(hp1,done);
  1647. continue;
  1648. end;
  1649. end
  1650. else
  1651. begin
  1652. { check further for
  1653. jCC xxx
  1654. <several movs>
  1655. jmp yyy
  1656. xxx:
  1657. <several movs>
  1658. yyy:
  1659. }
  1660. { hp2 points to jmp xxx }
  1661. hp2:=hp1;
  1662. { skip hp1 to xxx }
  1663. GetNextInstruction(hp1, hp1);
  1664. if assigned(hp2) and
  1665. assigned(hp1) and
  1666. (l<=3) and
  1667. (hp2^.typ=ait_instruction) and
  1668. (paicpu(hp2)^.is_jmp) and
  1669. (paicpu(hp2)^.condition=C_None) and
  1670. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1671. begin
  1672. l:=0;
  1673. while assigned(hp1) And
  1674. CanBeCMOV(hp1) do
  1675. begin
  1676. inc(l);
  1677. GetNextInstruction(hp1, hp1);
  1678. end;
  1679. end;
  1680. {
  1681. if assigned(hp1) and
  1682. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1683. begin
  1684. condition:=inverse_cond[paicpu(p)^.condition];
  1685. GetNextInstruction(p,hp1);
  1686. asml^.remove(p);
  1687. dispose(p,done);
  1688. p:=hp1;
  1689. repeat
  1690. paicpu(hp1)^.opcode:=A_CMOVcc;
  1691. paicpu(hp1)^.condition:=condition;
  1692. GetNextInstruction(hp1,hp1);
  1693. until not(assigned(hp1)) or
  1694. not(CanBeCMOV(hp1));
  1695. hp2:=hp1^.next;
  1696. condition:=inverse_cond[condition];
  1697. asml^.remove(hp1^.next)
  1698. dispose(hp1^.next,done);
  1699. asml^.remove(hp1);
  1700. dispose(hp1,done);
  1701. continue;
  1702. end;
  1703. }
  1704. end;
  1705. end;
  1706. end;
  1707. {$endif USECMOV}
  1708. A_FSTP,A_FISTP:
  1709. if doFpuLoadStoreOpt(asmL,p) then
  1710. continue;
  1711. A_IMUL:
  1712. begin
  1713. if ((paicpu(p)^.oper[0].typ = top_const) or
  1714. (paicpu(p)^.oper[0].typ = top_symbol)) and
  1715. (paicpu(p)^.oper[1].typ = top_reg) and
  1716. ((paicpu(p)^.oper[2].typ = top_none) or
  1717. ((paicpu(p)^.oper[2].typ = top_reg) and
  1718. (paicpu(p)^.oper[2].reg = paicpu(p)^.oper[1].reg))) and
  1719. getLastInstruction(p,hp1) and
  1720. (hp1^.typ = ait_instruction) and
  1721. (paicpu(hp1)^.opcode = A_MOV) and
  1722. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1723. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1724. (paicpu(hp1)^.oper[1].reg = paicpu(p)^.oper[1].reg) then
  1725. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1726. begin
  1727. paicpu(p)^.ops := 3;
  1728. paicpu(p)^.loadreg(1,paicpu(hp1)^.oper[0].reg);
  1729. paicpu(p)^.loadreg(2,paicpu(hp1)^.oper[1].reg);
  1730. asmL^.remove(hp1);
  1731. dispose(hp1,done);
  1732. end;
  1733. end;
  1734. A_MOV:
  1735. Begin
  1736. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1737. (Paicpu(p)^.oper[1].typ = top_reg) And
  1738. GetNextInstruction(p, hp1) And
  1739. (hp1^.typ = ait_Instruction) And
  1740. ((Paicpu(hp1)^.opcode = A_MOV) or
  1741. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1742. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1743. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1744. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1745. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1746. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1747. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1748. {mov reg1, reg2
  1749. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1750. Begin
  1751. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1752. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1753. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1754. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1755. AsmL^.Remove(p);
  1756. Dispose(p, Done);
  1757. p := hp1;
  1758. Continue;
  1759. End
  1760. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1761. GetNextInstruction(p,hp1) And
  1762. (hp1^.typ = ait_instruction) And
  1763. IsFoldableArithOp(paicpu(hp1),Paicpu(p)^.oper[1].reg) And
  1764. GetNextInstruction(hp1,hp2) And
  1765. (hp2^.typ = ait_instruction) And
  1766. (Paicpu(hp2)^.opcode = A_MOV) And
  1767. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1768. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1769. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1770. Begin
  1771. TmpUsedRegs := UsedRegs;
  1772. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1773. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1774. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg,
  1775. hp2, TmpUsedRegs)))
  1776. Then
  1777. { change mov (ref), reg }
  1778. { add/sub/or/... reg2/$const, reg }
  1779. { mov reg, (ref) }
  1780. { # release reg }
  1781. { to add/sub/or/... reg2/$const, (ref) }
  1782. Begin
  1783. case paicpu(hp1)^.opcode of
  1784. A_INC,A_DEC:
  1785. paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^))
  1786. else
  1787. paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1788. end;
  1789. AsmL^.Remove(p);
  1790. AsmL^.Remove(hp2);
  1791. Dispose(p,done);
  1792. Dispose(hp2,Done);
  1793. p := hp1
  1794. End;
  1795. End
  1796. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1797. (Paicpu(p)^.oper[0].val = 0) And
  1798. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1799. { change "mov $0, %reg" into "xor %reg, %reg" }
  1800. Begin
  1801. Paicpu(p)^.opcode := A_XOR;
  1802. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1803. End
  1804. End;
  1805. A_MOVZX:
  1806. Begin
  1807. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1808. If (Paicpu(p)^.oper[0].typ = top_reg)
  1809. Then
  1810. Case Paicpu(p)^.opsize of
  1811. S_BL:
  1812. Begin
  1813. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1814. Not(CS_LittleSize in aktglobalswitches) And
  1815. (aktoptprocessor = ClassP5)
  1816. Then
  1817. {Change "movzbl %reg1, %reg2" to
  1818. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1819. PentiumMMX}
  1820. Begin
  1821. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1822. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1823. InsertLLItem(AsmL,p^.previous, p, hp1);
  1824. Paicpu(p)^.opcode := A_MOV;
  1825. Paicpu(p)^.changeopsize(S_B);
  1826. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1827. End;
  1828. End;
  1829. End
  1830. Else
  1831. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1832. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1833. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1834. Not(CS_LittleSize in aktglobalswitches) And
  1835. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1836. (aktoptprocessor = ClassP5) And
  1837. (Paicpu(p)^.opsize = S_BL)
  1838. Then
  1839. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1840. Pentium and PentiumMMX}
  1841. Begin
  1842. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1843. Paicpu(p)^.oper[1].reg));
  1844. Paicpu(p)^.opcode := A_MOV;
  1845. Paicpu(p)^.changeopsize(S_B);
  1846. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1847. InsertLLItem(AsmL,p^.previous, p, hp1);
  1848. End;
  1849. End;
  1850. A_TEST, A_OR:
  1851. {removes the line marked with (x) from the sequence
  1852. And/or/xor/add/sub/... $x, %y
  1853. test/or %y, %y (x)
  1854. j(n)z _Label
  1855. as the first instruction already adjusts the ZF}
  1856. Begin
  1857. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1858. If GetLastInstruction(p, hp1) And
  1859. (pai(hp1)^.typ = ait_instruction) Then
  1860. Case Paicpu(hp1)^.opcode Of
  1861. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1862. Begin
  1863. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1864. Begin
  1865. hp1 := pai(p^.next);
  1866. asml^.remove(p);
  1867. dispose(p, done);
  1868. p := pai(hp1);
  1869. continue
  1870. End;
  1871. End;
  1872. A_DEC, A_INC, A_NEG:
  1873. Begin
  1874. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1875. Begin
  1876. Case Paicpu(hp1)^.opcode Of
  1877. A_DEC, A_INC:
  1878. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1879. Begin
  1880. Case Paicpu(hp1)^.opcode Of
  1881. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1882. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1883. End;
  1884. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1885. Paicpu(hp1)^.LoadConst(0,1);
  1886. Paicpu(hp1)^.ops:=2;
  1887. End
  1888. End;
  1889. hp1 := pai(p^.next);
  1890. asml^.remove(p);
  1891. dispose(p, done);
  1892. p := pai(hp1);
  1893. continue
  1894. End;
  1895. End
  1896. End
  1897. End;
  1898. End;
  1899. End;
  1900. End;
  1901. p := Pai(p^.next)
  1902. End;
  1903. End;
  1904. End.
  1905. {
  1906. $Log$
  1907. Revision 1.7 2000-08-04 22:00:52 peter
  1908. * merges from fixes
  1909. Revision 1.6 2000/07/31 08:44:05 jonas
  1910. - removed imul support from -dfoldarithops since "imull [reg32],[mem32]"
  1911. doesn't exist (merged from fixes branch)
  1912. Revision 1.5 2000/07/28 13:56:23 jonas
  1913. * fixed bug in shr/shl optimization when -Og is used (merged from fixes
  1914. branch)
  1915. Revision 1.4 2000/07/21 15:19:55 jonas
  1916. * daopt386: changes to getnextinstruction/getlastinstruction so they
  1917. ignore labels who have is_addr set
  1918. + daopt386/csopt386: remove loads of registers which are overwritten
  1919. before their contents are used (especially usefull for removing superfluous
  1920. maybe_loadesi outputs and push/pops transformed by below optimization
  1921. + popt386: transform pop/pop/pop/.../push/push/push to sequences of
  1922. 'movl x(%esp),%reg' (only active when compiling a go32v2 compiler
  1923. currently because I don't know whether it's safe to do this under Win32/
  1924. Linux (because of problems we had when using esp as frame pointer on
  1925. those os'es)
  1926. Revision 1.3 2000/07/14 05:11:49 michael
  1927. + Patch to 1.1
  1928. Revision 1.2 2000/07/13 11:32:45 michael
  1929. + removed logs
  1930. }