m68k.inc 21 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 1999-2000 by Carl-Eric Codere,
  4. member of the Free Pascal development team.
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. {****************************************************************************
  12. m68k.inc : Processor dependent implementation of system unit
  13. For Motorola 680x0 Processor.
  14. *****************************************************************************}
  15. {****************************************************************************}
  16. { Credit where credit is due: }
  17. { -Some of the copy routines taken from the Atari dlib source code: }
  18. { Dale Schumacher (alias: Dalnefre') [email protected] }
  19. { 399 Beacon Ave. St. Paul, MN 55104,USA }
  20. { -Some of the routines taken from the freeware ATARI Sozobon C compiler }
  21. { 1988 by Sozobon, Limited. Author: Johann Ruegg (freeware) }
  22. { Thanks to all these people wherever they maybe today! }
  23. {****************************************************************************}
  24. {$IF DEFINED(FPU68881) OR DEFINED(FPUCOLDFIRE)}
  25. function GetFPCR: DWord; assembler; nostackframe;
  26. asm
  27. fmove.l fpcr,d0
  28. end;
  29. function GetFPSR: DWord; assembler; nostackframe;
  30. asm
  31. fmove.l fpsr, d0
  32. end;
  33. procedure SetFPCR(x: DWord);
  34. begin
  35. Default68kFPCR:=x;
  36. asm
  37. fmove.l x, fpcr
  38. end;
  39. end;
  40. procedure SetFPSR(x: DWord); assembler; nostackframe;
  41. asm
  42. fmove.l x, fpsr
  43. end;
  44. function GetNativeFPUControlWord: TNativeFPUControlWord;
  45. begin
  46. result:=GetFPCR;
  47. end;
  48. procedure SetNativeFPUControlWord(const cw: TNativeFPUControlWord);
  49. begin
  50. SetFPCR(cw);
  51. end;
  52. {$DEFINE FPC_SYSTEM_HAS_SYSRESETFPU}
  53. procedure SysResetFPU;
  54. begin
  55. softfloat_exception_flags:=[];
  56. SetFPCR(Default68KFPCR);
  57. SetFPSR(0);
  58. end;
  59. {$DEFINE FPC_SYSTEM_HAS_SYSINITFPU}
  60. procedure SysInitFPU;
  61. begin
  62. softfloat_exception_mask:=[float_flag_underflow,float_flag_inexact,float_flag_denormal];
  63. softfloat_exception_flags:=[];
  64. SetFPSR(0);
  65. end;
  66. {$endif}
  67. {$ifndef INTERNAL_BACKTRACE}
  68. {$define FPC_SYSTEM_HAS_GET_FRAME}
  69. function get_frame : pointer; assembler;nostackframe;
  70. asm
  71. move.l fp,d0
  72. end;
  73. {$endif not INTERNAL_BACKTRACE}
  74. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  75. function get_caller_addr(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  76. asm
  77. move.l framebp,d0
  78. tst.l d0
  79. beq @Lnul_address
  80. move.l d0,a0
  81. move.l 4(a0),d0
  82. @Lnul_address:
  83. end;
  84. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  85. function get_caller_frame(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  86. asm
  87. move.l framebp,d0
  88. tst.l d0
  89. beq @Lnul_frame
  90. move.l d0,a0
  91. move.l (a0),d0
  92. @Lnul_frame:
  93. end;
  94. {$define FPC_SYSTEM_HAS_SPTR}
  95. function Sptr : pointer; assembler;nostackframe;
  96. asm
  97. move.l sp,d0
  98. end;
  99. {$define FPC_SYSTEM_HAS_GET_PC_ADDR}
  100. function get_pc_addr : pointer;assembler;nostackframe;
  101. asm
  102. move.l (sp),d0
  103. end;
  104. {$ifndef FPC_SYSTEM_HAS_FILLCHAR}
  105. {$define FPC_SYSTEM_HAS_FILLCHAR}
  106. procedure FillChar(var x; count : longint; value : byte); assembler; register; nostackframe;
  107. asm
  108. { a0 is x, d0 is count, d1 is value }
  109. tst.l d0 { anything to fill at all? }
  110. ble @Lquit
  111. cmp.l #32,d0 { limits were tested against real hardware on various CPU }
  112. blt @LfillByte
  113. cmp.l #128,d0 { limits were tested against real hardware on various CPU }
  114. blt @LfillWord
  115. bra @LfillDWord
  116. {$ifndef CPUM68K_HAS_DBRA}
  117. @LfillByte:
  118. {$endif}
  119. @LfillByteLoop:
  120. move.b d1,(a0)+
  121. {$ifdef CPUM68K_HAS_DBRA}
  122. @LfillByte:
  123. dbra d0,@LfillByteLoop
  124. {$else}
  125. subq.l #1,d0
  126. bne @LfillByteLoop
  127. {$endif}
  128. rts
  129. @LfillWord:
  130. move.l d2,-(sp)
  131. move.l a0,d2
  132. btst #0,d2
  133. beq @Leven
  134. subq.l #1,d0
  135. move.b d1,(a0)+
  136. @Leven:
  137. move.b d1,d2 // copy value to upper byte
  138. {$ifdef CPUCOLDFIRE}
  139. lsl.l #8,d1
  140. {$else}
  141. lsl.w #8,d1
  142. {$endif}
  143. move.b d2,d1
  144. move.l d0,d2 // adjust d0 for leftover copy
  145. bclr #0,d2
  146. sub.l d2,d0
  147. lsr.l #1,d2
  148. {$ifdef CPUM68K_HAS_DBRA}
  149. subq.l #1,d2
  150. {$endif}
  151. @LfillWordLoop:
  152. move.w d1,(a0)+
  153. {$ifdef CPUM68K_HAS_DBRA}
  154. dbra d2,@LFillWordLoop
  155. {$else}
  156. subq.l #1,d2
  157. bne @LfillWordLoop
  158. {$endif}
  159. move.l (sp)+,d2
  160. tst.l d0
  161. bne @LfillByte
  162. rts
  163. @LfillDWord:
  164. move.l d2,-(sp)
  165. move.b d1,d2 // copy value to upper bytes
  166. {$ifdef CPUCOLDFIRE}
  167. lsl.l #8,d1
  168. {$else}
  169. lsl.w #8,d1
  170. {$endif}
  171. move.b d2,d1
  172. move.w d1,d2
  173. swap d1
  174. move.w d2,d1
  175. move.l a0,d2 // do initial byte and word fill, if the address is unaligned
  176. btst #0,d2
  177. beq @Ldeven
  178. subq.l #1,d0
  179. move.b d1,(a0)+
  180. @Ldeven:
  181. move.l a0,d2
  182. btst #1,d2
  183. beq @Ldquad
  184. subq.l #2,d0
  185. move.w d1,(a0)+
  186. @Ldquad:
  187. move.l d0,d2 // adjust d0 for leftover copy
  188. {$ifdef CPUCOLDFIRE}
  189. and.l #$fffffffc,d2
  190. {$else}
  191. and.b #$fc,d2
  192. {$endif}
  193. sub.l d2,d0
  194. lsr.l #2,d2
  195. bra @LfillLongLoopStart
  196. @LfillLongLoop:
  197. move.l d1,(a0)+
  198. move.l d1,(a0)+
  199. move.l d1,(a0)+
  200. move.l d1,(a0)+
  201. subq.l #4,d2
  202. @LfillLongLoopStart:
  203. cmp.l #4,d2
  204. bgt @LfillLongLoop
  205. {$ifdef CPUM68K_HAS_DBRA}
  206. subq.l #1,d2
  207. {$endif}
  208. @LfillDWordLoop:
  209. move.l d1,(a0)+
  210. {$ifdef CPUM68K_HAS_DBRA}
  211. dbra d2,@LFillDWordLoop
  212. {$else}
  213. subq.l #1,d2
  214. bne @LfillDWordLoop
  215. {$endif}
  216. move.l (sp)+,d2
  217. tst.l d0
  218. bne @LfillByte
  219. @Lquit:
  220. end;
  221. {$endif ndef FPC_SYSTEM_HAS_FILLCHAR}
  222. {$ifdef dummy}
  223. { procedure strcopy(dstr,sstr : pointer;len : longint);[public,alias: 'STRCOPY'];}
  224. procedure strcopy; assembler;[public,alias: 'FPC_STRCOPY'];
  225. {---------------------------------------------------}
  226. { Low-level routine to copy a string to another }
  227. { string with maximum length. Never call directly! }
  228. { On Entry: }
  229. { a1.l = string to copy to }
  230. { a0.l = source string }
  231. { d0.l = maximum length of copy }
  232. { registers destroyed: a0,a1,d0,d1 }
  233. {---------------------------------------------------}
  234. asm
  235. { move.l sstr,a0
  236. move.l dstr,a1
  237. move.l len,d1 }
  238. move.l d0,d1
  239. move.b (a0)+,d0 { Get source length }
  240. and.w #$ff,d0
  241. cmp.w d1,d0 { This is a signed comparison! }
  242. ble @LM4
  243. move.b d1,d0 { If longer than maximum size of target, cut
  244. source length }
  245. @LM4:
  246. andi.l #$ff,d0 { zero extend d0-byte }
  247. move.l d0,d1 { save length to copy }
  248. move.b d0,(a1)+ { save new length }
  249. { Check if copying length is zero - if so then }
  250. { exit without copying anything. }
  251. tst.b d1
  252. beq @Lend
  253. bra @LMSTRCOPY55
  254. @LMSTRCOPY56: { 68010 Fast loop mode }
  255. move.b (a0)+,(a1)+
  256. @LMSTRCOPY55:
  257. {$ifndef CPUM68K_HAS_DBRA}
  258. sub.l #1,d1
  259. bpl @LMSTRCOPY56
  260. {$else CPUM68K_HAS_DBRA}
  261. dbra d1,@LMSTRCOPY56
  262. {$endif CPUM68K_HAS_DBRA}
  263. @Lend:
  264. end;
  265. { Concatenate Strings }
  266. { PARAMETERS ARE REVERSED COMPARED TO NORMAL! }
  267. { therefore online assembler may not parse the params as normal }
  268. procedure strconcat(s1,s2 : pointer);[public,alias: 'STRCONCAT'];
  269. begin
  270. asm
  271. move.b #255,d0
  272. move.l s1,a0 { a0 = destination }
  273. move.l s2,a1 { a1 = source }
  274. sub.b (a0),d0 { copyl:= 255 -length(s1) }
  275. move.b (a1),d6
  276. and.w #$ff,d0 { Sign flags are checked! }
  277. and.w #$ff,d6
  278. cmp.w d6,d0 { if copyl > length(s2) then }
  279. ble @Lcontinue
  280. move.b (a1),d0 { copyl:=length(s2) }
  281. @Lcontinue:
  282. move.b (a0),d6
  283. and.l #$ff,d6
  284. lea 1(a0,d6),a0 { s1[length(s1)+1] }
  285. add.l #1,a1 { s2[1] }
  286. move.b d0,d6
  287. { Check if copying length is zero - if so then }
  288. { exit without copying anything. }
  289. tst.b d6
  290. beq @Lend
  291. bra @ALoop
  292. @Loop:
  293. move.b (a1)+,(a0)+ { s1[i] := s2[i]; }
  294. @ALoop:
  295. {$ifndef CPUM68K_HAS_DBRA}
  296. sub.l #1,d6
  297. bpl @Loop
  298. {$else CPUM68K_HAS_DBRA}
  299. dbra d6,@Loop
  300. {$endif CPUM68K_HAS_DBRA}
  301. move.l s1,a0
  302. add.b d0,(a0) { change to new string length }
  303. @Lend:
  304. end ['d0','d1','a0','a1','d6'];
  305. end;
  306. { Compares strings }
  307. { DO NOT CALL directly. }
  308. { a0 = pointer to first string to compare }
  309. { a1 = pointer to second string to compare }
  310. { ALL FLAGS are set appropriately. }
  311. { ZF = strings are equal }
  312. { REGISTERS DESTROYED: a0, a1, d0, d1, d6 }
  313. procedure strcmp; assembler;[public,alias:'FPC_STRCMP'];
  314. asm
  315. move.b (a0)+,d0 { Get length of first string }
  316. move.b (a1)+,d6 { Get length of 2nd string }
  317. move.b d6,d1 { Save length of string for final compare }
  318. cmp.b d0,d6 { Get shortest string length }
  319. ble @LSTRCONCAT1
  320. move.b d0,d6 { Set length to shortest string }
  321. @LSTRCONCAT1:
  322. tst.b d6 { Both strings have a length of zero, exit }
  323. beq @LSTRCONCAT2
  324. andi.l #$ff,d6
  325. subq.l #1,d6 { subtract first attempt }
  326. { if value is -1 then don't loop and just compare lengths of }
  327. { both strings before exiting. }
  328. bmi @LSTRCONCAT2
  329. or.l d0,d0 { Make sure to set Zerfo flag to 0 }
  330. @LSTRCONCAT5:
  331. { Workaroung for GAS v.134 bug }
  332. { old: cmp.b (a1)+,(a0)+ }
  333. cmpm.b (a1)+,(a0)+
  334. @LSTRCONCAT4:
  335. dbne d6,@LSTRCONCAT5 { Repeat until not equal }
  336. bne @LSTRCONCAT3
  337. @LSTRCONCAT2:
  338. { If length of both string are equal }
  339. { Then set zero flag }
  340. cmp.b d1,d0 { Compare length - set flag if equal length strings }
  341. @LSTRCONCAT3:
  342. end;
  343. {$endif dummy}
  344. {$ifndef FPC_SYSTEM_HAS_MOVE}
  345. {$define FPC_SYSTEM_HAS_MOVE}
  346. procedure move(const source;var dest;count : longint); assembler;
  347. { base pointer+8 = source }
  348. { base pointer+12 = destination }
  349. { base pointer+16 = number of bytes to move}
  350. asm
  351. move.l count, d0 { number of bytes }
  352. ble @LMOVE5 { anything to copy at all? }
  353. move.l dest, a1 { destination }
  354. move.l source, a0 { source }
  355. {$ifdef CPUM68K_HAS_DBRA}
  356. cmpi.l #65535, d0 { check, if this is a word move }
  357. ble @LMEMSET00 { use fast dbra mode 68010+ }
  358. {$endif CPUM68K_HAS_DBRA}
  359. cmp.l a0,a1 { check copy direction }
  360. bls @LMOVE3
  361. add.l d0,a0 { move pointers to end }
  362. add.l d0,a1
  363. @LMOVE1:
  364. move.b -(a0),-(a1) { (s < d) copy loop }
  365. subq.l #1,d0
  366. bne @LMOVE1
  367. bra @LMOVE5
  368. @LMOVE3:
  369. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  370. subq.l #1,d0
  371. bne @LMOVE3
  372. bra @LMOVE5
  373. {$ifdef CPUM68K_HAS_DBRA}
  374. @LMEMSET00: { use fast loop mode 68010+ }
  375. cmp.l a0,a1 { check copy direction }
  376. bls @LMOVE04
  377. add.l d0,a0 { move pointers to end }
  378. add.l d0,a1
  379. bra @LMOVE02
  380. @LMOVE01:
  381. move.b -(a0),-(a1) { (s < d) copy loop }
  382. @LMOVE02:
  383. dbra d0,@LMOVE01
  384. bra @LMOVE5
  385. @LMOVE03:
  386. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  387. @LMOVE04:
  388. dbra d0,@LMOVE03
  389. {$endif CPUM68K_HAS_DBRA}
  390. { end fast loop mode }
  391. @LMOVE5:
  392. end;
  393. {$endif ndef FPC_SYSTEM_HAS_MOVE}
  394. {$ifdef CPUM68K_HAS_UNALIGNED}
  395. {$define FPC_SYSTEM_HAS_FILLWORD}
  396. procedure FillWord(var x; count : longint; value : word); assembler;
  397. asm
  398. move.l x, a0 { destination }
  399. move.w value, d1 { fill data }
  400. move.l count, d0 { number of bytes to fill }
  401. ble @LMEMSET3 { anything to fill at all? }
  402. bra @LMEMSET21
  403. @LMEMSET11:
  404. move.w d1,(a0)+
  405. @LMEMSET21:
  406. subq.l #1,d0
  407. bpl @LMEMSET11
  408. @LMEMSET3:
  409. end;
  410. {$endif}
  411. {$IFNDEF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  412. {$IFNDEF CPUM68K_HAS_CAS}
  413. var
  414. spinLock: byte;
  415. procedure getSpinLock; assembler; nostackframe;
  416. asm
  417. {$IFDEF CPUM68K_HAS_TAS}
  418. lea.l spinlock,a0
  419. @loop:
  420. tas (a0)
  421. bne @loop
  422. {$ENDIF}
  423. end;
  424. procedure releaseSpinLock; assembler; nostackframe;
  425. asm
  426. moveq.l #0,d0
  427. move.b d0,spinlock
  428. end;
  429. {$ENDIF}
  430. {$IFDEF VER3_2}
  431. function InterLockedDecrement (var Target: longint) : longint;
  432. {$ELSE VER3_2}
  433. {$DEFINE FPC_SYSTEM_HAS_ATOMIC_DEC_32}
  434. function fpc_atomic_dec_32 (var Target: longint) : longint;
  435. {$ENDIF VER3_2}
  436. {$IFDEF CPUM68K_HAS_CAS}
  437. register; assembler;
  438. asm
  439. move.l (a0), d0
  440. @loop:
  441. move.l d0, d1
  442. subq.l #1, d1
  443. cas.l d0, d1, (a0)
  444. bne @loop
  445. move.l d1, d0
  446. end;
  447. {$ELSE}
  448. begin
  449. getSpinLock;
  450. Dec(Target);
  451. Result := Target;
  452. releaseSpinLock;
  453. end;
  454. {$ENDIF}
  455. {$IFDEF VER3_2}
  456. function InterLockedIncrement (var Target: longint) : longint;
  457. {$ELSE VER3_2}
  458. {$DEFINE FPC_SYSTEM_HAS_ATOMIC_INC_32}
  459. function fpc_atomic_inc_32 (var Target: longint) : longint;
  460. {$ENDIF VER3_2}
  461. {$IFDEF CPUM68K_HAS_CAS}
  462. register; assembler;
  463. asm
  464. move.l (a0), d0
  465. @loop:
  466. move.l d0, d1
  467. addq.l #1, d1
  468. cas.l d0, d1, (a0)
  469. bne @loop
  470. move.l d1, d0
  471. end;
  472. {$ELSE}
  473. begin
  474. getSpinLock;
  475. Inc(Target);
  476. Result := Target;
  477. releaseSpinLock;
  478. end;
  479. {$ENDIF}
  480. {$IFDEF VER3_2}
  481. function InterLockedExchange (var Target: longint;Source : longint) : longint;
  482. {$ELSE VER3_2}
  483. {$DEFINE FPC_SYSTEM_HAS_ATOMIC_XCHG_32}
  484. function fpc_atomic_xchg_32 (var Target: longint;Source : longint) : longint;
  485. {$ENDIF VER3_2}
  486. {$IFDEF CPUM68K_HAS_CAS}
  487. register; assembler;
  488. asm
  489. move.l Source, d1
  490. move.l (a0), d0
  491. @loop:
  492. cas.l d0, d1, (a0)
  493. bne @loop
  494. end;
  495. {$ELSE}
  496. begin
  497. getSpinLock;
  498. Result := Target;
  499. Target := Source;
  500. releaseSpinLock;
  501. end;
  502. {$ENDIF}
  503. {$IFDEF VER3_2}
  504. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint;
  505. {$ELSE VER3_2}
  506. {$DEFINE FPC_SYSTEM_HAS_ATOMIC_ADD_32}
  507. function fpc_atomic_add_32 (var Target: longint;Value : longint) : longint;
  508. {$ENDIF VER3_2}
  509. {$IFDEF CPUM68K_HAS_CAS}
  510. register; assembler;
  511. asm
  512. {$IFDEF VER3_2}
  513. move.l Source, a1
  514. {$ELSE VER3_2}
  515. move.l Value, a1
  516. {$ENDIF VER3_2}
  517. move.l (a0), d0
  518. @loop:
  519. move.l a1, d1
  520. add.l d0, d1
  521. cas.l d0, d1, (a0)
  522. bne @loop
  523. end;
  524. {$ELSE}
  525. begin
  526. getSpinLock;
  527. Result := Target;
  528. Target := Target + {$IFDEF VER3_2}Source{$ELSE}Value{$ENDIF};
  529. releaseSpinLock;
  530. end;
  531. {$ENDIF}
  532. {$IFDEF VER3_2}
  533. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint;
  534. {$ELSE VER3_2}
  535. {$DEFINE FPC_SYSTEM_HAS_ATOMIC_CMP_XCHG_32}
  536. function fpc_atomic_cmp_xchg_32 (var Target: longint; NewValue: longint; Comparand: longint) : longint; [public,alias:'FPC_ATOMIC_CMP_XCHG_32'];
  537. {$ENDIF VER3_2}
  538. {$IFDEF CPUM68K_HAS_CAS}
  539. register; assembler;
  540. asm
  541. // Target = a0, NewValue = d0, Comperand = d1
  542. exg.l d0, d1
  543. cas.l d0, d1, (a0)
  544. end;
  545. {$ELSE}
  546. begin
  547. getSpinLock;
  548. Result := Target;
  549. if Target = {$IFDEF VER3_2}Comperand{$ELSE}Comparand{$ENDIF} then
  550. Target := NewValue;
  551. releaseSpinLock;
  552. end;
  553. {$ENDIF}
  554. {$ENDIF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  555. {$ifndef FPC_SYSTEM_HAS_TEST68K}
  556. procedure Test68k(var CPU: byte; var FPU: byte);
  557. begin
  558. {$warning Implement me!}
  559. CPU:=0;
  560. FPU:=0;
  561. end;
  562. {$endif}
  563. {$ifndef FPC_SYSTEM_HAS_SAR_QWORD}
  564. {$define FPC_SYSTEM_HAS_SAR_QWORD}
  565. function fpc_SarInt64(Const AValue : Int64;const Shift : Byte): Int64; [Public,Alias:'FPC_SARINT64']; compilerproc; assembler; nostackframe;
  566. asm
  567. // d0 = shift
  568. lea.l 4(sp),a0
  569. move.l d2,-(sp)
  570. move.l d0,d2
  571. {$ifndef CPUCOLDFIRE}
  572. and.w #63,d2
  573. cmp.w #32,d2
  574. {$else}
  575. and.l #63,d2
  576. cmp.l #32,d2
  577. {$endif}
  578. bge.s @longshift
  579. move.l (a0)+,d0
  580. move.l (a0),d1
  581. {$ifdef CPUM68K_HAS_ROLROR}
  582. cmp.w #1,d2
  583. beq.s @oneshift
  584. {$endif}
  585. {$ifdef CPU68000}
  586. cmp.w #16,d2
  587. beq.s @sixteenshift
  588. {$endif}
  589. move.l d3,a0
  590. move.l d4,a1
  591. move.l d0,d3
  592. moveq.l #32,d4
  593. {$ifndef CPUCOLDFIRE}
  594. sub.w d2,d4
  595. {$else}
  596. sub.l d2,d4
  597. {$endif}
  598. asr.l d2,d0
  599. lsl.l d4,d3
  600. lsr.l d2,d1
  601. or.l d3,d1
  602. move.l a0,d3
  603. move.l a1,d4
  604. bra.s @quit
  605. {$ifdef CPU68000}
  606. @sixteenshift:
  607. move.w d0,d1
  608. swap d1
  609. swap d0
  610. ext.l d0
  611. bra.s @quit
  612. {$endif}
  613. {$ifdef CPUM68K_HAS_ROLROR}
  614. @oneshift:
  615. asr.l #1,d0
  616. roxr.l #1,d1
  617. bra.s @quit
  618. {$endif}
  619. @longshift:
  620. move.l (a0),d0
  621. move.l d0,d1
  622. smi d0
  623. {$if defined(CPU68020) or defined(CPUCOLDFIRE)}
  624. extb.l d0
  625. {$else}
  626. ext.w d0
  627. ext.l d0
  628. {$endif}
  629. {$ifndef CPUCOLDFIRE}
  630. sub.w #32,d2
  631. {$else}
  632. sub.l #32,d2
  633. {$endif}
  634. asr.l d2,d1
  635. @quit:
  636. move.l (sp)+,d2
  637. end;
  638. {$endif}
  639. {$if defined(CPUM68K_HAS_BYTEREV) or defined(CPUM68K_HAS_ROLROR)}
  640. { Disabled for now, because not all cases below were tested. (KB) }
  641. {.$define FPC_SYSTEM_HAS_SWAPENDIAN}
  642. {$endif}
  643. {$if defined(FPC_SYSTEM_HAS_SWAPENDIAN)}
  644. function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
  645. asm
  646. {$if defined(CPUM68K_HAS_ROLROR)}
  647. move.w avalue, d0
  648. ror.w #8, d0
  649. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  650. move.w avalue, d0
  651. byterev d0
  652. swap d0
  653. {$else}
  654. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  655. clr.l d0
  656. move.w avalue, d0
  657. move.w d0, d1
  658. lsr.l #8, d0
  659. lsl.l #8, d1
  660. or.l d1, d0
  661. {$endif}
  662. end;
  663. function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
  664. asm
  665. {$if defined(CPUM68K_HAS_ROLROR)}
  666. move.w avalue, d0
  667. ror.w #8, d0
  668. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  669. move.w avalue, d0
  670. byterev d0
  671. swap d0
  672. {$else}
  673. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  674. clr.l d0
  675. move.w avalue, d0
  676. move.w d0, d1
  677. lsr.l #8, d0
  678. lsl.l #8, d1
  679. or.l d1, d0
  680. {$endif}
  681. end;
  682. function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
  683. asm
  684. {$if defined(CPUM68K_HAS_ROLROR)}
  685. move.l avalue, d0
  686. ror.w #8, d0
  687. swap d0
  688. ror.w #8, d0
  689. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  690. move.l avalue, d0
  691. byterev d0
  692. {$else}
  693. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  694. move.l avalue, d0
  695. move.l d0, d1
  696. andi.l #$ff00ff00, d0
  697. andi.l #$00ff00ff, d1
  698. lsr.l #8, d0
  699. lsl.l #8, d1
  700. or.l d1, d0
  701. swap d0
  702. {$endif}
  703. end;
  704. function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
  705. asm
  706. {$if defined(CPUM68K_HAS_ROLROR)}
  707. move.l avalue, d0
  708. ror.w #8, d0
  709. swap d0
  710. ror.w #8, d0
  711. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  712. move.l avalue, d0
  713. byterev d0
  714. {$else}
  715. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  716. move.l avalue, d0
  717. move.l d0, d1
  718. andi.l #$ff00ff00, d0
  719. andi.l #$00ff00ff, d1
  720. lsr.l #8, d0
  721. lsl.l #8, d1
  722. or.l d1, d0
  723. swap d0
  724. {$endif}
  725. end;
  726. function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
  727. asm
  728. {$if defined(CPUM68K_HAS_ROLROR)}
  729. move.l avalue+4, d0
  730. ror.w #8, d0
  731. swap d0
  732. ror.w #8, d0
  733. move.l avalue, d1
  734. ror.w #8, d1
  735. swap d1
  736. ror.w #8, d1
  737. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  738. move.l avalue+4, d0
  739. move.l avalue, d1
  740. byterev d0
  741. byterev d1
  742. {$else}
  743. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  744. move.l d2, -(sp)
  745. move.l avalue+4, d0
  746. move.l d0, d1
  747. andi.l #$ff00ff00, d0
  748. andi.l #$00ff00ff, d1
  749. lsr.l #8, d0
  750. lsl.l #8, d1
  751. or.l d1, d0
  752. swap d0
  753. move.l avalue, d1
  754. move.l d1, d2
  755. andi.l #$ff00ff00, d1
  756. andi.l #$00ff00ff, d2
  757. lsr.l #8, d1
  758. lsl.l #8, d2
  759. or.l d2, d1
  760. swap d1
  761. move.l (sp)+, d2
  762. {$endif}
  763. end;
  764. function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
  765. asm
  766. {$if defined(CPUM68K_HAS_ROLROR)}
  767. move.l avalue+4, d0
  768. ror.w #8, d0
  769. swap d0
  770. ror.w #8, d0
  771. move.l avalue, d1
  772. ror.w #8, d1
  773. swap d1
  774. ror.w #8, d1
  775. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  776. move.l avalue+4, d0
  777. move.l avalue, d1
  778. byterev d0
  779. byterev d1
  780. {$else}
  781. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  782. move.l d2, -(sp)
  783. move.l avalue+4, d0
  784. move.l d0, d1
  785. andi.l #$ff00ff00, d0
  786. andi.l #$00ff00ff, d1
  787. lsr.l #8, d0
  788. lsl.l #8, d1
  789. or.l d1, d0
  790. swap d0
  791. move.l avalue, d1
  792. move.l d1, d2
  793. andi.l #$ff00ff00, d1
  794. andi.l #$00ff00ff, d2
  795. lsr.l #8, d1
  796. lsl.l #8, d2
  797. or.l d2, d1
  798. swap d1
  799. move.l (sp)+, d2
  800. {$endif}
  801. end;
  802. {$endif FPC_SYSTEM_HAS_SWAPENDIAN}
  803. procedure fpc_cpucodeinit;
  804. begin
  805. Test68k(Test68000,Test68881);
  806. end;