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aoptcpu.pas
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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aoptcpub.pas
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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aoptcpuc.pas
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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aoptcpud.pas
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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cgcpu.pas
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4e60ceb237
* removed code which splits "unaligned" 8 byte stores/loads into two 4 bytes stores/loads on ppc64. The processor manuals and extensive testing showed that PPC970+ class processors have hardware assisted handling of unaligned memory accesses, which results in 8 byte memory accesses to be always faster than 4 byte ones
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17 年之前 |
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cpubase.pas
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00d6a03b2c
+ default code now preserves mm registers
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18 年之前 |
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cpuinfo.pas
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2a54d957b2
* fixed two small errors
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19 年之前 |
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cpunode.pas
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c13ff3729b
* Merged 2.3 branch changes:
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18 年之前 |
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cpupara.pas
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22f616d6af
* treat procvardef parameters the same as records (fixes webtbs/tw9141)
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18 年之前 |
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cpupi.pas
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45b7358d81
+ PIC support for darwin/ppc64
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18 年之前 |
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cputarg.pas
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c13ff3729b
* Merged 2.3 branch changes:
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18 年之前 |
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itcpugas.pas
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e0a45eaf28
* r8717 for ppc64 (fixed compilation after r8715)
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18 年之前 |
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nppcadd.pas
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1580e046ed
* fixed missing swapleftright in case of substracting unsigned numbers
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18 年之前 |
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nppccal.pas
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b7fe6797bf
Merged revisions 2921-2922,2925 via svnmerge from
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19 年之前 |
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nppccnv.pas
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6b8aed593f
* remove registers{int/mmx/fpu} from firstpass
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18 年之前 |
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nppcld.pas
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3078a1927f
* remove ttype
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19 年之前 |
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nppcmat.pas
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9adb202a92
* Rework the constexprint to allow operations from low(int64) to high(qword).
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18 年之前 |
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ppcins.dat
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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ppcreg.dat
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de20abf3ec
* cr reg fix for ppc64
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19 年之前 |
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rappc.pas
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b7fe6797bf
Merged revisions 2921-2922,2925 via svnmerge from
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19 年之前 |
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rappcgas.pas
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45b7358d81
+ PIC support for darwin/ppc64
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18 年之前 |
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rppccon.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcdwrf.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcgas.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcgri.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcgss.inc
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de20abf3ec
* cr reg fix for ppc64
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19 年之前 |
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rppcmot.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcmri.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcnor.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcnum.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcrni.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcsri.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcstab.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcstd.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
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rppcsup.inc
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6bf3269b41
* powerpc64 port from Thomas Schatzl
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20 年之前 |
tom_at_work
4e60ceb237
* removed code which splits "unaligned" 8 byte stores/loads into two 4 bytes stores/loads on ppc64. The processor manuals and extensive testing showed that PPC970+ class processors have hardware assisted handling of unaligned memory accesses, which results in 8 byte memory accesses to be always faster than 4 byte ones