popt386.pas 91 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  40. RegUsedAfterInstruction := Reg in UsedRegs
  41. End;
  42. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  43. {First pass of peepholeoptimizations}
  44. Var
  45. l : longint;
  46. p ,hp1, hp2 : pai;
  47. {$ifdef foropt}
  48. hp3, hp4: pai;
  49. {$endif foropt}
  50. TmpBool1, TmpBool2: Boolean;
  51. TmpRef: PReference;
  52. UsedRegs, TmpUsedRegs: TRegSet;
  53. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  54. {skips all labels and returns the next "real" instruction}
  55. Begin
  56. While assigned(hp^.next) and
  57. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  58. hp := pai(hp^.next);
  59. If assigned(hp^.next) Then
  60. Begin
  61. SkipLabels := True;
  62. hp2 := pai(hp^.next)
  63. End
  64. Else
  65. Begin
  66. hp2 := hp;
  67. SkipLabels := False
  68. End;
  69. End;
  70. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  71. {traces sucessive jumps to their final destination and sets it, e.g.
  72. je l1 je l3
  73. <code> <code>
  74. l1: becomes l1:
  75. je l2 je l3
  76. <code> <code>
  77. l2: l2:
  78. jmp l3 jmp l3}
  79. Var p1, p2: pai;
  80. l: pasmlabel;
  81. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  82. Begin
  83. FindAnyLabel := false;
  84. While assigned(hp^.next) and
  85. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  86. hp := pai(hp^.next);
  87. If assigned(hp^.next) and
  88. (pai(hp^.next)^.typ = ait_label) Then
  89. Begin
  90. FindAnyLabel := true;
  91. l := pai_label(hp^.next)^.l;
  92. End
  93. End;
  94. Begin
  95. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  96. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  97. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  98. Begin
  99. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  100. SkipLabels(p1,p1);
  101. If (pai(p1)^.typ = ait_instruction) and
  102. (paicpu(p1)^.is_jmp) Then
  103. If { the next instruction after the label where the jump hp arrives}
  104. { is unconditional or of the same type as hp, so continue }
  105. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  106. { the next instruction after the label where the jump hp arrives}
  107. { is the opposite of hp (so this one is never taken), but after }
  108. { that one there is a branch that will be taken, so perform a }
  109. { little hack: set p1 equal to this instruction (that's what the}
  110. { last SkipLabels is for, only works with short bool evaluation)}
  111. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  112. SkipLabels(p1,p2) and
  113. (p2^.typ = ait_instruction) and
  114. (paicpu(p2)^.is_jmp) and
  115. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  116. SkipLabels(p1,p1)) Then
  117. Begin
  118. GetFinalDestination(asml, paicpu(p1));
  119. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  120. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  121. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  122. End
  123. Else
  124. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  125. if not FindAnyLabel(p1,l) then
  126. begin
  127. {$ifdef finaldestdebug}
  128. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  129. strpnew('previous label inserted'))));
  130. {$endif finaldestdebug}
  131. getlabel(l);
  132. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  133. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  134. hp^.oper[0].sym := l;
  135. inc(l^.refs);
  136. { this won't work, since the new label isn't in the labeltable }
  137. { so it will fail the rangecheck. Labeltable should become a }
  138. { hashtable to support this: }
  139. { GetFinalDestination(asml, hp); }
  140. end
  141. else
  142. begin
  143. {$ifdef finaldestdebug}
  144. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  145. strpnew('next label reused'))));
  146. {$endif finaldestdebug}
  147. inc(l^.refs);
  148. hp^.oper[0].sym := l;
  149. GetFinalDestination(asml, hp);
  150. end;
  151. End;
  152. End;
  153. Function DoSubAddOpt(var p: Pai): Boolean;
  154. Begin
  155. DoSubAddOpt := False;
  156. If GetLastInstruction(p, hp1) And
  157. (hp1^.typ = ait_instruction) And
  158. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  159. Case Paicpu(hp1)^.opcode Of
  160. A_DEC:
  161. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  162. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  163. Begin
  164. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  165. AsmL^.Remove(hp1);
  166. Dispose(hp1, Done)
  167. End;
  168. A_SUB:
  169. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  170. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  171. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  172. Begin
  173. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  174. AsmL^.Remove(hp1);
  175. Dispose(hp1, Done)
  176. End;
  177. A_ADD:
  178. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  179. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  180. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  181. Begin
  182. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  183. AsmL^.Remove(hp1);
  184. Dispose(hp1, Done);
  185. If (Paicpu(p)^.oper[0].val = 0) Then
  186. Begin
  187. hp1 := Pai(p^.next);
  188. AsmL^.Remove(p);
  189. Dispose(p, Done);
  190. If Not GetLastInstruction(hp1, p) Then
  191. p := hp1;
  192. DoSubAddOpt := True;
  193. End
  194. End;
  195. End;
  196. End;
  197. Begin
  198. P := BlockStart;
  199. UsedRegs := [];
  200. While (P <> BlockEnd) Do
  201. Begin
  202. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  203. Case P^.Typ Of
  204. ait_instruction:
  205. Begin
  206. { Handle Jmp Optimizations }
  207. if Paicpu(p)^.is_jmp then
  208. begin
  209. {the following if-block removes all code between a jmp and the next label,
  210. because it can never be executed}
  211. If (paicpu(p)^.opcode = A_JMP) Then
  212. Begin
  213. While GetNextInstruction(p, hp1) and
  214. ((hp1^.typ <> ait_label) or
  215. { skip unused labels, they're not referenced anywhere }
  216. Not(Pai_Label(hp1)^.l^.is_used)) Do
  217. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  218. Begin
  219. AsmL^.Remove(hp1);
  220. Dispose(hp1, done);
  221. End;
  222. End;
  223. If GetNextInstruction(p, hp1) then
  224. Begin
  225. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  226. Begin
  227. hp2:=pai(hp1^.next);
  228. asml^.remove(p);
  229. dispose(p,done);
  230. p:=hp2;
  231. continue;
  232. end
  233. Else
  234. Begin
  235. if hp1^.typ = ait_label then
  236. SkipLabels(hp1,hp1);
  237. If (pai(hp1)^.typ=ait_instruction) and
  238. (paicpu(hp1)^.opcode=A_JMP) and
  239. GetNextInstruction(hp1, hp2) And
  240. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  241. Then
  242. Begin
  243. if paicpu(p)^.opcode=A_Jcc then
  244. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  245. else
  246. begin
  247. If (LabDif <> 0) Then
  248. GetFinalDestination(asml, paicpu(p));
  249. p:=pai(p^.next);
  250. continue;
  251. end;
  252. Dec(pai_label(hp2)^.l^.refs);
  253. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  254. Inc(paicpu(p)^.oper[0].sym^.refs);
  255. asml^.remove(hp1);
  256. dispose(hp1,done);
  257. If (LabDif <> 0) Then
  258. GetFinalDestination(asml, paicpu(p));
  259. end
  260. else
  261. If (LabDif <> 0) Then
  262. GetFinalDestination(asml, paicpu(p));
  263. end;
  264. end
  265. end
  266. else
  267. { All other optimizes }
  268. begin
  269. For l := 0 to 2 Do
  270. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  271. With Paicpu(p)^.oper[l].ref^ Do
  272. Begin
  273. If (base = R_NO) And
  274. (index <> R_NO) And
  275. (scalefactor in [0,1])
  276. Then
  277. Begin
  278. base := index;
  279. index := R_NO
  280. End
  281. End;
  282. Case Paicpu(p)^.opcode Of
  283. A_AND:
  284. Begin
  285. If (Paicpu(p)^.oper[0].typ = top_const) And
  286. (Paicpu(p)^.oper[1].typ = top_reg) And
  287. GetNextInstruction(p, hp1) And
  288. (Pai(hp1)^.typ = ait_instruction) And
  289. (Paicpu(hp1)^.opcode = A_AND) And
  290. (Paicpu(hp1)^.oper[0].typ = top_const) And
  291. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  292. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  293. Then
  294. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  295. Begin
  296. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  297. AsmL^.Remove(hp1);
  298. Dispose(hp1, Done)
  299. End
  300. Else
  301. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  302. jump, but only if it's a conditional jump (PFV) }
  303. If (Paicpu(p)^.oper[1].typ = top_reg) And
  304. GetNextInstruction(p, hp1) And
  305. (hp1^.typ = ait_instruction) And
  306. (Paicpu(hp1)^.is_jmp) and
  307. (Paicpu(hp1)^.opcode<>A_JMP) and
  308. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  309. Paicpu(p)^.opcode := A_TEST;
  310. End;
  311. A_CMP:
  312. Begin
  313. If (Paicpu(p)^.oper[0].typ = top_const) And
  314. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  315. (Paicpu(p)^.oper[0].val = 0) Then
  316. {$ifdef foropt}
  317. If GetNextInstruction(p, hp1) And
  318. (hp1^.typ = ait_instruction) And
  319. (Paicpu(hp1)^.is_jmp) and
  320. (paicpu(hp1)^.opcode=A_Jcc) and
  321. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  322. GetNextInstruction(hp1,hp2) and
  323. (hp2^.typ = ait_instruction) and
  324. (Paicpu(hp2)^.opcode = A_DEC) And
  325. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  326. GetNextInstruction(hp2, hp3) And
  327. (hp3^.typ = ait_instruction) and
  328. (Paicpu(hp3)^.is_jmp) and
  329. (Paicpu(hp3)^.opcode = A_JMP) And
  330. GetNextInstruction(hp3, hp4) And
  331. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  332. Then
  333. Begin
  334. Paicpu(hp2)^.Opcode := A_SUB;
  335. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  336. Paicpu(hp2)^.LoadConst(0,1);
  337. Paicpu(hp2)^.ops:=2;
  338. Paicpu(hp3)^.Opcode := A_Jcc;
  339. Case paicpu(hp1)^.condition of
  340. C_LE: Paicpu(hp3)^.condition := C_GE;
  341. C_BE: Paicpu(hp3)^.condition := C_AE;
  342. End;
  343. AsmL^.Remove(p);
  344. AsmL^.Remove(hp1);
  345. Dispose(p, Done);
  346. Dispose(hp1, Done);
  347. p := hp2;
  348. continue;
  349. End
  350. Else
  351. {$endif foropt}
  352. {change "cmp $0, %reg" to "test %reg, %reg"}
  353. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  354. Begin
  355. Paicpu(p)^.opcode := A_TEST;
  356. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  357. End;
  358. End;
  359. A_FLD:
  360. Begin
  361. If (Paicpu(p)^.oper[0].typ = top_reg) And
  362. GetNextInstruction(p, hp1) And
  363. (hp1^.typ = Ait_Instruction) And
  364. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  365. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  366. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  367. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  368. { change to
  369. fld reg fxxx reg,st
  370. fxxxp st, st1 (hp1)
  371. Remark: non commutative operations must be reversed!
  372. }
  373. begin
  374. Case Paicpu(hp1)^.opcode Of
  375. A_FMULP,A_FADDP,
  376. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  377. begin
  378. Case Paicpu(hp1)^.opcode Of
  379. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  380. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  381. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  382. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  383. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  384. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  385. End;
  386. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  387. Paicpu(hp1)^.oper[1].reg := R_ST;
  388. AsmL^.Remove(p);
  389. Dispose(p, Done);
  390. p := hp1;
  391. Continue;
  392. end;
  393. end;
  394. end
  395. else
  396. If (Paicpu(p)^.oper[0].typ = top_ref) And
  397. GetNextInstruction(p, hp2) And
  398. (hp2^.typ = Ait_Instruction) And
  399. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  400. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  401. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  402. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  403. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  404. If GetLastInstruction(p, hp1) And
  405. (hp1^.typ = Ait_Instruction) And
  406. ((Paicpu(hp1)^.opcode = A_FLD) Or
  407. (Paicpu(hp1)^.opcode = A_FST)) And
  408. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  409. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  410. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  411. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  412. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  413. { change to
  414. fld/fst mem1 (hp1) fld/fst mem1
  415. fld mem1 (p) fadd/
  416. faddp/ fmul st, st
  417. fmulp st, st1 (hp2) }
  418. Begin
  419. AsmL^.Remove(p);
  420. Dispose(p, Done);
  421. p := hp1;
  422. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  423. Paicpu(hp2)^.opcode := A_FADD
  424. Else
  425. Paicpu(hp2)^.opcode := A_FMUL;
  426. Paicpu(hp2)^.oper[1].reg := R_ST;
  427. End
  428. Else
  429. { change to
  430. fld/fst mem1 (hp1) fld/fst mem1
  431. fld mem1 (p) fld st}
  432. Begin
  433. Paicpu(p)^.changeopsize(S_FL);
  434. Paicpu(p)^.loadreg(0,R_ST);
  435. End
  436. Else
  437. Begin
  438. Case Paicpu(hp2)^.opcode Of
  439. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  440. { change to
  441. fld/fst mem1 (hp1) fld/fst mem1
  442. fld mem2 (p) fxxx mem2
  443. fxxxp st, st1 (hp2) }
  444. Begin
  445. Case Paicpu(hp2)^.opcode Of
  446. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  447. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  448. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  449. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  450. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  451. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  452. End;
  453. AsmL^.Remove(hp2);
  454. Dispose(hp2, Done)
  455. End
  456. End
  457. End
  458. End;
  459. A_FSTP,A_FISTP:
  460. Begin
  461. If (Paicpu(p)^.oper[0].typ = top_ref) And
  462. GetNextInstruction(p, hp1) And
  463. (Pai(hp1)^.typ = ait_instruction) And
  464. (((Paicpu(hp1)^.opcode = A_FLD) And
  465. (Paicpu(p)^.opcode = A_FSTP)) Or
  466. ((Paicpu(p)^.opcode = A_FISTP) And
  467. (Paicpu(hp1)^.opcode = A_FILD))) And
  468. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  469. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  470. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  471. Then
  472. Begin
  473. If GetNextInstruction(hp1, hp2) And
  474. (hp2^.typ = ait_instruction) And
  475. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  476. (Paicpu(hp2)^.opcode = A_RET)) And
  477. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  478. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  479. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  480. Then
  481. Begin
  482. AsmL^.Remove(p);
  483. AsmL^.Remove(hp1);
  484. Dispose(p, Done);
  485. Dispose(hp1, Done);
  486. p := hp2;
  487. Continue
  488. End
  489. Else
  490. {fst can't store an extended value!}
  491. If (Paicpu(p)^.opsize <> S_FX) And
  492. (Paicpu(p)^.opsize <> S_IQ) Then
  493. Begin
  494. If (Paicpu(p)^.opcode = A_FSTP) Then
  495. Paicpu(p)^.opcode := A_FST
  496. Else Paicpu(p)^.opcode := A_FIST;
  497. AsmL^.Remove(hp1);
  498. Dispose(hp1, done)
  499. End
  500. End;
  501. End;
  502. A_IMUL:
  503. {changes certain "imul const, %reg"'s to lea sequences}
  504. Begin
  505. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  506. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  507. (Paicpu(p)^.opsize = S_L) Then
  508. If (Paicpu(p)^.oper[0].val = 1) Then
  509. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  510. {remove "imul $1, reg"}
  511. Begin
  512. hp1 := Pai(p^.Next);
  513. AsmL^.Remove(p);
  514. Dispose(p, Done);
  515. p := hp1;
  516. Continue;
  517. End
  518. Else
  519. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  520. Begin
  521. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  522. hp1^.fileinfo := p^.fileinfo;
  523. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  524. Dispose(p, Done);
  525. p := hp1;
  526. End
  527. Else If
  528. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  529. (Paicpu(p)^.oper[2].typ = Top_None)) And
  530. (aktoptprocessor < ClassP6) And
  531. (Paicpu(p)^.oper[0].val <= 12) And
  532. Not(CS_LittleSize in aktglobalswitches) And
  533. (Not(GetNextInstruction(p, hp1)) Or
  534. {GetNextInstruction(p, hp1) And}
  535. Not((Pai(hp1)^.typ = ait_instruction) And
  536. ((paicpu(hp1)^.opcode=A_Jcc) and
  537. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  538. Then
  539. Begin
  540. New(TmpRef);
  541. Reset_reference(tmpref^);
  542. Case Paicpu(p)^.oper[0].val Of
  543. 3: Begin
  544. {imul 3, reg1, reg2 to
  545. lea (reg1,reg1,2), reg2
  546. imul 3, reg1 to
  547. lea (reg1,reg1,2), reg1}
  548. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  549. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  550. TmpRef^.ScaleFactor := 2;
  551. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  552. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  553. Else
  554. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  555. hp1^.fileinfo := p^.fileinfo;
  556. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  557. Dispose(p, Done);
  558. p := hp1;
  559. End;
  560. 5: Begin
  561. {imul 5, reg1, reg2 to
  562. lea (reg1,reg1,4), reg2
  563. imul 5, reg1 to
  564. lea (reg1,reg1,4), reg1}
  565. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  566. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  567. TmpRef^.ScaleFactor := 4;
  568. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  569. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  570. Else
  571. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  572. hp1^.fileinfo:= p^.fileinfo;
  573. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  574. Dispose(p, Done);
  575. p := hp1;
  576. End;
  577. 6: Begin
  578. {imul 6, reg1, reg2 to
  579. lea (,reg1,2), reg2
  580. lea (reg2,reg1,4), reg2
  581. imul 6, reg1 to
  582. lea (reg1,reg1,2), reg1
  583. add reg1, reg1}
  584. If (aktoptprocessor <= Class386)
  585. Then
  586. Begin
  587. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  588. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  589. Then
  590. Begin
  591. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  592. TmpRef^.ScaleFactor := 4;
  593. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  594. End
  595. Else
  596. Begin
  597. Dispose(TmpRef);
  598. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  599. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  600. End;
  601. hp1^.fileinfo := p^.fileinfo;
  602. InsertLLItem(AsmL,p, p^.next, hp1);
  603. New(TmpRef);
  604. Reset_reference(tmpref^);
  605. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  606. TmpRef^.ScaleFactor := 2;
  607. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  608. Then
  609. Begin
  610. TmpRef^.base := R_NO;
  611. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  612. Paicpu(p)^.oper[2].reg));
  613. End
  614. Else
  615. Begin
  616. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  617. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  618. End;
  619. hp1^.fileinfo := p^.fileinfo;
  620. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  621. Dispose(p, Done);
  622. p := Pai(hp1^.next);
  623. End
  624. Else Dispose(TmpRef);
  625. End;
  626. 9: Begin
  627. {imul 9, reg1, reg2 to
  628. lea (reg1,reg1,8), reg2
  629. imul 9, reg1 to
  630. lea (reg1,reg1,8), reg1}
  631. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  632. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  633. TmpRef^.ScaleFactor := 8;
  634. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  635. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  636. Else
  637. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  638. hp1^.fileinfo := p^.fileinfo;
  639. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  640. Dispose(p, Done);
  641. p := hp1;
  642. End;
  643. 10: Begin
  644. {imul 10, reg1, reg2 to
  645. lea (reg1,reg1,4), reg2
  646. add reg2, reg2
  647. imul 10, reg1 to
  648. lea (reg1,reg1,4), reg1
  649. add reg1, reg1}
  650. If (aktoptprocessor <= Class386) Then
  651. Begin
  652. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  653. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  654. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  655. Else
  656. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  657. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  658. hp1^.fileinfo := p^.fileinfo;
  659. InsertLLItem(AsmL,p, p^.next, hp1);
  660. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  661. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  662. TmpRef^.ScaleFactor := 4;
  663. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  664. Then
  665. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg))
  666. Else
  667. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  668. hp1^.fileinfo := p^.fileinfo;
  669. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  670. Dispose(p, Done);
  671. p := Pai(hp1^.next);
  672. End
  673. Else Dispose(TmpRef);
  674. End;
  675. 12: Begin
  676. {imul 12, reg1, reg2 to
  677. lea (,reg1,4), reg2
  678. lea (,reg1,8) reg2
  679. imul 12, reg1 to
  680. lea (reg1,reg1,2), reg1
  681. lea (,reg1,4), reg1}
  682. If (aktoptprocessor <= Class386)
  683. Then
  684. Begin
  685. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  686. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  687. Begin
  688. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  689. TmpRef^.ScaleFactor := 8;
  690. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  691. End
  692. Else
  693. Begin
  694. TmpRef^.base := R_NO;
  695. TmpRef^.ScaleFactor := 4;
  696. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  697. End;
  698. hp1^.fileinfo := p^.fileinfo;
  699. InsertLLItem(AsmL,p, p^.next, hp1);
  700. New(TmpRef);
  701. Reset_reference(tmpref^);
  702. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  703. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  704. Begin
  705. TmpRef^.base := R_NO;
  706. TmpRef^.ScaleFactor := 4;
  707. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  708. End
  709. Else
  710. Begin
  711. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  712. TmpRef^.ScaleFactor := 2;
  713. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  714. End;
  715. hp1^.fileinfo := p^.fileinfo;
  716. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  717. Dispose(p, Done);
  718. p := Pai(hp1^.next);
  719. End
  720. Else Dispose(TmpRef);
  721. End
  722. Else Dispose(TmpRef);
  723. End;
  724. End;
  725. End;
  726. A_LEA:
  727. Begin
  728. {removes seg register prefixes from LEA operations, as they
  729. don't do anything}
  730. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  731. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  732. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  733. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  734. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  735. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  736. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  737. Then
  738. Begin
  739. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  740. Paicpu(p)^.oper[1].reg));
  741. hp1^.fileinfo := p^.fileinfo;
  742. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  743. Dispose(p, Done);
  744. p := hp1;
  745. Continue;
  746. End
  747. Else
  748. Begin
  749. hp1 := Pai(p^.Next);
  750. AsmL^.Remove(p);
  751. Dispose(p, Done);
  752. p := hp1;
  753. Continue;
  754. End;
  755. End;
  756. A_MOV:
  757. Begin
  758. TmpUsedRegs := UsedRegs;
  759. If (Paicpu(p)^.oper[1].typ = top_reg) And
  760. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  761. GetNextInstruction(p, hp1) And
  762. (Pai(hp1)^.typ = ait_instruction) And
  763. (Paicpu(hp1)^.opcode = A_MOV) And
  764. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  765. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  766. Then
  767. {we have "mov x, %treg; mov %treg, y}
  768. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  769. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  770. Case Paicpu(p)^.oper[0].typ Of
  771. top_reg:
  772. Begin
  773. { change "mov %reg, %treg; mov %treg, y"
  774. to "mov %reg, y" }
  775. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  776. AsmL^.Remove(p);
  777. Dispose(p, Done);
  778. p := hp1;
  779. continue;
  780. End;
  781. top_ref:
  782. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  783. Begin
  784. { change "mov mem, %treg; mov %treg, %reg"
  785. to "mov mem, %reg" }
  786. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  787. AsmL^.Remove(hp1);
  788. Dispose(hp1, Done);
  789. continue;
  790. End;
  791. End
  792. Else
  793. {remove an instruction which never makes sense: we've got
  794. "mov mem, %reg1; mov %reg1, %edi" and then EDI isn't used anymore!}
  795. { Begin
  796. If (Paicpu(hp1)^.oper[1].reg = R_EDI) And
  797. Not(GetNextInstruction(hp1, hp2) And
  798. (Pai(hp2)^.typ = ait_instruction) And
  799. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  800. (Paicpu(hp2)^.oper[1] = Pointer(R_ESI))) Then
  801. Begin
  802. AsmL^.Remove(hp1);
  803. Dispose(hp1, Done);
  804. Continue;
  805. End
  806. End}
  807. Else
  808. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  809. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  810. penalty}
  811. If (Paicpu(p)^.oper[0].typ = top_reg) And
  812. (Paicpu(p)^.oper[1].typ = top_reg) And
  813. GetNextInstruction(p,hp1) And
  814. (Pai(hp1)^.typ = ait_instruction) And
  815. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  816. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  817. Then
  818. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  819. Begin
  820. If ((Paicpu(hp1)^.opcode = A_OR) Or
  821. (Paicpu(hp1)^.opcode = A_TEST)) And
  822. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  823. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  824. Then
  825. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  826. Begin
  827. TmpUsedRegs := UsedRegs;
  828. If GetNextInstruction(hp1, hp2) And
  829. (hp2^.typ = ait_instruction) And
  830. paicpu(hp2)^.is_jmp and
  831. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  832. Then
  833. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  834. "test %reg1, %reg1; jxx"}
  835. Begin
  836. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  837. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  838. AsmL^.Remove(p);
  839. Dispose(p, done);
  840. p := hp1;
  841. continue
  842. End
  843. Else
  844. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  845. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  846. Begin
  847. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  848. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  849. End;
  850. End
  851. { Else
  852. If (Paicpu(p^.next)^.opcode
  853. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  854. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  855. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  856. End
  857. Else
  858. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  859. x >= RetOffset) as it doesn't do anything (it writes either to a
  860. parameter or to the temporary storage room for the function
  861. result)}
  862. If GetNextInstruction(p, hp1) And
  863. (Pai(hp1)^.typ = ait_instruction)
  864. Then
  865. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  866. (Paicpu(hp1)^.opcode = A_RET)) And
  867. (Paicpu(p)^.oper[1].typ = top_ref) And
  868. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  869. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  870. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  871. (Paicpu(p)^.oper[0].typ = top_reg)
  872. Then
  873. Begin
  874. AsmL^.Remove(p);
  875. Dispose(p, done);
  876. p := hp1;
  877. End
  878. Else
  879. If (Paicpu(p)^.oper[0].typ = top_reg) And
  880. (Paicpu(p)^.oper[1].typ = top_ref) And
  881. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  882. (Paicpu(hp1)^.opcode = A_CMP) And
  883. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  884. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  885. Then
  886. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  887. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  888. { Next instruction is also a MOV ? }
  889. If GetNextInstruction(p, hp1) And
  890. (pai(hp1)^.typ = ait_instruction) and
  891. (Paicpu(hp1)^.opcode = A_MOV) and
  892. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  893. Then
  894. Begin
  895. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  896. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  897. Then
  898. {mov reg1, mem1 or mov mem1, reg1
  899. mov mem2, reg2 mov reg2, mem2}
  900. Begin
  901. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  902. {mov reg1, mem1 or mov mem1, reg1
  903. mov mem2, reg1 mov reg2, mem1}
  904. Begin
  905. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  906. { Removes the second statement from
  907. mov reg1, mem1
  908. mov mem1, reg1 }
  909. Begin
  910. AsmL^.remove(hp1);
  911. Dispose(hp1,done);
  912. End
  913. Else
  914. Begin
  915. TmpUsedRegs := UsedRegs;
  916. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  917. If (Paicpu(p)^.oper[0].typ = top_reg) And
  918. { mov reg1, mem1
  919. mov mem2, reg1 }
  920. GetNextInstruction(hp1, hp2) And
  921. (hp2^.typ = ait_instruction) And
  922. (Paicpu(hp2)^.opcode = A_CMP) And
  923. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  924. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  925. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  926. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  927. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  928. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  929. { change to
  930. mov reg1, mem1 mov reg1, mem1
  931. mov mem2, reg1 cmp reg1, mem2
  932. cmp mem1, reg1 }
  933. Begin
  934. AsmL^.Remove(hp2);
  935. Dispose(hp2, Done);
  936. Paicpu(hp1)^.opcode := A_CMP;
  937. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  938. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  939. End;
  940. End;
  941. End
  942. Else
  943. Begin
  944. If GetNextInstruction(hp1, hp2) And
  945. (Paicpu(p)^.oper[0].typ = top_ref) And
  946. (Paicpu(p)^.oper[1].typ = top_reg) And
  947. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  948. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  949. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  950. (Pai(hp2)^.typ = ait_instruction) And
  951. (Paicpu(hp2)^.opcode = A_MOV) And
  952. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  953. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  954. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  955. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^)
  956. Then
  957. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI])
  958. Then
  959. { mov mem1, %edi
  960. mov %edi, mem2
  961. mov mem2, reg2
  962. to:
  963. mov mem1, reg2
  964. mov reg2, mem2}
  965. Begin
  966. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  967. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  968. AsmL^.Remove(hp2);
  969. Dispose(hp2,Done);
  970. End
  971. Else
  972. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  973. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  974. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  975. Then
  976. { mov mem1, reg1 mov mem1, reg1
  977. mov reg1, mem2 mov reg1, mem2
  978. mov mem2, reg2 mov mem2, reg1
  979. to: to:
  980. mov mem1, reg1 mov mem1, reg1
  981. mov mem1, reg2 mov reg1, mem2
  982. mov reg1, mem2
  983. or (if mem1 depends on reg1
  984. and/or if mem2 depends on reg2)
  985. to:
  986. mov mem1, reg1
  987. mov reg1, mem2
  988. mov reg1, reg2
  989. }
  990. Begin
  991. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  992. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  993. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  994. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  995. End
  996. Else
  997. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  998. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  999. Else
  1000. Begin
  1001. AsmL^.Remove(hp2);
  1002. Dispose(hp2, Done);
  1003. End
  1004. End;
  1005. End
  1006. Else
  1007. (* {movl [mem1],reg1
  1008. movl [mem1],reg2
  1009. to:
  1010. movl [mem1],reg1
  1011. movl reg1,reg2 }
  1012. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1013. (Paicpu(p)^.oper[1].typ = top_reg) and
  1014. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1015. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1016. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1017. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1018. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1019. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1020. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1021. Else*)
  1022. { movl const1,[mem1]
  1023. movl [mem1],reg1
  1024. to:
  1025. movl const1,reg1
  1026. movl reg1,[mem1] }
  1027. If (Paicpu(p)^.oper[0].typ = top_const) and
  1028. (Paicpu(p)^.oper[1].typ = top_ref) and
  1029. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1030. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1031. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1032. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1033. Begin
  1034. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1035. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1036. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1037. End
  1038. End;
  1039. End;
  1040. A_MOVZX:
  1041. Begin
  1042. {removes superfluous And's after movzx's}
  1043. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1044. GetNextInstruction(p, hp1) And
  1045. (Pai(hp1)^.typ = ait_instruction) And
  1046. (Paicpu(hp1)^.opcode = A_AND) And
  1047. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1048. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1049. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1050. Then
  1051. Case Paicpu(p)^.opsize Of
  1052. S_BL, S_BW:
  1053. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1054. Begin
  1055. AsmL^.Remove(hp1);
  1056. Dispose(hp1, Done);
  1057. End;
  1058. S_WL:
  1059. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1060. Begin
  1061. AsmL^.Remove(hp1);
  1062. Dispose(hp1, Done);
  1063. End;
  1064. End;
  1065. {changes some movzx constructs to faster synonims (all examples
  1066. are given with eax/ax, but are also valid for other registers)}
  1067. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1068. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1069. Case Paicpu(p)^.opsize of
  1070. S_BW:
  1071. Begin
  1072. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1073. Not(CS_LittleSize In aktglobalswitches)
  1074. Then
  1075. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1076. Begin
  1077. Paicpu(p)^.opcode := A_AND;
  1078. Paicpu(p)^.changeopsize(S_W);
  1079. Paicpu(p)^.LoadConst(0,$ff);
  1080. End
  1081. Else
  1082. If GetNextInstruction(p, hp1) And
  1083. (Pai(hp1)^.typ = ait_instruction) And
  1084. (Paicpu(hp1)^.opcode = A_AND) And
  1085. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1086. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1087. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1088. Then
  1089. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1090. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1091. Begin
  1092. Paicpu(p)^.opcode := A_MOV;
  1093. Paicpu(p)^.changeopsize(S_W);
  1094. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1095. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1096. End;
  1097. End;
  1098. S_BL:
  1099. Begin
  1100. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1101. Not(CS_LittleSize in aktglobalswitches)
  1102. Then
  1103. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1104. Begin
  1105. Paicpu(p)^.opcode := A_AND;
  1106. Paicpu(p)^.changeopsize(S_L);
  1107. Paicpu(p)^.loadconst(0,$ff)
  1108. End
  1109. Else
  1110. If GetNextInstruction(p, hp1) And
  1111. (Pai(hp1)^.typ = ait_instruction) And
  1112. (Paicpu(hp1)^.opcode = A_AND) And
  1113. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1114. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1115. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1116. Then
  1117. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1118. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1119. Begin
  1120. Paicpu(p)^.opcode := A_MOV;
  1121. Paicpu(p)^.changeopsize(S_L);
  1122. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1123. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1124. End
  1125. End;
  1126. S_WL:
  1127. Begin
  1128. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1129. Not(CS_LittleSize In aktglobalswitches)
  1130. Then
  1131. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1132. Begin
  1133. Paicpu(p)^.opcode := A_AND;
  1134. Paicpu(p)^.changeopsize(S_L);
  1135. Paicpu(p)^.LoadConst(0,$ffff);
  1136. End
  1137. Else
  1138. If GetNextInstruction(p, hp1) And
  1139. (Pai(hp1)^.typ = ait_instruction) And
  1140. (Paicpu(hp1)^.opcode = A_AND) And
  1141. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1142. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1143. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1144. Then
  1145. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1146. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1147. Begin
  1148. Paicpu(p)^.opcode := A_MOV;
  1149. Paicpu(p)^.changeopsize(S_L);
  1150. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1151. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1152. End;
  1153. End;
  1154. End
  1155. Else
  1156. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1157. Begin
  1158. If GetNextInstruction(p, hp1) And
  1159. (Pai(hp1)^.typ = ait_instruction) And
  1160. (Paicpu(hp1)^.opcode = A_AND) And
  1161. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1162. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1163. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1164. Begin
  1165. Paicpu(p)^.opcode := A_MOV;
  1166. Case Paicpu(p)^.opsize Of
  1167. S_BL:
  1168. Begin
  1169. Paicpu(p)^.changeopsize(S_L);
  1170. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1171. End;
  1172. S_WL:
  1173. Begin
  1174. Paicpu(p)^.changeopsize(S_L);
  1175. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1176. End;
  1177. S_BW:
  1178. Begin
  1179. Paicpu(p)^.changeopsize(S_W);
  1180. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1181. End;
  1182. End;
  1183. End;
  1184. End;
  1185. End;
  1186. A_POP:
  1187. Begin
  1188. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1189. GetNextInstruction(p, hp1) And
  1190. (pai(hp1)^.typ=ait_instruction) and
  1191. (Paicpu(hp1)^.opcode=A_PUSH) and
  1192. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1193. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1194. { This can't be done, because the register which is popped
  1195. can still be used after the push (PFV)
  1196. If (Not(cs_regalloc in aktglobalswitches)) Then
  1197. Begin
  1198. hp2:=pai(hp1^.next);
  1199. asml^.remove(p);
  1200. asml^.remove(hp1);
  1201. dispose(p,done);
  1202. dispose(hp1,done);
  1203. p:=hp2;
  1204. continue
  1205. End
  1206. Else }
  1207. Begin
  1208. { change it to a two op operation }
  1209. Paicpu(p)^.oper[1].typ:=top_none;
  1210. Paicpu(p)^.ops:=2;
  1211. Paicpu(p)^.opcode := A_MOV;
  1212. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1213. New(TmpRef);
  1214. Reset_reference(tmpref^);
  1215. TmpRef^.base := R_ESP;
  1216. Paicpu(p)^.LoadRef(0,TmpRef);
  1217. AsmL^.Remove(hp1);
  1218. Dispose(hp1, Done)
  1219. End;
  1220. end;
  1221. A_PUSH:
  1222. Begin
  1223. If (Paicpu(p)^.opsize = S_W) And
  1224. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1225. GetNextInstruction(p, hp1) And
  1226. (Pai(hp1)^.typ = ait_instruction) And
  1227. (Paicpu(hp1)^.opcode = A_PUSH) And
  1228. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1229. (Paicpu(hp1)^.opsize = S_W) Then
  1230. Begin
  1231. Paicpu(p)^.changeopsize(S_L);
  1232. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + Paicpu(hp1)^.oper[0].val);
  1233. AsmL^.Remove(hp1);
  1234. Dispose(hp1, Done)
  1235. End;
  1236. End;
  1237. A_SHL, A_SAL:
  1238. Begin
  1239. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1240. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1241. (Paicpu(p)^.opsize = S_L) And
  1242. (Paicpu(p)^.oper[0].val <= 3)
  1243. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1244. Then
  1245. Begin
  1246. TmpBool1 := True; {should we check the next instruction?}
  1247. TmpBool2 := False; {have we found an add/sub which could be
  1248. integrated in the lea?}
  1249. New(TmpRef);
  1250. Reset_reference(tmpref^);
  1251. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1252. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1253. While TmpBool1 And
  1254. GetNextInstruction(p, hp1) And
  1255. (Pai(hp1)^.typ = ait_instruction) And
  1256. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1257. (Paicpu(hp1)^.opcode = A_SUB)) And
  1258. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1259. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1260. Begin
  1261. TmpBool1 := False;
  1262. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1263. Then
  1264. Begin
  1265. TmpBool1 := True;
  1266. TmpBool2 := True;
  1267. If Paicpu(hp1)^.opcode = A_ADD Then
  1268. Inc(TmpRef^.offset, Paicpu(hp1)^.oper[0].val)
  1269. Else
  1270. Dec(TmpRef^.offset, Paicpu(hp1)^.oper[0].val);
  1271. AsmL^.Remove(hp1);
  1272. Dispose(hp1, Done);
  1273. End
  1274. Else
  1275. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1276. (Paicpu(hp1)^.opcode = A_ADD) And
  1277. (TmpRef^.base = R_NO) Then
  1278. Begin
  1279. TmpBool1 := True;
  1280. TmpBool2 := True;
  1281. TmpRef^.base := Paicpu(hp1)^.oper[0].reg;
  1282. AsmL^.Remove(hp1);
  1283. Dispose(hp1, Done);
  1284. End;
  1285. End;
  1286. If TmpBool2 Or
  1287. ((aktoptprocessor < ClassP6) And
  1288. (Paicpu(p)^.oper[0].val <= 3) And
  1289. Not(CS_LittleSize in aktglobalswitches))
  1290. Then
  1291. Begin
  1292. If Not(TmpBool2) And
  1293. (Paicpu(p)^.oper[0].val = 1)
  1294. Then
  1295. Begin
  1296. Dispose(TmpRef);
  1297. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1298. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1299. End
  1300. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  1301. Paicpu(p)^.oper[1].reg));
  1302. hp1^.fileinfo := p^.fileinfo;
  1303. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1304. Dispose(p, Done);
  1305. p := hp1;
  1306. End;
  1307. End
  1308. Else
  1309. If (aktoptprocessor < ClassP6) And
  1310. (Paicpu(p)^.oper[0].typ = top_const) And
  1311. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1312. If (Paicpu(p)^.oper[0].val = 1)
  1313. Then
  1314. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1315. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1316. (unlike shl, which is only pairable in the U pipe)}
  1317. Begin
  1318. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1319. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1320. hp1^.fileinfo := p^.fileinfo;
  1321. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1322. Dispose(p, done);
  1323. p := hp1;
  1324. End
  1325. Else If (Paicpu(p)^.opsize = S_L) and
  1326. (Paicpu(p)^.oper[0].val<= 3) Then
  1327. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1328. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1329. Begin
  1330. New(TmpRef);
  1331. Reset_reference(tmpref^);
  1332. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1333. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1334. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,TmpRef, Paicpu(p)^.oper[1].reg));
  1335. hp1^.fileinfo := p^.fileinfo;
  1336. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1337. Dispose(p, done);
  1338. p := hp1;
  1339. End
  1340. End;
  1341. A_SAR, A_SHR:
  1342. {changes the code sequence
  1343. shr/sar const1, x
  1344. shl const2, x
  1345. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1346. Begin
  1347. If GetNextInstruction(p, hp1) And
  1348. (pai(hp1)^.typ = ait_instruction) and
  1349. (Paicpu(hp1)^.opcode = A_SHL) and
  1350. (Paicpu(p)^.oper[0].typ = top_const) and
  1351. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1352. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1353. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1354. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1355. Then
  1356. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1357. Not(CS_LittleSize In aktglobalswitches)
  1358. Then
  1359. { shr/sar const1, %reg
  1360. shl const2, %reg
  1361. with const1 > const2 }
  1362. Begin
  1363. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1364. Paicpu(hp1)^.opcode := A_AND;
  1365. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1366. Case Paicpu(p)^.opsize Of
  1367. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1368. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1369. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1370. End;
  1371. End
  1372. Else
  1373. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1374. Not(CS_LittleSize In aktglobalswitches)
  1375. Then
  1376. { shr/sar const1, %reg
  1377. shl const2, %reg
  1378. with const1 < const2 }
  1379. Begin
  1380. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1381. Paicpu(p)^.opcode := A_AND;
  1382. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1383. Case Paicpu(p)^.opsize Of
  1384. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1385. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1386. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1387. End;
  1388. End
  1389. Else
  1390. { shr/sar const1, %reg
  1391. shl const2, %reg
  1392. with const1 = const2 }
  1393. Begin
  1394. Paicpu(p)^.opcode := A_AND;
  1395. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1396. Case Paicpu(p)^.opsize Of
  1397. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1398. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1399. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1400. End;
  1401. AsmL^.remove(hp1);
  1402. dispose(hp1, done);
  1403. End;
  1404. End;
  1405. A_SETcc :
  1406. Begin
  1407. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1408. GetNextInstruction(p, hp1) And
  1409. GetNextInstruction(hp1, hp2) And
  1410. (hp2^.typ = ait_instruction) And
  1411. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1412. (Paicpu(hp2)^.opcode = A_RET)) And
  1413. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1414. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1415. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1416. (hp1^.typ = ait_instruction) And
  1417. (Paicpu(hp1)^.opcode = A_MOV) And
  1418. (Paicpu(hp1)^.opsize = S_B) And
  1419. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1420. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1421. Begin
  1422. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1423. AsmL^.Remove(hp1);
  1424. Dispose(hp1, Done)
  1425. End
  1426. End;
  1427. A_SUB:
  1428. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1429. { * change "sub/add const1, reg" or "dec reg" followed by
  1430. "sub const2, reg" to one "sub ..., reg" }
  1431. Begin
  1432. If (Paicpu(p)^.oper[0].typ = top_const) And
  1433. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1434. If (Paicpu(p)^.oper[0].val = 2) And
  1435. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1436. Begin
  1437. hp1 := Pai(p^.next);
  1438. While Assigned(hp1) And
  1439. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1440. Not((Pai(hp1)^.typ = ait_instruction) And
  1441. ((Paicpu(hp1)^.opcode = A_CALL) or
  1442. (Paicpu(hp1)^.opcode = A_PUSH) or
  1443. ((Paicpu(hp1)^.opcode = A_MOV) And
  1444. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1445. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1446. hp1 := Pai(hp1^.next);
  1447. If Assigned(hp1) And
  1448. (Pai(hp1)^.typ = ait_instruction) And
  1449. (Paicpu(hp1)^.opcode = A_PUSH) And
  1450. (Paicpu(hp1)^.opsize = S_W)
  1451. Then
  1452. Begin
  1453. Paicpu(hp1)^.changeopsize(S_L);
  1454. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1455. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1456. hp1 := Pai(p^.next);
  1457. AsmL^.Remove(p);
  1458. Dispose(p, Done);
  1459. p := hp1;
  1460. Continue
  1461. End;
  1462. If DoSubAddOpt(p) Then continue;
  1463. End
  1464. Else If DoSubAddOpt(p) Then Continue
  1465. End;
  1466. A_TEST, A_OR:
  1467. {removes the line marked with (x) from the sequence
  1468. And/or/xor/add/sub/... $x, %y
  1469. test/or %y, %y (x)
  1470. j(n)z _Label
  1471. as the first instruction already adjusts the ZF}
  1472. Begin
  1473. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1474. If GetLastInstruction(p, hp1) And
  1475. (pai(hp1)^.typ = ait_instruction) Then
  1476. Case Paicpu(hp1)^.opcode Of
  1477. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1478. Begin
  1479. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1480. Begin
  1481. hp1 := pai(p^.next);
  1482. asml^.remove(p);
  1483. dispose(p, done);
  1484. p := pai(hp1);
  1485. continue
  1486. End;
  1487. End;
  1488. A_DEC, A_INC, A_NEG:
  1489. Begin
  1490. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1491. Begin
  1492. Case Paicpu(hp1)^.opcode Of
  1493. A_DEC, A_INC:
  1494. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1495. Begin
  1496. Case Paicpu(hp1)^.opcode Of
  1497. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1498. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1499. End;
  1500. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1501. Paicpu(hp1)^.LoadConst(0,1);
  1502. Paicpu(hp1)^.ops:=2;
  1503. End
  1504. End;
  1505. hp1 := pai(p^.next);
  1506. asml^.remove(p);
  1507. dispose(p, done);
  1508. p := pai(hp1);
  1509. continue
  1510. End;
  1511. End
  1512. End
  1513. Else
  1514. End;
  1515. A_XOR:
  1516. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1517. (Paicpu(p)^.oper[1].typ = top_reg) And
  1518. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1519. { temporarily change this to 'mov reg,0' to make it easier }
  1520. { for the CSE. Will be changed back in pass 2 }
  1521. begin
  1522. paicpu(p)^.opcode := A_MOV;
  1523. paicpu(p)^.loadconst(0,0);
  1524. end;
  1525. End;
  1526. end; { if is_jmp }
  1527. End;
  1528. { ait_label:
  1529. Begin
  1530. If Not(Pai_Label(p)^.l^.is_used)
  1531. Then
  1532. Begin
  1533. hp1 := Pai(p^.next);
  1534. AsmL^.Remove(p);
  1535. Dispose(p, Done);
  1536. p := hp1;
  1537. Continue
  1538. End;
  1539. End;}
  1540. End;
  1541. p:=pai(p^.next);
  1542. end;
  1543. end;
  1544. {$ifdef foldArithOps}
  1545. Function IsArithOp(opcode: TAsmOp): Boolean;
  1546. Begin
  1547. IsArithOp := False;
  1548. Case opcode Of
  1549. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1550. End;
  1551. End;
  1552. {$endif foldArithOps}
  1553. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1554. var
  1555. p,hp1,hp2: pai;
  1556. {$ifdef foldArithOps}
  1557. UsedRegs, TmpUsedRegs: TRegSet;
  1558. {$endif foldArithOps}
  1559. Begin
  1560. P := BlockStart;
  1561. {$ifdef foldArithOps}
  1562. UsedRegs := [];
  1563. {$endif foldArithOps}
  1564. While (P <> BlockEnd) Do
  1565. Begin
  1566. {$ifdef foldArithOps}
  1567. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1568. {$endif foldArithOps}
  1569. Case P^.Typ Of
  1570. Ait_Instruction:
  1571. Begin
  1572. Case Paicpu(p)^.opcode Of
  1573. A_CALL:
  1574. If (AktOptProcessor < ClassP6) And
  1575. GetNextInstruction(p, hp1) And
  1576. (hp1^.typ = ait_instruction) And
  1577. (paicpu(hp1)^.opcode = A_JMP) Then
  1578. Begin
  1579. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1580. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1581. hp2^.fileinfo := p^.fileinfo;
  1582. InsertLLItem(AsmL, p^.previous, p, hp2);
  1583. Paicpu(p)^.opcode := A_JMP;
  1584. AsmL^.Remove(hp1);
  1585. Dispose(hp1, Done)
  1586. End;
  1587. A_MOV:
  1588. Begin
  1589. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1590. (Paicpu(p)^.oper[1].typ = top_reg) And
  1591. GetNextInstruction(p, hp1) And
  1592. (hp1^.typ = ait_Instruction) And
  1593. ((Paicpu(hp1)^.opcode = A_MOV) or
  1594. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1595. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1596. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1597. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1598. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1599. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1600. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1601. {mov reg1, reg2
  1602. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1603. Begin
  1604. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1605. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1606. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1607. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1608. AsmL^.Remove(p);
  1609. Dispose(p, Done);
  1610. p := hp1;
  1611. Continue;
  1612. End
  1613. {$ifdef foldArithOps}
  1614. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1615. GetNextInstruction(p,hp1) And
  1616. (hp1^.typ = ait_instruction) And
  1617. IsArithOp(Paicpu(hp1)^.opcode) And
  1618. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1619. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1620. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1621. GetNextInstruction(hp1,hp2) And
  1622. (hp2^.typ = ait_instruction) And
  1623. (Paicpu(hp2)^.opcode = A_MOV) And
  1624. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1625. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1626. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1627. Begin
  1628. TmpUsedRegs := UsedRegs;
  1629. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1630. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1631. Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
  1632. hp2, TmpUsedRegs)))
  1633. Then
  1634. { change mov (ref), reg }
  1635. { add/sub/or/... reg2/$const, reg }
  1636. { mov (reg), ref }
  1637. { # relaese reg }
  1638. { to add/sub/or/... reg2/$const, (ref) }
  1639. Begin
  1640. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1641. AsmL^.Remove(p);
  1642. AsmL^.Remove(hp2);
  1643. Dispose(p,done);
  1644. Dispose(hp2,Done);
  1645. p := hp1
  1646. End;
  1647. End
  1648. {$endif foldArithOps}
  1649. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1650. (Paicpu(p)^.oper[0].val = 0) And
  1651. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1652. { change "mov $0, %reg" into "xor %reg, %reg" }
  1653. Begin
  1654. Paicpu(p)^.opcode := A_XOR;
  1655. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1656. End
  1657. End;
  1658. A_MOVZX:
  1659. Begin
  1660. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1661. If (Paicpu(p)^.oper[0].typ = top_reg)
  1662. Then
  1663. Case Paicpu(p)^.opsize of
  1664. S_BL:
  1665. Begin
  1666. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1667. Not(CS_LittleSize in aktglobalswitches) And
  1668. (aktoptprocessor = ClassP5)
  1669. Then
  1670. {Change "movzbl %reg1, %reg2" to
  1671. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1672. PentiumMMX}
  1673. Begin
  1674. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1675. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1676. hp1^.fileinfo := p^.fileinfo;
  1677. InsertLLItem(AsmL,p^.previous, p, hp1);
  1678. Paicpu(p)^.opcode := A_MOV;
  1679. Paicpu(p)^.changeopsize(S_B);
  1680. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1681. End;
  1682. End;
  1683. End
  1684. Else
  1685. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1686. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1687. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1688. Not(CS_LittleSize in aktglobalswitches) And
  1689. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1690. (aktoptprocessor = ClassP5) And
  1691. (Paicpu(p)^.opsize = S_BL)
  1692. Then
  1693. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1694. Pentium and PentiumMMX}
  1695. Begin
  1696. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1697. Paicpu(p)^.oper[1].reg));
  1698. hp1^.fileinfo := p^.fileinfo;
  1699. Paicpu(p)^.opcode := A_MOV;
  1700. Paicpu(p)^.changeopsize(S_B);
  1701. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1702. InsertLLItem(AsmL,p^.previous, p, hp1);
  1703. End;
  1704. End;
  1705. End;
  1706. End;
  1707. End;
  1708. p := Pai(p^.next)
  1709. End;
  1710. End;
  1711. End.
  1712. {
  1713. $Log$
  1714. Revision 1.76 2000-01-07 01:14:30 peter
  1715. * updated copyright to 2000
  1716. Revision 1.75 1999/12/30 17:56:44 peter
  1717. * fixed and;jmp being translated into test;jmp
  1718. Revision 1.74 1999/12/05 16:48:43 jonas
  1719. * CSE of constant loading in regs works properly again
  1720. + if a constant is stored into memory using "mov const, ref" and
  1721. there is a reg that contains this const, it is changed into
  1722. "mov reg, ref"
  1723. Revision 1.73 1999/12/02 11:26:41 peter
  1724. * newoptimizations define added
  1725. Revision 1.72 1999/11/30 10:40:45 peter
  1726. + ttype, tsymlist
  1727. Revision 1.71 1999/11/27 23:47:55 jonas
  1728. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1729. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1730. Enable with -dfoldArithOps
  1731. Revision 1.70 1999/11/21 13:09:41 jonas
  1732. * fixed some missed optimizations because 8bit regs were not always
  1733. taken into account
  1734. Revision 1.69 1999/11/13 19:03:56 jonas
  1735. * don't remove align objects between JMP's and labels
  1736. Revision 1.68 1999/11/06 16:24:00 jonas
  1737. * getfinaldestination works completely again (a lot of functionality
  1738. got lost in the conversion resulting from the removal of
  1739. ait_labeled_instruction)
  1740. Revision 1.67 1999/11/06 14:34:23 peter
  1741. * truncated log to 20 revs
  1742. Revision 1.66 1999/09/27 23:44:55 peter
  1743. * procinfo is now a pointer
  1744. * support for result setting in sub procedure
  1745. Revision 1.65 1999/09/05 14:27:19 florian
  1746. + fld reg;fxxx to fxxxr reg optimization
  1747. Revision 1.64 1999/08/25 12:00:02 jonas
  1748. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1749. Revision 1.63 1999/08/23 10:20:46 jonas
  1750. * fixed pop/push optmization
  1751. Revision 1.62 1999/08/10 12:30:00 pierre
  1752. * avoid unused locals
  1753. Revision 1.61 1999/08/05 15:02:48 jonas
  1754. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1755. Revision 1.60 1999/08/04 00:23:16 florian
  1756. * renamed i386asm and i386base to cpuasm and cpubase
  1757. Revision 1.59 1999/08/03 17:13:28 jonas
  1758. * fix for sar/shr-shl optimization
  1759. Revision 1.58 1999/07/30 18:17:55 jonas
  1760. * fix so (,reg) gets optimized to (reg)
  1761. Revision 1.57 1999/07/01 18:12:16 jonas
  1762. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1763. a movzx or movsx
  1764. Revision 1.56 1999/06/23 12:33:52 jonas
  1765. * merged
  1766. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1767. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1768. Revision 1.55 1999/06/18 09:55:31 peter
  1769. * merged
  1770. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1771. * pop;push -> mov (esp),reg always instead of being removed
  1772. Revision 1.54 1999/05/27 19:44:49 peter
  1773. * removed oldasm
  1774. * plabel -> pasmlabel
  1775. * -a switches to source writing automaticly
  1776. * assembler readers OOPed
  1777. * asmsymbol automaticly external
  1778. * jumptables and other label fixes for asm readers
  1779. Revision 1.53 1999/05/12 00:19:52 peter
  1780. * removed R_DEFAULT_SEG
  1781. * uniform float names
  1782. Revision 1.52 1999/05/05 16:19:04 jonas
  1783. + remove the segment prefixes from LEA instructions
  1784. Revision 1.51 1999/05/05 10:05:54 florian
  1785. * a delphi compiled compiler recompiles ppc
  1786. Revision 1.50 1999/05/02 21:33:55 florian
  1787. * several bugs regarding -Or fixed
  1788. Revision 1.49 1999/05/02 14:26:31 peter
  1789. * fixed dec -> sub $1 opt which didn't set ops=2
  1790. }