cpubase.pas 19 KB

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  1. {
  2. Copyright (c) 1998-2012 by Florian Klaempfl and Peter Vreman
  3. Copyright (c) 2014 by Jonas Maebe and Florian Klaempfl
  4. Contains the base types for Aarch64
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. { Base unit for processor information. This unit contains
  19. enumerations of registers, opcodes, sizes, and other
  20. such things which are processor specific.
  21. }
  22. unit cpubase;
  23. {$define USEINLINE}
  24. {$i fpcdefs.inc}
  25. interface
  26. uses
  27. cutils,cclasses,
  28. globtype,globals,
  29. cpuinfo,
  30. aasmbase,
  31. cgbase
  32. ;
  33. {*****************************************************************************
  34. Assembler Opcodes
  35. *****************************************************************************}
  36. type
  37. TAsmOp= {$i a64op.inc}
  38. { This should define the array of instructions as string }
  39. op2strtable=array[tasmop] of string[11];
  40. const
  41. { First value of opcode enumeration }
  42. firstop = low(tasmop);
  43. { Last value of opcode enumeration }
  44. lastop = high(tasmop);
  45. {*****************************************************************************
  46. Registers
  47. *****************************************************************************}
  48. type
  49. { Number of registers used for indexing in tables }
  50. tregisterindex=0..{$i ra64nor.inc}-1;
  51. const
  52. { Available Superregisters }
  53. {$i ra64sup.inc}
  54. RS_IP0 = RS_X16;
  55. RS_IP1 = RS_X17;
  56. R_SUBWHOLE = R_SUBQ;
  57. { Available Registers }
  58. {$i ra64con.inc}
  59. NR_IP0 = NR_X16;
  60. NR_IP1 = NR_X17;
  61. { Integer Super registers first and last }
  62. first_int_supreg = RS_X0;
  63. { xzr and sp take up a separate super register because some instructions
  64. are ambiguous otherwise }
  65. first_int_imreg = $21;
  66. { Integer Super registers first and last }
  67. first_fpu_supreg = RS_S0;
  68. first_fpu_imreg = $20;
  69. { MM Super register first and last }
  70. first_mm_supreg = RS_S0;
  71. first_mm_imreg = $20;
  72. { Required parameter alignment when calling a routine declared as
  73. stdcall and cdecl. The alignment value should be the one defined
  74. by GCC or the target ABI.
  75. The value of this constant is equal to the constant
  76. PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
  77. }
  78. std_param_align = 8;
  79. { TODO: Calculate bsstart}
  80. regnumber_count_bsstart = 128;
  81. regnumber_table : array[tregisterindex] of tregister = (
  82. {$i ra64num.inc}
  83. );
  84. regstabs_table : array[tregisterindex] of shortint = (
  85. {$i ra64sta.inc}
  86. );
  87. regdwarf_table : array[tregisterindex] of shortint = (
  88. {$i ra64dwa.inc}
  89. );
  90. { registers which may be destroyed by calls }
  91. VOLATILE_INTREGISTERS = [RS_X0..RS_X18,RS_X30];
  92. VOLATILE_MMREGISTERS = [RS_D0..RS_D7,RS_D16..RS_D31];
  93. type
  94. totherregisterset = set of tregisterindex;
  95. {*****************************************************************************
  96. Instruction post fixes
  97. *****************************************************************************}
  98. type
  99. { ARM instructions load/store and arithmetic instructions
  100. can have several instruction post fixes which are collected
  101. in this enumeration
  102. }
  103. TOpPostfix = (PF_None,
  104. { update condition flags }
  105. PF_S,
  106. { load/store sizes }
  107. PF_B,PF_SB,PF_H,PF_SH,PF_W,PF_SW
  108. );
  109. TOpPostfixes = set of TOpPostfix;
  110. const
  111. tcgsizep2size: array[OS_NO..OS_F128] of byte =
  112. {OS_NO }
  113. (0,
  114. {OS_8,OS_16,OS_32,OS_64,OS_128,OS_S8,OS_S16,OS_S32,OS_S64,OS_S128}
  115. 0, 1, 2, 3, 4, 0, 1, 2, 3, 4,
  116. {OS_F32,OS_F64,OS_F80,OS_C64,OS_F128,}
  117. 2, 3, 0, 3, 4);
  118. oppostfix2str: array[TOpPostfix] of string[2] = ('',
  119. 's',
  120. 'b','sb','h','sh','w','sw');
  121. {*****************************************************************************
  122. Conditions
  123. *****************************************************************************}
  124. type
  125. TAsmCond=(C_None,
  126. C_EQ,C_NE,C_HS,C_LO,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  127. C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
  128. );
  129. TAsmConds = set of TAsmCond;
  130. const
  131. C_CS = C_HS;
  132. C_CC = C_LO;
  133. cond2str : array[TAsmCond] of string[2]=('',
  134. 'eq','ne','hs','lo','mi','pl','vs','vc','hi','ls',
  135. 'ge','lt','gt','le','al','nv'
  136. );
  137. uppercond2str : array[TAsmCond] of string[2]=('',
  138. 'EQ','NE','HS','LO','MI','PL','VS','VC','HI','LS',
  139. 'GE','LT','GT','LE','AL','NV'
  140. );
  141. {*****************************************************************************
  142. Flags
  143. *****************************************************************************}
  144. type
  145. TResFlags = (F_EQ,F_NE,F_CS,F_CC,F_MI,F_PL,F_VS,F_VC,F_HI,F_LS,
  146. F_GE,F_LT,F_GT,F_LE);
  147. const
  148. F_HS = F_CS;
  149. F_LO = F_CC;
  150. {*****************************************************************************
  151. Operands
  152. *****************************************************************************}
  153. type
  154. taddressmode = (AM_OFFSET,AM_PREINDEXED,AM_POSTINDEXED);
  155. tshiftmode = (SM_None,
  156. { shifted register instructions. LSL can also be used for
  157. the index register of certain loads/stores }
  158. SM_LSL,SM_LSR,SM_ASR,
  159. { extended register instructions: zero/sign extension +
  160. optional shift (interpreted as LSL after extension)
  161. -- the index register of certain loads/stores can be
  162. extended via (s|u)xtw with a shiftval of either 0 or
  163. log2(transfer size of the load/store)
  164. }
  165. SM_UXTB,SM_UXTH,SM_UXTW,SM_UXTX,SM_SXTB,SM_SXTH,SM_SXTW,SM_SXTX);
  166. tupdatereg = (UR_None,UR_Update);
  167. pshifterop = ^tshifterop;
  168. tshifterop = record
  169. shiftmode : tshiftmode;
  170. shiftimm : byte;
  171. end;
  172. {*****************************************************************************
  173. Constants
  174. *****************************************************************************}
  175. const
  176. max_operands = 6;
  177. maxintregs = 32;
  178. maxfpuregs = 32;
  179. maxaddrregs = 0;
  180. shiftedregmodes = [SM_LSL,SM_UXTB,SM_UXTH,SM_UXTW,SM_UXTX,SM_SXTB,SM_SXTH,SM_SXTW,SM_SXTX];
  181. extendedregmodes = [SM_LSL,SM_LSR,SM_ASR];
  182. {*****************************************************************************
  183. Operand Sizes
  184. *****************************************************************************}
  185. type
  186. topsize = (S_NO,
  187. S_B,S_W,S_L,S_BW,S_BL,S_WL,
  188. S_IS,S_IL,S_IQ,
  189. S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
  190. );
  191. {*****************************************************************************
  192. Default generic sizes
  193. *****************************************************************************}
  194. const
  195. { Defines the default address size for a processor, }
  196. OS_ADDR = OS_64;
  197. { the natural int size for a processor,
  198. has to match osuinttype/ossinttype as initialized in psystem }
  199. OS_INT = OS_64;
  200. OS_SINT = OS_S64;
  201. { the maximum float size for a processor, }
  202. OS_FLOAT = OS_F64;
  203. { the size of a vector register for a processor }
  204. OS_VECTOR = OS_M128;
  205. {*****************************************************************************
  206. Generic Register names
  207. *****************************************************************************}
  208. NR_FP = NR_X29;
  209. RS_FP = RS_X29;
  210. NR_WFP = NR_W29;
  211. RS_WFP = RS_W29;
  212. NR_LR = NR_X30;
  213. RS_LR = RS_X30;
  214. NR_WLR = NR_W30;
  215. RS_WLR = RS_W30;
  216. { Stack pointer register }
  217. NR_STACK_POINTER_REG = NR_SP;
  218. RS_STACK_POINTER_REG = RS_SP;
  219. { Frame pointer register }
  220. NR_FRAME_POINTER_REG = NR_X29;
  221. RS_FRAME_POINTER_REG = RS_X29;
  222. { Register for addressing absolute data in a position independant way,
  223. such as in PIC code. The exact meaning is ABI specific. For
  224. further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
  225. }
  226. NR_PIC_OFFSET_REG = NR_X18;
  227. { Results are returned in this register (32-bit values) }
  228. NR_FUNCTION_RETURN_REG = NR_X0;
  229. RS_FUNCTION_RETURN_REG = RS_X0;
  230. { The value returned from a function is available in this register }
  231. NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
  232. RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
  233. NR_FPU_RESULT_REG = NR_NO;
  234. NR_MM_RESULT_REG = NR_D0;
  235. NR_RETURN_ADDRESS_REG = NR_FUNCTION_RETURN_REG;
  236. { Offset where the parent framepointer is pushed }
  237. PARENT_FRAMEPOINTER_OFFSET = 0;
  238. NR_DEFAULTFLAGS = NR_NZCV;
  239. RS_DEFAULTFLAGS = RS_NZCV;
  240. {*****************************************************************************
  241. Helpers
  242. *****************************************************************************}
  243. { Returns the tcgsize corresponding with the size of reg.}
  244. function reg_cgsize(const reg: tregister) : tcgsize;
  245. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  246. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  247. procedure inverse_flags(var f: TResFlags);
  248. function flags_to_cond(const f: TResFlags) : TAsmCond;
  249. function findreg_by_number(r:Tregister):tregisterindex;
  250. function std_regnum_search(const s:string):Tregister;
  251. function std_regname(r:Tregister):string;
  252. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  253. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  254. procedure shifterop_reset(var so : tshifterop); {$ifdef USEINLINE}inline;{$endif USEINLINE}
  255. function dwarf_reg(r:tregister):shortint;
  256. function is_shifter_const(d: aint; size: tcgsize): boolean;
  257. implementation
  258. uses
  259. systems,rgBase,verbose;
  260. const
  261. std_regname_table : TRegNameTable = (
  262. {$i ra64std.inc}
  263. );
  264. regnumber_index : array[tregisterindex] of tregisterindex = (
  265. {$i ra64rni.inc}
  266. );
  267. std_regname_index : array[tregisterindex] of tregisterindex = (
  268. {$i ra64sri.inc}
  269. );
  270. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  271. begin
  272. case regtype of
  273. R_INTREGISTER:
  274. begin
  275. case s of
  276. { there's only Wn and Xn }
  277. OS_64,
  278. OS_S64:
  279. cgsize2subreg:=R_SUBWHOLE;
  280. else
  281. cgsize2subreg:=R_SUBD;
  282. end;
  283. end;
  284. R_MMREGISTER:
  285. begin
  286. case s of
  287. OS_F32:
  288. cgsize2subreg:=R_SUBMMS;
  289. OS_F64:
  290. cgsize2subreg:=R_SUBMMD;
  291. else
  292. internalerror(2009112701);
  293. end;
  294. end;
  295. else
  296. cgsize2subreg:=R_SUBWHOLE;
  297. end;
  298. end;
  299. function reg_cgsize(const reg: tregister): tcgsize;
  300. begin
  301. case getregtype(reg) of
  302. R_INTREGISTER:
  303. case getsubreg(reg) of
  304. R_SUBD:
  305. result:=OS_32
  306. else
  307. result:=OS_64;
  308. end;
  309. R_MMREGISTER :
  310. begin
  311. case getsubreg(reg) of
  312. R_SUBMMD:
  313. result:=OS_F64;
  314. R_SUBMMS:
  315. result:=OS_F32;
  316. R_SUBMMWHOLE:
  317. result:=OS_M128;
  318. else
  319. internalerror(2009112903);
  320. end;
  321. end;
  322. else
  323. internalerror(200303181);
  324. end;
  325. end;
  326. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  327. begin
  328. is_calljmp:=o in [A_B,A_BL,A_BLR,A_RET,A_CBNZ,A_CBZ,A_TBNZ,A_TBZ];
  329. end;
  330. procedure inverse_flags(var f: TResFlags);
  331. const
  332. inv_flags: array[TResFlags] of TResFlags =
  333. (F_NE,F_EQ,F_CC,F_CS,F_PL,F_MI,F_VC,F_VS,F_LS,F_HI,
  334. F_LT,F_GE,F_LE,F_GT);
  335. begin
  336. f:=inv_flags[f];
  337. end;
  338. function flags_to_cond(const f: TResFlags) : TAsmCond;
  339. const
  340. flag_2_cond: array[TResFlags] of TAsmCond =
  341. (C_EQ,C_NE,C_HS,C_LO,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  342. C_GE,C_LT,C_GT,C_LE);
  343. begin
  344. if f>high(flag_2_cond) then
  345. internalerror(200112301);
  346. result:=flag_2_cond[f];
  347. end;
  348. function findreg_by_number(r:Tregister):tregisterindex;
  349. begin
  350. result:=rgBase.findreg_by_number_table(r,regnumber_index);
  351. end;
  352. function std_regnum_search(const s:string):Tregister;
  353. begin
  354. result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
  355. end;
  356. function std_regname(r:Tregister):string;
  357. var
  358. p : tregisterindex;
  359. begin
  360. p:=findreg_by_number_table(r,regnumber_index);
  361. if p<>0 then
  362. result:=std_regname_table[p]
  363. else
  364. result:=generic_regname(r);
  365. end;
  366. procedure shifterop_reset(var so : tshifterop);{$ifdef USEINLINE}inline;{$endif USEINLINE}
  367. begin
  368. FillChar(so,sizeof(so),0);
  369. end;
  370. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  371. const
  372. inverse: array[TAsmCond] of TAsmCond=(C_None,
  373. C_NE,C_EQ,C_LO,C_HS,C_PL,C_MI,C_VC,C_VS,C_LS,C_HI,
  374. C_LT,C_GE,C_LE,C_GT,C_None,C_None
  375. );
  376. begin
  377. result := inverse[c];
  378. end;
  379. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  380. begin
  381. result := c1 = c2;
  382. end;
  383. function dwarf_reg(r:tregister):shortint;
  384. begin
  385. result:=regdwarf_table[findreg_by_number(r)];
  386. if result=-1 then
  387. internalerror(200603251);
  388. end;
  389. function is_shifter_const(d: aint; size: tcgsize): boolean;
  390. var
  391. pattern, checkpattern: qword;
  392. patternlen, maxbits, replicatedlen: longint;
  393. rightmostone, rightmostzero, checkbit, secondrightmostbit: longint;
  394. begin
  395. result:=false;
  396. { patterns with all bits 0 or 1 cannot be represented this way }
  397. if (d=0) then
  398. exit;
  399. case size of
  400. OS_64,
  401. OS_S64:
  402. begin
  403. if d=-1 then
  404. exit;
  405. maxbits:=64;
  406. end
  407. else
  408. begin
  409. if longint(d)=-1 then
  410. exit;
  411. { we'll generate a 32 bit pattern -> ignore upper sign bits in
  412. case of negative longint value }
  413. d:=cardinal(d);
  414. maxbits:=32;
  415. end;
  416. end;
  417. { "The Logical (immediate) instructions accept a bitmask immediate value
  418. that is a 32-bit pattern or a 64-bit pattern viewed as a vector of
  419. identical elements of size e = 2, 4, 8, 16, 32 or, 64 bits. Each
  420. element contains the same sub-pattern, that is a single run of
  421. 1 to (e - 1) nonzero bits from bit 0 followed by zero bits, then
  422. rotated by 0 to (e - 1) bits." (ARMv8 ARM)
  423. Rather than generating all possible patterns and checking whether they
  424. match our constant, we check whether the lowest 2/4/8/... bits are
  425. a valid pattern, and if so whether the constant consists of a
  426. replication of this pattern. Such a valid pattern has the form of
  427. either (regexp notation)
  428. * 1+0+1*
  429. * 0+1+0* }
  430. patternlen:=2;
  431. while patternlen<=maxbits do
  432. begin
  433. { try lowest <patternlen> bits of d as pattern }
  434. if patternlen<>64 then
  435. pattern:=qword(d) and ((qword(1) shl patternlen)-1)
  436. else
  437. pattern:=qword(d);
  438. { valid pattern? If it contains too many 1<->0 transitions, larger
  439. parts of d cannot be a valid pattern either }
  440. rightmostone:=BsfQWord(pattern);
  441. rightmostzero:=BsfQWord(not(pattern));
  442. { pattern all ones or zeroes -> not a valid pattern (but larger ones
  443. can still be valid, since we have too few transitions) }
  444. if (rightmostone<patternlen) and
  445. (rightmostzero<patternlen) then
  446. begin
  447. if rightmostone>rightmostzero then
  448. begin
  449. { we have .*1*0* -> check next zero position by shifting
  450. out the existing zeroes (shr rightmostone), inverting and
  451. then again looking for the rightmost one position }
  452. checkpattern:=not(pattern);
  453. checkbit:=rightmostone;
  454. end
  455. else
  456. begin
  457. { same as above, but for .*0*1* }
  458. checkpattern:=pattern;
  459. checkbit:=rightmostzero;
  460. end;
  461. secondrightmostbit:=BsfQWord(checkpattern shr checkbit)+checkbit;
  462. { if this position is >= patternlen -> ok (1 transition),
  463. otherwise we now have 2 transitions and have to check for a
  464. third (if there is one, abort)
  465. bsf returns 255 if no 1 bit is found, so in that case it's
  466. also ok
  467. }
  468. if secondrightmostbit<patternlen then
  469. begin
  470. secondrightmostbit:=BsfQWord(not(checkpattern) shr secondrightmostbit)+secondrightmostbit;
  471. if secondrightmostbit<patternlen then
  472. exit;
  473. end;
  474. { ok, this is a valid pattern, now does d consist of a
  475. repetition of this pattern? }
  476. replicatedlen:=patternlen;
  477. checkpattern:=pattern;
  478. while replicatedlen<maxbits do
  479. begin
  480. { douplicate current pattern }
  481. checkpattern:=checkpattern or (checkpattern shl replicatedlen);
  482. replicatedlen:=replicatedlen*2;
  483. end;
  484. if qword(d)=checkpattern then
  485. begin
  486. { yes! }
  487. result:=true;
  488. exit;
  489. end;
  490. end;
  491. patternlen:=patternlen*2;
  492. end;
  493. end;
  494. end.