popt386.pas 96 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  40. RegUsedAfterInstruction :=
  41. (Reg in UsedRegs) and
  42. (not(getNextInstruction(p,p)) or
  43. not(regLoadedWithNewValue(reg,false,p)));
  44. End;
  45. function doFpuLoadStoreOpt(asmL: paasmoutput; var p: pai): boolean;
  46. { returns true if a "continue" should be done after this optimization }
  47. var hp1, hp2: pai;
  48. begin
  49. doFpuLoadStoreOpt := false;
  50. if (paicpu(p)^.oper[0].typ = top_ref) and
  51. getNextInstruction(p, hp1) and
  52. (hp1^.typ = ait_instruction) and
  53. (((paicpu(hp1)^.opcode = A_FLD) and
  54. (paicpu(p)^.opcode = A_FSTP)) or
  55. ((paicpu(p)^.opcode = A_FISTP) and
  56. (paicpu(hp1)^.opcode = A_FILD))) and
  57. (paicpu(hp1)^.oper[0].typ = top_ref) and
  58. (paicpu(hp1)^.opsize = Paicpu(p)^.opsize) and
  59. refsEqual(paicpu(p)^.oper[0].ref^, paicpu(hp1)^.oper[0].ref^) then
  60. begin
  61. if getNextInstruction(hp1, hp2) and
  62. (hp2^.typ = ait_instruction) and
  63. ((paicpu(hp2)^.opcode = A_LEAVE) or
  64. (paicpu(hp2)^.opcode = A_RET)) and
  65. (paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) and
  66. (paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) and
  67. (paicpu(p)^.oper[0].ref^.Index = R_NO) then
  68. begin
  69. asmL^.remove(p);
  70. asmL^.remove(hp1);
  71. dispose(p, done);
  72. dispose(hp1, done);
  73. p := hp2;
  74. removeLastDeallocForFuncRes(asmL, p);
  75. doFPULoadStoreOpt := true;
  76. end
  77. else
  78. { fst can't store an extended value! }
  79. if (paicpu(p)^.opsize <> S_FX) and
  80. (paicpu(p)^.opsize <> S_IQ) then
  81. begin
  82. if (paicpu(p)^.opcode = A_FSTP) then
  83. paicpu(p)^.opcode := A_FST
  84. else Paicpu(p)^.opcode := A_FIST;
  85. asmL^.remove(hp1);
  86. dispose(hp1, done)
  87. end
  88. end;
  89. end;
  90. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  91. {First pass of peepholeoptimizations}
  92. Var
  93. l : longint;
  94. p,hp1,hp2 : pai;
  95. {$ifdef foropt}
  96. hp3,hp4: pai;
  97. {$endif foropt}
  98. TmpBool1, TmpBool2: Boolean;
  99. TmpRef: TReference;
  100. UsedRegs, TmpUsedRegs: TRegSet;
  101. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  102. {skips all labels and returns the next "real" instruction}
  103. Begin
  104. While assigned(hp^.next) and
  105. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  106. hp := pai(hp^.next);
  107. If assigned(hp^.next) Then
  108. Begin
  109. SkipLabels := True;
  110. hp2 := pai(hp^.next)
  111. End
  112. Else
  113. Begin
  114. hp2 := hp;
  115. SkipLabels := False
  116. End;
  117. End;
  118. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  119. {traces sucessive jumps to their final destination and sets it, e.g.
  120. je l1 je l3
  121. <code> <code>
  122. l1: becomes l1:
  123. je l2 je l3
  124. <code> <code>
  125. l2: l2:
  126. jmp l3 jmp l3}
  127. Var p1, p2: pai;
  128. l: pasmlabel;
  129. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  130. Begin
  131. FindAnyLabel := false;
  132. While assigned(hp^.next) and
  133. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  134. hp := pai(hp^.next);
  135. If assigned(hp^.next) and
  136. (pai(hp^.next)^.typ = ait_label) Then
  137. Begin
  138. FindAnyLabel := true;
  139. l := pai_label(hp^.next)^.l;
  140. End
  141. End;
  142. Begin
  143. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  144. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  145. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  146. Begin
  147. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  148. SkipLabels(p1,p1);
  149. If (pai(p1)^.typ = ait_instruction) and
  150. (paicpu(p1)^.is_jmp) Then
  151. If { the next instruction after the label where the jump hp arrives}
  152. { is unconditional or of the same type as hp, so continue }
  153. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  154. { the next instruction after the label where the jump hp arrives}
  155. { is the opposite of hp (so this one is never taken), but after }
  156. { that one there is a branch that will be taken, so perform a }
  157. { little hack: set p1 equal to this instruction (that's what the}
  158. { last SkipLabels is for, only works with short bool evaluation)}
  159. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  160. SkipLabels(p1,p2) and
  161. (p2^.typ = ait_instruction) and
  162. (paicpu(p2)^.is_jmp) and
  163. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  164. SkipLabels(p1,p1)) Then
  165. Begin
  166. GetFinalDestination(asml, paicpu(p1));
  167. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  168. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  169. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  170. End
  171. Else
  172. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  173. if not FindAnyLabel(p1,l) then
  174. begin
  175. {$ifdef finaldestdebug}
  176. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  177. strpnew('previous label inserted'))));
  178. {$endif finaldestdebug}
  179. getlabel(l);
  180. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  181. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  182. hp^.oper[0].sym := l;
  183. inc(l^.refs);
  184. { this won't work, since the new label isn't in the labeltable }
  185. { so it will fail the rangecheck. Labeltable should become a }
  186. { hashtable to support this: }
  187. { GetFinalDestination(asml, hp); }
  188. end
  189. else
  190. begin
  191. {$ifdef finaldestdebug}
  192. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  193. strpnew('next label reused'))));
  194. {$endif finaldestdebug}
  195. inc(l^.refs);
  196. hp^.oper[0].sym := l;
  197. GetFinalDestination(asml, hp);
  198. end;
  199. End;
  200. End;
  201. Function DoSubAddOpt(var p: Pai): Boolean;
  202. Begin
  203. DoSubAddOpt := False;
  204. If GetLastInstruction(p, hp1) And
  205. (hp1^.typ = ait_instruction) And
  206. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  207. Case Paicpu(hp1)^.opcode Of
  208. A_DEC:
  209. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  210. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  211. Begin
  212. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  213. AsmL^.Remove(hp1);
  214. Dispose(hp1, Done)
  215. End;
  216. A_SUB:
  217. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  218. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  219. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  220. Begin
  221. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  222. AsmL^.Remove(hp1);
  223. Dispose(hp1, Done)
  224. End;
  225. A_ADD:
  226. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  227. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  228. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  229. Begin
  230. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  231. AsmL^.Remove(hp1);
  232. Dispose(hp1, Done);
  233. If (Paicpu(p)^.oper[0].val = 0) Then
  234. Begin
  235. hp1 := Pai(p^.next);
  236. AsmL^.Remove(p);
  237. Dispose(p, Done);
  238. If Not GetLastInstruction(hp1, p) Then
  239. p := hp1;
  240. DoSubAddOpt := True;
  241. End
  242. End;
  243. End;
  244. End;
  245. Begin
  246. P := BlockStart;
  247. UsedRegs := [];
  248. While (P <> BlockEnd) Do
  249. Begin
  250. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  251. Case P^.Typ Of
  252. ait_instruction:
  253. Begin
  254. { Handle Jmp Optimizations }
  255. if Paicpu(p)^.is_jmp then
  256. begin
  257. {the following if-block removes all code between a jmp and the next label,
  258. because it can never be executed}
  259. If (paicpu(p)^.opcode = A_JMP) Then
  260. Begin
  261. While GetNextInstruction(p, hp1) and
  262. ((hp1^.typ <> ait_label) or
  263. { skip unused labels, they're not referenced anywhere }
  264. Not(Pai_Label(hp1)^.l^.is_used)) Do
  265. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  266. Begin
  267. AsmL^.Remove(hp1);
  268. Dispose(hp1, done);
  269. End;
  270. End;
  271. If GetNextInstruction(p, hp1) then
  272. Begin
  273. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  274. Begin
  275. hp2:=pai(hp1^.next);
  276. asml^.remove(p);
  277. dispose(p,done);
  278. p:=hp2;
  279. continue;
  280. end
  281. Else
  282. Begin
  283. if hp1^.typ = ait_label then
  284. SkipLabels(hp1,hp1);
  285. If (pai(hp1)^.typ=ait_instruction) and
  286. (paicpu(hp1)^.opcode=A_JMP) and
  287. GetNextInstruction(hp1, hp2) And
  288. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  289. Then
  290. Begin
  291. if paicpu(p)^.opcode=A_Jcc then
  292. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  293. else
  294. begin
  295. If (LabDif <> 0) Then
  296. GetFinalDestination(asml, paicpu(p));
  297. p:=pai(p^.next);
  298. continue;
  299. end;
  300. Dec(pai_label(hp2)^.l^.refs);
  301. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  302. Inc(paicpu(p)^.oper[0].sym^.refs);
  303. asml^.remove(hp1);
  304. dispose(hp1,done);
  305. If (LabDif <> 0) Then
  306. GetFinalDestination(asml, paicpu(p));
  307. end
  308. else
  309. If (LabDif <> 0) Then
  310. GetFinalDestination(asml, paicpu(p));
  311. end;
  312. end;
  313. end
  314. else
  315. { All other optimizes }
  316. begin
  317. For l := 0 to 2 Do
  318. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  319. With Paicpu(p)^.oper[l].ref^ Do
  320. Begin
  321. If (base = R_NO) And
  322. (index <> R_NO) And
  323. (scalefactor in [0,1])
  324. Then
  325. Begin
  326. base := index;
  327. index := R_NO
  328. End
  329. End;
  330. Case Paicpu(p)^.opcode Of
  331. A_AND:
  332. Begin
  333. If (Paicpu(p)^.oper[0].typ = top_const) And
  334. (Paicpu(p)^.oper[1].typ = top_reg) And
  335. GetNextInstruction(p, hp1) And
  336. (Pai(hp1)^.typ = ait_instruction) And
  337. (Paicpu(hp1)^.opcode = A_AND) And
  338. (Paicpu(hp1)^.oper[0].typ = top_const) And
  339. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  340. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  341. Then
  342. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  343. Begin
  344. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  345. AsmL^.Remove(hp1);
  346. Dispose(hp1, Done)
  347. End
  348. Else
  349. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  350. jump, but only if it's a conditional jump (PFV) }
  351. If (Paicpu(p)^.oper[1].typ = top_reg) And
  352. GetNextInstruction(p, hp1) And
  353. (hp1^.typ = ait_instruction) And
  354. (Paicpu(hp1)^.is_jmp) and
  355. (Paicpu(hp1)^.opcode<>A_JMP) and
  356. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  357. Paicpu(p)^.opcode := A_TEST;
  358. End;
  359. A_CMP:
  360. Begin
  361. If (Paicpu(p)^.oper[0].typ = top_const) And
  362. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  363. (Paicpu(p)^.oper[0].val = 0) Then
  364. {$ifdef foropt}
  365. If GetNextInstruction(p, hp1) And
  366. (hp1^.typ = ait_instruction) And
  367. (Paicpu(hp1)^.is_jmp) and
  368. (paicpu(hp1)^.opcode=A_Jcc) and
  369. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  370. GetNextInstruction(hp1,hp2) and
  371. (hp2^.typ = ait_instruction) and
  372. (Paicpu(hp2)^.opcode = A_DEC) And
  373. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  374. GetNextInstruction(hp2, hp3) And
  375. (hp3^.typ = ait_instruction) and
  376. (Paicpu(hp3)^.is_jmp) and
  377. (Paicpu(hp3)^.opcode = A_JMP) And
  378. GetNextInstruction(hp3, hp4) And
  379. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  380. Then
  381. Begin
  382. Paicpu(hp2)^.Opcode := A_SUB;
  383. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  384. Paicpu(hp2)^.LoadConst(0,1);
  385. Paicpu(hp2)^.ops:=2;
  386. Paicpu(hp3)^.Opcode := A_Jcc;
  387. Case paicpu(hp1)^.condition of
  388. C_LE: Paicpu(hp3)^.condition := C_GE;
  389. C_BE: Paicpu(hp3)^.condition := C_AE;
  390. End;
  391. AsmL^.Remove(p);
  392. AsmL^.Remove(hp1);
  393. Dispose(p, Done);
  394. Dispose(hp1, Done);
  395. p := hp2;
  396. continue;
  397. End
  398. Else
  399. {$endif foropt}
  400. {change "cmp $0, %reg" to "test %reg, %reg"}
  401. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  402. Begin
  403. Paicpu(p)^.opcode := A_TEST;
  404. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  405. End;
  406. End;
  407. A_FLD:
  408. Begin
  409. If (Paicpu(p)^.oper[0].typ = top_reg) And
  410. GetNextInstruction(p, hp1) And
  411. (hp1^.typ = Ait_Instruction) And
  412. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  413. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  414. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  415. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  416. { change to
  417. fld reg fxxx reg,st
  418. fxxxp st, st1 (hp1)
  419. Remark: non commutative operations must be reversed!
  420. }
  421. begin
  422. Case Paicpu(hp1)^.opcode Of
  423. A_FMULP,A_FADDP,
  424. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  425. begin
  426. Case Paicpu(hp1)^.opcode Of
  427. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  428. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  429. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  430. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  431. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  432. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  433. End;
  434. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  435. Paicpu(hp1)^.oper[1].reg := R_ST;
  436. AsmL^.Remove(p);
  437. Dispose(p, Done);
  438. p := hp1;
  439. Continue;
  440. end;
  441. end;
  442. end
  443. else
  444. If (Paicpu(p)^.oper[0].typ = top_ref) And
  445. GetNextInstruction(p, hp2) And
  446. (hp2^.typ = Ait_Instruction) And
  447. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  448. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  449. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  450. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  451. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  452. If GetLastInstruction(p, hp1) And
  453. (hp1^.typ = Ait_Instruction) And
  454. ((Paicpu(hp1)^.opcode = A_FLD) Or
  455. (Paicpu(hp1)^.opcode = A_FST)) And
  456. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  457. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  458. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  459. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  460. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  461. { change to
  462. fld/fst mem1 (hp1) fld/fst mem1
  463. fld mem1 (p) fadd/
  464. faddp/ fmul st, st
  465. fmulp st, st1 (hp2) }
  466. Begin
  467. AsmL^.Remove(p);
  468. Dispose(p, Done);
  469. p := hp1;
  470. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  471. Paicpu(hp2)^.opcode := A_FADD
  472. Else
  473. Paicpu(hp2)^.opcode := A_FMUL;
  474. Paicpu(hp2)^.oper[1].reg := R_ST;
  475. End
  476. Else
  477. { change to
  478. fld/fst mem1 (hp1) fld/fst mem1
  479. fld mem1 (p) fld st}
  480. Begin
  481. Paicpu(p)^.changeopsize(S_FL);
  482. Paicpu(p)^.loadreg(0,R_ST);
  483. End
  484. Else
  485. Begin
  486. Case Paicpu(hp2)^.opcode Of
  487. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  488. { change to
  489. fld/fst mem1 (hp1) fld/fst mem1
  490. fld mem2 (p) fxxx mem2
  491. fxxxp st, st1 (hp2) }
  492. Begin
  493. Case Paicpu(hp2)^.opcode Of
  494. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  495. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  496. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  497. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  498. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  499. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  500. End;
  501. AsmL^.Remove(hp2);
  502. Dispose(hp2, Done)
  503. End
  504. End
  505. End
  506. End;
  507. A_FSTP,A_FISTP:
  508. if doFpuLoadStoreOpt(asmL,p) then
  509. continue;
  510. A_IMUL:
  511. {changes certain "imul const, %reg"'s to lea sequences}
  512. Begin
  513. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  514. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  515. (Paicpu(p)^.opsize = S_L) Then
  516. If (Paicpu(p)^.oper[0].val = 1) Then
  517. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  518. {remove "imul $1, reg"}
  519. Begin
  520. hp1 := Pai(p^.Next);
  521. AsmL^.Remove(p);
  522. Dispose(p, Done);
  523. p := hp1;
  524. Continue;
  525. End
  526. Else
  527. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  528. Begin
  529. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  530. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  531. Dispose(p, Done);
  532. p := hp1;
  533. End
  534. Else If
  535. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  536. (Paicpu(p)^.oper[2].typ = Top_None)) And
  537. (aktoptprocessor < ClassP6) And
  538. (Paicpu(p)^.oper[0].val <= 12) And
  539. Not(CS_LittleSize in aktglobalswitches) And
  540. (Not(GetNextInstruction(p, hp1)) Or
  541. {GetNextInstruction(p, hp1) And}
  542. Not((Pai(hp1)^.typ = ait_instruction) And
  543. ((paicpu(hp1)^.opcode=A_Jcc) and
  544. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  545. Then
  546. Begin
  547. Reset_reference(tmpref);
  548. Case Paicpu(p)^.oper[0].val Of
  549. 3: Begin
  550. {imul 3, reg1, reg2 to
  551. lea (reg1,reg1,2), reg2
  552. imul 3, reg1 to
  553. lea (reg1,reg1,2), reg1}
  554. TmpRef.base := Paicpu(p)^.oper[1].reg;
  555. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  556. TmpRef.ScaleFactor := 2;
  557. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  558. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  559. Else
  560. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  561. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  562. Dispose(p, Done);
  563. p := hp1;
  564. End;
  565. 5: Begin
  566. {imul 5, reg1, reg2 to
  567. lea (reg1,reg1,4), reg2
  568. imul 5, reg1 to
  569. lea (reg1,reg1,4), reg1}
  570. TmpRef.base := Paicpu(p)^.oper[1].reg;
  571. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  572. TmpRef.ScaleFactor := 4;
  573. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  574. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  575. Else
  576. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  577. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  578. Dispose(p, Done);
  579. p := hp1;
  580. End;
  581. 6: Begin
  582. {imul 6, reg1, reg2 to
  583. lea (,reg1,2), reg2
  584. lea (reg2,reg1,4), reg2
  585. imul 6, reg1 to
  586. lea (reg1,reg1,2), reg1
  587. add reg1, reg1}
  588. If (aktoptprocessor <= Class386)
  589. Then
  590. Begin
  591. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  592. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  593. Then
  594. Begin
  595. TmpRef.base := Paicpu(p)^.oper[2].reg;
  596. TmpRef.ScaleFactor := 4;
  597. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  598. End
  599. Else
  600. Begin
  601. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  602. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  603. End;
  604. InsertLLItem(AsmL,p, p^.next, hp1);
  605. Reset_reference(tmpref);
  606. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  607. TmpRef.ScaleFactor := 2;
  608. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  609. Then
  610. Begin
  611. TmpRef.base := R_NO;
  612. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  613. Paicpu(p)^.oper[2].reg));
  614. End
  615. Else
  616. Begin
  617. TmpRef.base := Paicpu(p)^.oper[1].reg;
  618. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  619. End;
  620. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  621. Dispose(p, Done);
  622. p := Pai(hp1^.next);
  623. End
  624. End;
  625. 9: Begin
  626. {imul 9, reg1, reg2 to
  627. lea (reg1,reg1,8), reg2
  628. imul 9, reg1 to
  629. lea (reg1,reg1,8), reg1}
  630. TmpRef.base := Paicpu(p)^.oper[1].reg;
  631. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  632. TmpRef.ScaleFactor := 8;
  633. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  634. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  635. Else
  636. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  637. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  638. Dispose(p, Done);
  639. p := hp1;
  640. End;
  641. 10: Begin
  642. {imul 10, reg1, reg2 to
  643. lea (reg1,reg1,4), reg2
  644. add reg2, reg2
  645. imul 10, reg1 to
  646. lea (reg1,reg1,4), reg1
  647. add reg1, reg1}
  648. If (aktoptprocessor <= Class386) Then
  649. Begin
  650. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  651. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  652. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  653. Else
  654. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  655. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  656. InsertLLItem(AsmL,p, p^.next, hp1);
  657. TmpRef.base := Paicpu(p)^.oper[1].reg;
  658. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  659. TmpRef.ScaleFactor := 4;
  660. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  661. Then
  662. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  663. Else
  664. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  665. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  666. Dispose(p, Done);
  667. p := Pai(hp1^.next);
  668. End
  669. End;
  670. 12: Begin
  671. {imul 12, reg1, reg2 to
  672. lea (,reg1,4), reg2
  673. lea (,reg1,8) reg2
  674. imul 12, reg1 to
  675. lea (reg1,reg1,2), reg1
  676. lea (,reg1,4), reg1}
  677. If (aktoptprocessor <= Class386)
  678. Then
  679. Begin
  680. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  681. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  682. Begin
  683. TmpRef.base := Paicpu(p)^.oper[2].reg;
  684. TmpRef.ScaleFactor := 8;
  685. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  686. End
  687. Else
  688. Begin
  689. TmpRef.base := R_NO;
  690. TmpRef.ScaleFactor := 4;
  691. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  692. End;
  693. InsertLLItem(AsmL,p, p^.next, hp1);
  694. Reset_reference(tmpref);
  695. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  696. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  697. Begin
  698. TmpRef.base := R_NO;
  699. TmpRef.ScaleFactor := 4;
  700. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  701. End
  702. Else
  703. Begin
  704. TmpRef.base := Paicpu(p)^.oper[1].reg;
  705. TmpRef.ScaleFactor := 2;
  706. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  707. End;
  708. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  709. Dispose(p, Done);
  710. p := Pai(hp1^.next);
  711. End
  712. End
  713. End;
  714. End;
  715. End;
  716. A_LEA:
  717. Begin
  718. {removes seg register prefixes from LEA operations, as they
  719. don't do anything}
  720. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  721. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  722. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  723. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  724. {$ifndef newOptimizations}
  725. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  726. {$endif newOptimizations}
  727. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  728. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  729. {$ifdef newOptimizations}
  730. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  731. {$endif newOptimizations}
  732. Then
  733. Begin
  734. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  735. Paicpu(p)^.oper[1].reg));
  736. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  737. Dispose(p, Done);
  738. p := hp1;
  739. Continue;
  740. End
  741. Else
  742. {$ifdef newOptimizations}
  743. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  744. {$endif newOptimizations}
  745. Begin
  746. hp1 := Pai(p^.Next);
  747. AsmL^.Remove(p);
  748. Dispose(p, Done);
  749. p := hp1;
  750. Continue;
  751. End
  752. {$ifdef newOptimizations}
  753. else
  754. with Paicpu(p)^.oper[0].ref^ do
  755. if (Base = Paicpu(p)^.oper[1].reg) then
  756. begin
  757. l := offset+offsetfixup;
  758. case l of
  759. 1,-1:
  760. begin
  761. if l = 1 then
  762. paicpu(p)^.opcode := A_INC
  763. else paicpu(p)^.opcode := A_DEC;
  764. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  765. paicpu(p)^.ops := 1;
  766. end;
  767. else
  768. begin
  769. paicpu(p)^.opcode := A_ADD;
  770. paicpu(p)^.loadconst(0,offset+offsetfixup);
  771. end;
  772. end;
  773. end;
  774. {$endif newOptimizations}
  775. End;
  776. A_MOV:
  777. Begin
  778. TmpUsedRegs := UsedRegs;
  779. If (Paicpu(p)^.oper[1].typ = top_reg) And
  780. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  781. GetNextInstruction(p, hp1) And
  782. (Pai(hp1)^.typ = ait_instruction) And
  783. (Paicpu(hp1)^.opcode = A_MOV) And
  784. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  785. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  786. Then
  787. {we have "mov x, %treg; mov %treg, y}
  788. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  789. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  790. Case Paicpu(p)^.oper[0].typ Of
  791. top_reg:
  792. Begin
  793. { change "mov %reg, %treg; mov %treg, y"
  794. to "mov %reg, y" }
  795. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  796. AsmL^.Remove(p);
  797. Dispose(p, Done);
  798. p := hp1;
  799. continue;
  800. End;
  801. top_ref:
  802. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  803. Begin
  804. { change "mov mem, %treg; mov %treg, %reg"
  805. to "mov mem, %reg" }
  806. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  807. AsmL^.Remove(hp1);
  808. Dispose(hp1, Done);
  809. continue;
  810. End;
  811. End
  812. Else
  813. Else
  814. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  815. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  816. penalty}
  817. If (Paicpu(p)^.oper[0].typ = top_reg) And
  818. (Paicpu(p)^.oper[1].typ = top_reg) And
  819. GetNextInstruction(p,hp1) And
  820. (Pai(hp1)^.typ = ait_instruction) And
  821. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  822. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  823. Then
  824. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  825. Begin
  826. If ((Paicpu(hp1)^.opcode = A_OR) Or
  827. (Paicpu(hp1)^.opcode = A_TEST)) And
  828. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  829. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  830. Then
  831. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  832. Begin
  833. TmpUsedRegs := UsedRegs;
  834. If GetNextInstruction(hp1, hp2) And
  835. (hp2^.typ = ait_instruction) And
  836. paicpu(hp2)^.is_jmp and
  837. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  838. Then
  839. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  840. "test %reg1, %reg1; jxx"}
  841. Begin
  842. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  843. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  844. AsmL^.Remove(p);
  845. Dispose(p, done);
  846. p := hp1;
  847. continue
  848. End
  849. Else
  850. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  851. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  852. Begin
  853. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  854. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  855. End;
  856. End
  857. { Else
  858. If (Paicpu(p^.next)^.opcode
  859. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  860. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  861. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  862. End
  863. Else
  864. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  865. x >= RetOffset) as it doesn't do anything (it writes either to a
  866. parameter or to the temporary storage room for the function
  867. result)}
  868. If GetNextInstruction(p, hp1) And
  869. (Pai(hp1)^.typ = ait_instruction)
  870. Then
  871. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  872. (Paicpu(hp1)^.opcode = A_RET)) And
  873. (Paicpu(p)^.oper[1].typ = top_ref) And
  874. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  875. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  876. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  877. (Paicpu(p)^.oper[0].typ = top_reg)
  878. Then
  879. Begin
  880. AsmL^.Remove(p);
  881. Dispose(p, done);
  882. p := hp1;
  883. RemoveLastDeallocForFuncRes(asmL,p);
  884. End
  885. Else
  886. If (Paicpu(p)^.oper[0].typ = top_reg) And
  887. (Paicpu(p)^.oper[1].typ = top_ref) And
  888. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  889. (Paicpu(hp1)^.opcode = A_CMP) And
  890. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  891. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  892. Then
  893. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  894. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  895. { Next instruction is also a MOV ? }
  896. If GetNextInstruction(p, hp1) And
  897. (pai(hp1)^.typ = ait_instruction) and
  898. (Paicpu(hp1)^.opcode = A_MOV) and
  899. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  900. Then
  901. Begin
  902. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  903. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  904. Then
  905. {mov reg1, mem1 or mov mem1, reg1
  906. mov mem2, reg2 mov reg2, mem2}
  907. Begin
  908. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  909. {mov reg1, mem1 or mov mem1, reg1
  910. mov mem2, reg1 mov reg2, mem1}
  911. Begin
  912. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  913. { Removes the second statement from
  914. mov reg1, mem1
  915. mov mem1, reg1 }
  916. Begin
  917. AsmL^.remove(hp1);
  918. Dispose(hp1,done);
  919. End
  920. Else
  921. Begin
  922. TmpUsedRegs := UsedRegs;
  923. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  924. If (Paicpu(p)^.oper[0].typ = top_reg) And
  925. { mov reg1, mem1
  926. mov mem2, reg1 }
  927. GetNextInstruction(hp1, hp2) And
  928. (hp2^.typ = ait_instruction) And
  929. (Paicpu(hp2)^.opcode = A_CMP) And
  930. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  931. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  932. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  933. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  934. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  935. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  936. { change to
  937. mov reg1, mem1 mov reg1, mem1
  938. mov mem2, reg1 cmp reg1, mem2
  939. cmp mem1, reg1 }
  940. Begin
  941. AsmL^.Remove(hp2);
  942. Dispose(hp2, Done);
  943. Paicpu(hp1)^.opcode := A_CMP;
  944. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  945. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  946. End;
  947. End;
  948. End
  949. Else
  950. Begin
  951. tmpUsedRegs := UsedRegs;
  952. If GetNextInstruction(hp1, hp2) And
  953. (Paicpu(p)^.oper[0].typ = top_ref) And
  954. (Paicpu(p)^.oper[1].typ = top_reg) And
  955. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  956. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  957. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  958. (Pai(hp2)^.typ = ait_instruction) And
  959. (Paicpu(hp2)^.opcode = A_MOV) And
  960. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  961. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  962. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  963. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  964. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  965. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  966. { mov mem1, %edi
  967. mov %edi, mem2
  968. mov mem2, reg2
  969. to:
  970. mov mem1, reg2
  971. mov reg2, mem2}
  972. Begin
  973. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  974. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  975. AsmL^.Remove(hp2);
  976. Dispose(hp2,Done);
  977. End
  978. Else
  979. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  980. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  981. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  982. Then
  983. { mov mem1, reg1 mov mem1, reg1
  984. mov reg1, mem2 mov reg1, mem2
  985. mov mem2, reg2 mov mem2, reg1
  986. to: to:
  987. mov mem1, reg1 mov mem1, reg1
  988. mov mem1, reg2 mov reg1, mem2
  989. mov reg1, mem2
  990. or (if mem1 depends on reg1
  991. and/or if mem2 depends on reg2)
  992. to:
  993. mov mem1, reg1
  994. mov reg1, mem2
  995. mov reg1, reg2
  996. }
  997. Begin
  998. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  999. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  1000. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  1001. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1002. End
  1003. Else
  1004. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  1005. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  1006. Else
  1007. Begin
  1008. AsmL^.Remove(hp2);
  1009. Dispose(hp2, Done);
  1010. End
  1011. End;
  1012. End
  1013. Else
  1014. (* {movl [mem1],reg1
  1015. movl [mem1],reg2
  1016. to:
  1017. movl [mem1],reg1
  1018. movl reg1,reg2 }
  1019. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1020. (Paicpu(p)^.oper[1].typ = top_reg) and
  1021. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1022. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1023. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1024. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1025. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1026. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1027. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1028. Else*)
  1029. { movl const1,[mem1]
  1030. movl [mem1],reg1
  1031. to:
  1032. movl const1,reg1
  1033. movl reg1,[mem1] }
  1034. If (Paicpu(p)^.oper[0].typ = top_const) and
  1035. (Paicpu(p)^.oper[1].typ = top_ref) and
  1036. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1037. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1038. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1039. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1040. Begin
  1041. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1042. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1043. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1044. End
  1045. End;
  1046. End;
  1047. A_MOVZX:
  1048. Begin
  1049. {removes superfluous And's after movzx's}
  1050. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1051. GetNextInstruction(p, hp1) And
  1052. (Pai(hp1)^.typ = ait_instruction) And
  1053. (Paicpu(hp1)^.opcode = A_AND) And
  1054. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1055. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1056. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1057. Then
  1058. Case Paicpu(p)^.opsize Of
  1059. S_BL, S_BW:
  1060. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1061. Begin
  1062. AsmL^.Remove(hp1);
  1063. Dispose(hp1, Done);
  1064. End;
  1065. S_WL:
  1066. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1067. Begin
  1068. AsmL^.Remove(hp1);
  1069. Dispose(hp1, Done);
  1070. End;
  1071. End;
  1072. {changes some movzx constructs to faster synonims (all examples
  1073. are given with eax/ax, but are also valid for other registers)}
  1074. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1075. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1076. Case Paicpu(p)^.opsize of
  1077. S_BW:
  1078. Begin
  1079. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1080. Not(CS_LittleSize In aktglobalswitches)
  1081. Then
  1082. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1083. Begin
  1084. Paicpu(p)^.opcode := A_AND;
  1085. Paicpu(p)^.changeopsize(S_W);
  1086. Paicpu(p)^.LoadConst(0,$ff);
  1087. End
  1088. Else
  1089. If GetNextInstruction(p, hp1) And
  1090. (Pai(hp1)^.typ = ait_instruction) And
  1091. (Paicpu(hp1)^.opcode = A_AND) And
  1092. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1093. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1094. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1095. Then
  1096. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1097. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1098. Begin
  1099. Paicpu(p)^.opcode := A_MOV;
  1100. Paicpu(p)^.changeopsize(S_W);
  1101. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1102. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1103. End;
  1104. End;
  1105. S_BL:
  1106. Begin
  1107. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1108. Not(CS_LittleSize in aktglobalswitches)
  1109. Then
  1110. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1111. Begin
  1112. Paicpu(p)^.opcode := A_AND;
  1113. Paicpu(p)^.changeopsize(S_L);
  1114. Paicpu(p)^.loadconst(0,$ff)
  1115. End
  1116. Else
  1117. If GetNextInstruction(p, hp1) And
  1118. (Pai(hp1)^.typ = ait_instruction) And
  1119. (Paicpu(hp1)^.opcode = A_AND) And
  1120. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1121. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1122. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1123. Then
  1124. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1125. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1126. Begin
  1127. Paicpu(p)^.opcode := A_MOV;
  1128. Paicpu(p)^.changeopsize(S_L);
  1129. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1130. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1131. End
  1132. End;
  1133. S_WL:
  1134. Begin
  1135. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1136. Not(CS_LittleSize In aktglobalswitches)
  1137. Then
  1138. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1139. Begin
  1140. Paicpu(p)^.opcode := A_AND;
  1141. Paicpu(p)^.changeopsize(S_L);
  1142. Paicpu(p)^.LoadConst(0,$ffff);
  1143. End
  1144. Else
  1145. If GetNextInstruction(p, hp1) And
  1146. (Pai(hp1)^.typ = ait_instruction) And
  1147. (Paicpu(hp1)^.opcode = A_AND) And
  1148. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1149. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1150. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1151. Then
  1152. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1153. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1154. Begin
  1155. Paicpu(p)^.opcode := A_MOV;
  1156. Paicpu(p)^.changeopsize(S_L);
  1157. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1158. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1159. End;
  1160. End;
  1161. End
  1162. Else
  1163. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1164. Begin
  1165. If GetNextInstruction(p, hp1) And
  1166. (Pai(hp1)^.typ = ait_instruction) And
  1167. (Paicpu(hp1)^.opcode = A_AND) And
  1168. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1169. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1170. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1171. Begin
  1172. Paicpu(p)^.opcode := A_MOV;
  1173. Case Paicpu(p)^.opsize Of
  1174. S_BL:
  1175. Begin
  1176. Paicpu(p)^.changeopsize(S_L);
  1177. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1178. End;
  1179. S_WL:
  1180. Begin
  1181. Paicpu(p)^.changeopsize(S_L);
  1182. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1183. End;
  1184. S_BW:
  1185. Begin
  1186. Paicpu(p)^.changeopsize(S_W);
  1187. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1188. End;
  1189. End;
  1190. End;
  1191. End;
  1192. End;
  1193. A_POP:
  1194. Begin
  1195. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1196. GetNextInstruction(p, hp1) And
  1197. (pai(hp1)^.typ=ait_instruction) and
  1198. (Paicpu(hp1)^.opcode=A_PUSH) and
  1199. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1200. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1201. { This can't be done, because the register which is popped
  1202. can still be used after the push (PFV)
  1203. If (Not(cs_regalloc in aktglobalswitches)) Then
  1204. Begin
  1205. hp2:=pai(hp1^.next);
  1206. asml^.remove(p);
  1207. asml^.remove(hp1);
  1208. dispose(p,done);
  1209. dispose(hp1,done);
  1210. p:=hp2;
  1211. continue
  1212. End
  1213. Else }
  1214. Begin
  1215. { change it to a two op operation }
  1216. Paicpu(p)^.oper[1].typ:=top_none;
  1217. Paicpu(p)^.ops:=2;
  1218. Paicpu(p)^.opcode := A_MOV;
  1219. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1220. Reset_reference(tmpref);
  1221. TmpRef.base := R_ESP;
  1222. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1223. AsmL^.Remove(hp1);
  1224. Dispose(hp1, Done)
  1225. End;
  1226. end;
  1227. A_PUSH:
  1228. Begin
  1229. If (Paicpu(p)^.opsize = S_W) And
  1230. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1231. GetNextInstruction(p, hp1) And
  1232. (Pai(hp1)^.typ = ait_instruction) And
  1233. (Paicpu(hp1)^.opcode = A_PUSH) And
  1234. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1235. (Paicpu(hp1)^.opsize = S_W) Then
  1236. Begin
  1237. Paicpu(p)^.changeopsize(S_L);
  1238. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1239. AsmL^.Remove(hp1);
  1240. Dispose(hp1, Done)
  1241. End;
  1242. End;
  1243. A_SHL, A_SAL:
  1244. Begin
  1245. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1246. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1247. (Paicpu(p)^.opsize = S_L) And
  1248. (Paicpu(p)^.oper[0].val <= 3)
  1249. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1250. Then
  1251. Begin
  1252. TmpBool1 := True; {should we check the next instruction?}
  1253. TmpBool2 := False; {have we found an add/sub which could be
  1254. integrated in the lea?}
  1255. Reset_reference(tmpref);
  1256. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1257. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1258. While TmpBool1 And
  1259. GetNextInstruction(p, hp1) And
  1260. (Pai(hp1)^.typ = ait_instruction) And
  1261. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1262. (Paicpu(hp1)^.opcode = A_SUB)) And
  1263. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1264. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1265. Begin
  1266. TmpBool1 := False;
  1267. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1268. Then
  1269. Begin
  1270. TmpBool1 := True;
  1271. TmpBool2 := True;
  1272. If Paicpu(hp1)^.opcode = A_ADD Then
  1273. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1274. Else
  1275. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1276. AsmL^.Remove(hp1);
  1277. Dispose(hp1, Done);
  1278. End
  1279. Else
  1280. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1281. (Paicpu(hp1)^.opcode = A_ADD) And
  1282. (TmpRef.base = R_NO) Then
  1283. Begin
  1284. TmpBool1 := True;
  1285. TmpBool2 := True;
  1286. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1287. AsmL^.Remove(hp1);
  1288. Dispose(hp1, Done);
  1289. End;
  1290. End;
  1291. If TmpBool2 Or
  1292. ((aktoptprocessor < ClassP6) And
  1293. (Paicpu(p)^.oper[0].val <= 3) And
  1294. Not(CS_LittleSize in aktglobalswitches))
  1295. Then
  1296. Begin
  1297. If Not(TmpBool2) And
  1298. (Paicpu(p)^.oper[0].val = 1)
  1299. Then
  1300. Begin
  1301. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1302. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1303. End
  1304. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1305. Paicpu(p)^.oper[1].reg));
  1306. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1307. Dispose(p, Done);
  1308. p := hp1;
  1309. End;
  1310. End
  1311. Else
  1312. If (aktoptprocessor < ClassP6) And
  1313. (Paicpu(p)^.oper[0].typ = top_const) And
  1314. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1315. If (Paicpu(p)^.oper[0].val = 1)
  1316. Then
  1317. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1318. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1319. (unlike shl, which is only pairable in the U pipe)}
  1320. Begin
  1321. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1322. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1323. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1324. Dispose(p, done);
  1325. p := hp1;
  1326. End
  1327. Else If (Paicpu(p)^.opsize = S_L) and
  1328. (Paicpu(p)^.oper[0].val<= 3) Then
  1329. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1330. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1331. Begin
  1332. Reset_reference(tmpref);
  1333. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1334. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1335. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1336. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1337. Dispose(p, done);
  1338. p := hp1;
  1339. End
  1340. End;
  1341. A_SAR, A_SHR:
  1342. {changes the code sequence
  1343. shr/sar const1, x
  1344. shl const2, x
  1345. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1346. Begin
  1347. If GetNextInstruction(p, hp1) And
  1348. (pai(hp1)^.typ = ait_instruction) and
  1349. (Paicpu(hp1)^.opcode = A_SHL) and
  1350. (Paicpu(p)^.oper[0].typ = top_const) and
  1351. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1352. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1353. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1354. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1355. Then
  1356. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1357. Not(CS_LittleSize In aktglobalswitches)
  1358. Then
  1359. { shr/sar const1, %reg
  1360. shl const2, %reg
  1361. with const1 > const2 }
  1362. Begin
  1363. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1364. Paicpu(hp1)^.opcode := A_AND;
  1365. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1366. Case Paicpu(p)^.opsize Of
  1367. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1368. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1369. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1370. End;
  1371. End
  1372. Else
  1373. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1374. Not(CS_LittleSize In aktglobalswitches)
  1375. Then
  1376. { shr/sar const1, %reg
  1377. shl const2, %reg
  1378. with const1 < const2 }
  1379. Begin
  1380. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1381. Paicpu(p)^.opcode := A_AND;
  1382. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1383. Case Paicpu(p)^.opsize Of
  1384. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1385. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1386. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1387. End;
  1388. End
  1389. Else
  1390. { shr/sar const1, %reg
  1391. shl const2, %reg
  1392. with const1 = const2 }
  1393. Begin
  1394. Paicpu(p)^.opcode := A_AND;
  1395. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1396. Case Paicpu(p)^.opsize Of
  1397. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1398. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1399. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1400. End;
  1401. AsmL^.remove(hp1);
  1402. dispose(hp1, done);
  1403. End;
  1404. End;
  1405. A_SETcc :
  1406. { changes
  1407. setcc (funcres) setcc reg
  1408. movb (funcres), reg to leave/ret
  1409. leave/ret }
  1410. Begin
  1411. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1412. GetNextInstruction(p, hp1) And
  1413. GetNextInstruction(hp1, hp2) And
  1414. (hp2^.typ = ait_instruction) And
  1415. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1416. (Paicpu(hp2)^.opcode = A_RET)) And
  1417. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1418. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1419. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1420. (hp1^.typ = ait_instruction) And
  1421. (Paicpu(hp1)^.opcode = A_MOV) And
  1422. (Paicpu(hp1)^.opsize = S_B) And
  1423. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1424. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1425. Begin
  1426. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1427. AsmL^.Remove(hp1);
  1428. Dispose(hp1, Done)
  1429. End
  1430. End;
  1431. A_SUB:
  1432. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1433. { * change "sub/add const1, reg" or "dec reg" followed by
  1434. "sub const2, reg" to one "sub ..., reg" }
  1435. Begin
  1436. If (Paicpu(p)^.oper[0].typ = top_const) And
  1437. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1438. If (Paicpu(p)^.oper[0].val = 2) And
  1439. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1440. Begin
  1441. hp1 := Pai(p^.next);
  1442. While Assigned(hp1) And
  1443. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1444. Not((Pai(hp1)^.typ = ait_instruction) And
  1445. ((Paicpu(hp1)^.opcode = A_CALL) or
  1446. (Paicpu(hp1)^.opcode = A_PUSH) or
  1447. ((Paicpu(hp1)^.opcode = A_MOV) And
  1448. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1449. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1450. hp1 := Pai(hp1^.next);
  1451. If Assigned(hp1) And
  1452. (Pai(hp1)^.typ = ait_instruction) And
  1453. (Paicpu(hp1)^.opcode = A_PUSH) And
  1454. (Paicpu(hp1)^.opsize = S_W)
  1455. Then
  1456. Begin
  1457. Paicpu(hp1)^.changeopsize(S_L);
  1458. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1459. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1460. hp1 := Pai(p^.next);
  1461. AsmL^.Remove(p);
  1462. Dispose(p, Done);
  1463. p := hp1;
  1464. Continue
  1465. End;
  1466. If DoSubAddOpt(p) Then continue;
  1467. End
  1468. Else If DoSubAddOpt(p) Then Continue
  1469. End;
  1470. A_TEST, A_OR:
  1471. {removes the line marked with (x) from the sequence
  1472. And/or/xor/add/sub/... $x, %y
  1473. test/or %y, %y (x)
  1474. j(n)z _Label
  1475. as the first instruction already adjusts the ZF}
  1476. Begin
  1477. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1478. If GetLastInstruction(p, hp1) And
  1479. (pai(hp1)^.typ = ait_instruction) Then
  1480. Case Paicpu(hp1)^.opcode Of
  1481. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1482. Begin
  1483. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1484. Begin
  1485. hp1 := pai(p^.next);
  1486. asml^.remove(p);
  1487. dispose(p, done);
  1488. p := pai(hp1);
  1489. continue
  1490. End;
  1491. End;
  1492. A_DEC, A_INC, A_NEG:
  1493. Begin
  1494. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1495. Begin
  1496. Case Paicpu(hp1)^.opcode Of
  1497. A_DEC, A_INC:
  1498. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1499. Begin
  1500. Case Paicpu(hp1)^.opcode Of
  1501. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1502. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1503. End;
  1504. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1505. Paicpu(hp1)^.LoadConst(0,1);
  1506. Paicpu(hp1)^.ops:=2;
  1507. End
  1508. End;
  1509. hp1 := pai(p^.next);
  1510. asml^.remove(p);
  1511. dispose(p, done);
  1512. p := pai(hp1);
  1513. continue
  1514. End;
  1515. End
  1516. End
  1517. Else
  1518. End;
  1519. A_XOR:
  1520. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1521. (Paicpu(p)^.oper[1].typ = top_reg) And
  1522. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1523. { temporarily change this to 'mov reg,0' to make it easier }
  1524. { for the CSE. Will be changed back in pass 2 }
  1525. begin
  1526. paicpu(p)^.opcode := A_MOV;
  1527. paicpu(p)^.loadconst(0,0);
  1528. end;
  1529. End;
  1530. end; { if is_jmp }
  1531. End;
  1532. { ait_label:
  1533. Begin
  1534. If Not(Pai_Label(p)^.l^.is_used)
  1535. Then
  1536. Begin
  1537. hp1 := Pai(p^.next);
  1538. AsmL^.Remove(p);
  1539. Dispose(p, Done);
  1540. p := hp1;
  1541. Continue
  1542. End;
  1543. End;}
  1544. End;
  1545. p:=pai(p^.next);
  1546. end;
  1547. end;
  1548. {$ifdef foldArithOps}
  1549. Function IsArithOp(opcode: TAsmOp): Boolean;
  1550. Begin
  1551. IsArithOp := False;
  1552. Case opcode Of
  1553. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1554. End;
  1555. End;
  1556. {$endif foldArithOps}
  1557. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1558. function CanBeCMOV(p : pai) : boolean;
  1559. begin
  1560. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1561. (paicpu(p)^.opcode=A_MOV) and
  1562. (paicpu(p)^.opsize in [S_L,S_W]) and
  1563. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1564. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1565. end;
  1566. var
  1567. p,hp1,hp2: pai;
  1568. {$ifdef USECMOV}
  1569. l : longint;
  1570. condition : tasmcond;
  1571. hp3: pai;
  1572. {$endif USECMOV}
  1573. {$ifdef foldArithOps}
  1574. UsedRegs, TmpUsedRegs: TRegSet;
  1575. {$endif foldArithOps}
  1576. Begin
  1577. P := BlockStart;
  1578. {$ifdef foldArithOps}
  1579. UsedRegs := [];
  1580. {$endif foldArithOps}
  1581. While (P <> BlockEnd) Do
  1582. Begin
  1583. {$ifdef foldArithOps}
  1584. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1585. {$endif foldArithOps}
  1586. Case P^.Typ Of
  1587. Ait_Instruction:
  1588. Begin
  1589. Case Paicpu(p)^.opcode Of
  1590. A_CALL:
  1591. If (AktOptProcessor < ClassP6) And
  1592. GetNextInstruction(p, hp1) And
  1593. (hp1^.typ = ait_instruction) And
  1594. (paicpu(hp1)^.opcode = A_JMP) Then
  1595. Begin
  1596. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1597. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1598. InsertLLItem(AsmL, p^.previous, p, hp2);
  1599. Paicpu(p)^.opcode := A_JMP;
  1600. AsmL^.Remove(hp1);
  1601. Dispose(hp1, Done)
  1602. End;
  1603. {$ifdef USECMOV}
  1604. A_Jcc:
  1605. if (aktspecificoptprocessor=ClassP6) then
  1606. begin
  1607. { check for
  1608. jCC xxx
  1609. <several movs>
  1610. xxx:
  1611. }
  1612. l:=0;
  1613. GetNextInstruction(p, hp1);
  1614. while assigned(hp1) And
  1615. CanBeCMOV(hp1) do
  1616. begin
  1617. inc(l);
  1618. GetNextInstruction(hp1,hp1);
  1619. end;
  1620. if assigned(hp1) then
  1621. begin
  1622. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1623. begin
  1624. if (l<=4) and (l>0) then
  1625. begin
  1626. condition:=inverse_cond[paicpu(p)^.condition];
  1627. GetNextInstruction(p,hp1);
  1628. asml^.remove(p);
  1629. dispose(p,done);
  1630. p:=hp1;
  1631. repeat
  1632. paicpu(hp1)^.opcode:=A_CMOVcc;
  1633. paicpu(hp1)^.condition:=condition;
  1634. GetNextInstruction(hp1,hp1);
  1635. until not(assigned(hp1)) or
  1636. not(CanBeCMOV(hp1));
  1637. asml^.remove(hp1);
  1638. dispose(hp1,done);
  1639. continue;
  1640. end;
  1641. end
  1642. else
  1643. begin
  1644. { check further for
  1645. jCC xxx
  1646. <several movs>
  1647. jmp yyy
  1648. xxx:
  1649. <several movs>
  1650. yyy:
  1651. }
  1652. { hp2 points to jmp xxx }
  1653. hp2:=hp1;
  1654. { skip hp1 to xxx }
  1655. GetNextInstruction(hp1, hp1);
  1656. if assigned(hp2) and
  1657. assigned(hp1) and
  1658. (l<=3) and
  1659. (hp2^.typ=ait_instruction) and
  1660. (paicpu(hp2)^.is_jmp) and
  1661. (paicpu(hp2)^.condition=C_None) and
  1662. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1663. begin
  1664. l:=0;
  1665. while assigned(hp1) And
  1666. CanBeCMOV(hp1) do
  1667. begin
  1668. inc(l);
  1669. GetNextInstruction(hp1, hp1);
  1670. end;
  1671. end;
  1672. {
  1673. if assigned(hp1) and
  1674. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1675. begin
  1676. condition:=inverse_cond[paicpu(p)^.condition];
  1677. GetNextInstruction(p,hp1);
  1678. asml^.remove(p);
  1679. dispose(p,done);
  1680. p:=hp1;
  1681. repeat
  1682. paicpu(hp1)^.opcode:=A_CMOVcc;
  1683. paicpu(hp1)^.condition:=condition;
  1684. GetNextInstruction(hp1,hp1);
  1685. until not(assigned(hp1)) or
  1686. not(CanBeCMOV(hp1));
  1687. hp2:=hp1^.next;
  1688. condition:=inverse_cond[condition];
  1689. asml^.remove(hp1^.next)
  1690. dispose(hp1^.next,done);
  1691. asml^.remove(hp1);
  1692. dispose(hp1,done);
  1693. continue;
  1694. end;
  1695. }
  1696. end;
  1697. end;
  1698. end;
  1699. {$endif USECMOV}
  1700. A_FSTP,A_FISTP:
  1701. if doFpuLoadStoreOpt(asmL,p) then
  1702. continue;
  1703. {$ifdef foldArithOps}
  1704. A_IMUL:
  1705. begin
  1706. if ((paicpu(p)^.oper[0].typ = top_const) or
  1707. (paicpu(p)^.oper[0].typ = top_symbol)) and
  1708. (paicpu(p)^.oper[1].typ = top_reg) and
  1709. ((paicpu(p)^.oper[2].typ = top_none) or
  1710. ((paicpu(p)^.oper[2].typ = top_reg) and
  1711. (paicpu(p)^.oper[2].reg = paicpu(p)^.oper[1].reg))) and
  1712. getLastInstruction(p,hp1) and
  1713. (hp1^.typ = ait_instruction) and
  1714. (paicpu(hp1)^.opcode = A_MOV) and
  1715. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1716. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1717. (paicpu(hp1)^.oper[1].reg = paicpu(p)^.oper[1].reg) then
  1718. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1719. begin
  1720. paicpu(p)^.ops := 3;
  1721. paicpu(p)^.loadreg(1,paicpu(hp1)^.oper[0].reg);
  1722. paicpu(p)^.loadreg(2,paicpu(hp1)^.oper[1].reg);
  1723. asmL^.remove(hp1);
  1724. dispose(hp1,done);
  1725. end;
  1726. end;
  1727. {$endif foldArithOps}
  1728. A_MOV:
  1729. Begin
  1730. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1731. (Paicpu(p)^.oper[1].typ = top_reg) And
  1732. GetNextInstruction(p, hp1) And
  1733. (hp1^.typ = ait_Instruction) And
  1734. ((Paicpu(hp1)^.opcode = A_MOV) or
  1735. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1736. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1737. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1738. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1739. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1740. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1741. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1742. {mov reg1, reg2
  1743. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1744. Begin
  1745. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1746. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1747. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1748. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1749. AsmL^.Remove(p);
  1750. Dispose(p, Done);
  1751. p := hp1;
  1752. Continue;
  1753. End
  1754. {$ifdef foldArithOps}
  1755. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1756. GetNextInstruction(p,hp1) And
  1757. (hp1^.typ = ait_instruction) And
  1758. IsArithOp(Paicpu(hp1)^.opcode) And
  1759. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1760. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1761. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1762. GetNextInstruction(hp1,hp2) And
  1763. (hp2^.typ = ait_instruction) And
  1764. (Paicpu(hp2)^.opcode = A_MOV) And
  1765. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1766. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1767. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1768. Begin
  1769. TmpUsedRegs := UsedRegs;
  1770. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1771. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1772. Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
  1773. hp2, TmpUsedRegs)))
  1774. Then
  1775. { change mov (ref), reg }
  1776. { add/sub/or/... reg2/$const, reg }
  1777. { mov (reg), ref }
  1778. { # release reg }
  1779. { to add/sub/or/... reg2/$const, (ref) }
  1780. Begin
  1781. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1782. AsmL^.Remove(p);
  1783. AsmL^.Remove(hp2);
  1784. Dispose(p,done);
  1785. Dispose(hp2,Done);
  1786. p := hp1
  1787. End;
  1788. End
  1789. {$endif foldArithOps}
  1790. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1791. (Paicpu(p)^.oper[0].val = 0) And
  1792. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1793. { change "mov $0, %reg" into "xor %reg, %reg" }
  1794. Begin
  1795. Paicpu(p)^.opcode := A_XOR;
  1796. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1797. End
  1798. End;
  1799. A_MOVZX:
  1800. Begin
  1801. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1802. If (Paicpu(p)^.oper[0].typ = top_reg)
  1803. Then
  1804. Case Paicpu(p)^.opsize of
  1805. S_BL:
  1806. Begin
  1807. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1808. Not(CS_LittleSize in aktglobalswitches) And
  1809. (aktoptprocessor = ClassP5)
  1810. Then
  1811. {Change "movzbl %reg1, %reg2" to
  1812. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1813. PentiumMMX}
  1814. Begin
  1815. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1816. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1817. InsertLLItem(AsmL,p^.previous, p, hp1);
  1818. Paicpu(p)^.opcode := A_MOV;
  1819. Paicpu(p)^.changeopsize(S_B);
  1820. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1821. End;
  1822. End;
  1823. End
  1824. Else
  1825. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1826. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1827. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1828. Not(CS_LittleSize in aktglobalswitches) And
  1829. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1830. (aktoptprocessor = ClassP5) And
  1831. (Paicpu(p)^.opsize = S_BL)
  1832. Then
  1833. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1834. Pentium and PentiumMMX}
  1835. Begin
  1836. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1837. Paicpu(p)^.oper[1].reg));
  1838. Paicpu(p)^.opcode := A_MOV;
  1839. Paicpu(p)^.changeopsize(S_B);
  1840. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1841. InsertLLItem(AsmL,p^.previous, p, hp1);
  1842. End;
  1843. End;
  1844. End;
  1845. End;
  1846. End;
  1847. p := Pai(p^.next)
  1848. End;
  1849. End;
  1850. End.
  1851. {
  1852. $Log$
  1853. Revision 1.87 2000-02-13 14:21:50 jonas
  1854. * modifications to make the compiler functional when compiled with
  1855. -Or
  1856. Revision 1.86 2000/02/12 19:28:56 jonas
  1857. * fix for imul optimization in popt386 (exclude top_ref as first
  1858. argument)
  1859. * in csopt386: change "mov reg1,reg2; <several operations on reg2>;
  1860. mov reg2,reg1" to "<several operations on reg1>" (-dnewopt...)
  1861. Revision 1.85 2000/02/12 14:10:15 jonas
  1862. + change "mov reg1,reg2;imul x,reg2" to "imul x,reg1,reg2" in popt386
  1863. (-dnewoptimizations)
  1864. * shl(d) and shr(d) are considered to have a hardcoded register if
  1865. they use cl as shift count (since you can't replace them with
  1866. another register) in csopt386 (also for -dnewoptimizations)
  1867. Revision 1.84 2000/02/09 13:22:58 peter
  1868. * log truncated
  1869. Revision 1.83 2000/02/04 13:53:04 jonas
  1870. * fpuloadstore optimizations are now done before and after the CSE
  1871. Revision 1.82 2000/01/24 12:17:24 florian
  1872. * some improvemenst to cmov support
  1873. * disabled excpetion frame generation in cosntructors temporarily
  1874. Revision 1.81 2000/01/23 21:29:17 florian
  1875. * CMOV support in optimizer (in define USECMOV)
  1876. + start of support of exceptions in constructors
  1877. Revision 1.80 2000/01/22 16:05:15 jonas
  1878. + change "lea x(reg),reg" to "add x,reg" (-dnewoptimizations)
  1879. * detection whether edi is used after instructions (since regalloc
  1880. info for it is now available)
  1881. * better regUsedAfterInstruction function
  1882. Revision 1.79 2000/01/21 11:26:19 pierre
  1883. * bug fix for bug 802
  1884. Revision 1.78 2000/01/11 17:14:49 jonas
  1885. * fixed a serious memory leak
  1886. Revision 1.77 2000/01/09 12:35:02 jonas
  1887. * changed edi allocation to use getexplicitregister32/ungetregister
  1888. (adapted tgeni386 a bit for this) and enabled it by default
  1889. * fixed very big and stupid bug of mine in cg386mat that broke the
  1890. include() code (and make cycle :( ) if you compiled without
  1891. -dnewoptimizations
  1892. Revision 1.76 2000/01/07 01:14:30 peter
  1893. * updated copyright to 2000
  1894. Revision 1.75 1999/12/30 17:56:44 peter
  1895. * fixed and;jmp being translated into test;jmp
  1896. Revision 1.74 1999/12/05 16:48:43 jonas
  1897. * CSE of constant loading in regs works properly again
  1898. + if a constant is stored into memory using "mov const, ref" and
  1899. there is a reg that contains this const, it is changed into
  1900. "mov reg, ref"
  1901. Revision 1.73 1999/12/02 11:26:41 peter
  1902. * newoptimizations define added
  1903. Revision 1.72 1999/11/30 10:40:45 peter
  1904. + ttype, tsymlist
  1905. Revision 1.71 1999/11/27 23:47:55 jonas
  1906. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1907. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1908. Enable with -dfoldArithOps
  1909. Revision 1.70 1999/11/21 13:09:41 jonas
  1910. * fixed some missed optimizations because 8bit regs were not always
  1911. taken into account
  1912. Revision 1.69 1999/11/13 19:03:56 jonas
  1913. * don't remove align objects between JMP's and labels
  1914. Revision 1.68 1999/11/06 16:24:00 jonas
  1915. * getfinaldestination works completely again (a lot of functionality
  1916. got lost in the conversion resulting from the removal of
  1917. ait_labeled_instruction)
  1918. Revision 1.67 1999/11/06 14:34:23 peter
  1919. * truncated log to 20 revs
  1920. Revision 1.66 1999/09/27 23:44:55 peter
  1921. * procinfo is now a pointer
  1922. * support for result setting in sub procedure
  1923. Revision 1.65 1999/09/05 14:27:19 florian
  1924. + fld reg;fxxx to fxxxr reg optimization
  1925. Revision 1.64 1999/08/25 12:00:02 jonas
  1926. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1927. }