aoptcpu.pas 39 KB

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  1. {
  2. Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
  3. Development Team
  4. This unit implements the ARM optimizer object
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. Interface
  21. uses cgbase, cpubase, aasmtai, aopt, aoptcpub, aoptobj;
  22. Type
  23. { TCpuAsmOptimizer }
  24. TCpuAsmOptimizer = class(TAsmOptimizer)
  25. { uses the same constructor as TAopObj }
  26. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  27. procedure PeepHoleOptPass2;override;
  28. Function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
  29. procedure RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string);
  30. function RegUsedAfterInstruction(reg: Tregister; p: tai;
  31. var AllUsedRegs: TAllUsedRegs): Boolean;
  32. End;
  33. TCpuPreRegallocScheduler = class(TAsmOptimizer)
  34. function PeepHoleOptPass1Cpu(var p: tai): boolean;override;
  35. end;
  36. TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
  37. { uses the same constructor as TAopObj }
  38. procedure PeepHoleOptPass2;override;
  39. End;
  40. Implementation
  41. uses
  42. cutils,
  43. verbose,
  44. cgutils,
  45. aasmbase,aasmdata,aasmcpu;
  46. function CanBeCond(p : tai) : boolean;
  47. begin
  48. result:=
  49. (p.typ=ait_instruction) and
  50. (taicpu(p).condition=C_None) and
  51. ((taicpu(p).opcode<>A_BLX) or
  52. (taicpu(p).oper[0]^.typ=top_reg));
  53. end;
  54. function RefsEqual(const r1, r2: treference): boolean;
  55. begin
  56. refsequal :=
  57. (r1.offset = r2.offset) and
  58. (r1.base = r2.base) and
  59. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  60. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  61. (r1.relsymbol = r2.relsymbol) and
  62. (r1.signindex = r2.signindex) and
  63. (r1.shiftimm = r2.shiftimm) and
  64. (r1.addressmode = r2.addressmode) and
  65. (r1.shiftmode = r2.shiftmode);
  66. end;
  67. function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
  68. begin
  69. result :=
  70. (instr.typ = ait_instruction) and
  71. (taicpu(instr).opcode = op) and
  72. ((cond = []) or (taicpu(instr).condition in cond)) and
  73. ((postfix = []) or (taicpu(instr).oppostfix in postfix));
  74. end;
  75. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
  76. begin
  77. result := (oper1.typ = oper2.typ) and
  78. (
  79. ((oper1.typ = top_const) and (oper1.val = oper2.val)) or
  80. ((oper1.typ = top_reg) and (oper1.reg = oper2.reg)) or
  81. ((oper1.typ = top_conditioncode) and (oper1.cc = oper2.cc))
  82. );
  83. end;
  84. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  85. begin
  86. result := (oper.typ = top_reg) and (oper.reg = reg);
  87. end;
  88. procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList);
  89. begin
  90. if (taicpu(movp).condition = C_EQ) and
  91. (taicpu(cmpp).oper[0]^.reg = taicpu(movp).oper[0]^.reg) and
  92. (taicpu(cmpp).oper[1]^.val = taicpu(movp).oper[1]^.val) then
  93. begin
  94. asml.insertafter(tai_comment.Create(strpnew('Peephole CmpMovMov - Removed redundant moveq')), movp);
  95. asml.remove(movp);
  96. movp.free;
  97. end;
  98. end;
  99. function regLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  100. var
  101. p: taicpu;
  102. begin
  103. p := taicpu(hp);
  104. regLoadedWithNewValue := false;
  105. if not ((assigned(hp)) and (hp.typ = ait_instruction)) then
  106. exit;
  107. {These are not writing to their first oper}
  108. if p.opcode in [A_STR, A_STRB, A_STRH, A_CMP, A_CMN, A_TST, A_TEQ,
  109. A_B, A_BL, A_BX, A_BLX] then
  110. exit;
  111. { These four are writing into the first 2 register, UMLAL and SMLAL will also read from them }
  112. if (p.opcode in [A_UMLAL, A_UMULL, A_SMLAL, A_SMULL]) and
  113. (p.oper[1]^.typ = top_reg) and
  114. (p.oper[1]^.reg = reg) then
  115. begin
  116. regLoadedWithNewValue := true;
  117. exit
  118. end;
  119. {All other instructions use oper[0] as destination}
  120. regLoadedWithNewValue :=
  121. (p.oper[0]^.typ = top_reg) and
  122. (p.oper[0]^.reg = reg);
  123. end;
  124. function instructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
  125. var
  126. p: taicpu;
  127. i: longint;
  128. begin
  129. instructionLoadsFromReg := false;
  130. if not (assigned(hp) and (hp.typ = ait_instruction)) then
  131. exit;
  132. p:=taicpu(hp);
  133. i:=1;
  134. {For these instructions we have to start on oper[0]}
  135. if (p.opcode in [A_STR, A_STRB, A_STRH, A_CMP, A_CMN, A_TST, A_TEQ,
  136. A_B, A_BL, A_BX, A_BLX,
  137. A_SMLAL, A_UMLAL]) then i:=0;
  138. while(i<p.ops) do
  139. begin
  140. case p.oper[I]^.typ of
  141. top_reg:
  142. instructionLoadsFromReg := p.oper[I]^.reg = reg;
  143. top_regset:
  144. instructionLoadsFromReg := (getsupreg(reg) in p.oper[I]^.regset^);
  145. top_shifterop:
  146. instructionLoadsFromReg := p.oper[I]^.shifterop^.rs = reg;
  147. top_ref:
  148. instructionLoadsFromReg :=
  149. (p.oper[I]^.ref^.base = reg) or
  150. (p.oper[I]^.ref^.index = reg);
  151. end;
  152. if instructionLoadsFromReg then exit; {Bailout if we found something}
  153. Inc(I);
  154. end;
  155. end;
  156. function TCpuAsmOptimizer.RegUsedAfterInstruction(reg: Tregister; p: tai;
  157. var AllUsedRegs: TAllUsedRegs): Boolean;
  158. begin
  159. AllUsedRegs[getregtype(reg)].Update(tai(p.Next));
  160. RegUsedAfterInstruction :=
  161. (AllUsedRegs[getregtype(reg)].IsUsed(reg)) and
  162. (not(getNextInstruction(p,p)) or
  163. instructionLoadsFromReg(reg,p) or
  164. not(regLoadedWithNewValue(reg,p)));
  165. end;
  166. procedure TCpuAsmOptimizer.RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string);
  167. var
  168. TmpUsedRegs: TAllUsedRegs;
  169. begin
  170. if MatchInstruction(movp, A_MOV, [taicpu(p).condition], [PF_None]) and
  171. (taicpu(movp).ops=2) and {We can't optimize if there is a shiftop}
  172. MatchOperand(taicpu(movp).oper[1]^, taicpu(p).oper[0]^.reg) and
  173. {There is a special requirement for MUL and MLA, oper[0] and oper[1] are not allowed to be the same}
  174. not (
  175. (taicpu(p).opcode in [A_MLA, A_MUL]) and
  176. (taicpu(p).oper[1]^.reg = taicpu(movp).oper[0]^.reg)
  177. ) then
  178. begin
  179. CopyUsedRegs(TmpUsedRegs);
  180. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  181. if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,movp,TmpUsedRegs)) then
  182. begin
  183. asml.insertbefore(tai_comment.Create(strpnew('Peephole '+optimizer+' removed superfluous mov')), movp);
  184. taicpu(p).loadreg(0,taicpu(movp).oper[0]^.reg);
  185. asml.remove(movp);
  186. movp.free;
  187. end;
  188. ReleaseUsedRegs(TmpUsedRegs);
  189. end;
  190. end;
  191. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  192. var
  193. hp1,hp2: tai;
  194. i: longint;
  195. TmpUsedRegs: TAllUsedRegs;
  196. begin
  197. result := false;
  198. case p.typ of
  199. ait_instruction:
  200. begin
  201. (* optimization proved not to be safe, see tw4768.pp
  202. {
  203. change
  204. <op> reg,x,y
  205. cmp reg,#0
  206. into
  207. <op>s reg,x,y
  208. }
  209. { this optimization can applied only to the currently enabled operations because
  210. the other operations do not update all flags and FPC does not track flag usage }
  211. if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
  212. (taicpu(p).oppostfix = PF_None) and
  213. (taicpu(p).condition = C_None) and
  214. GetNextInstruction(p, hp1) and
  215. MatchInstruction(hp1, A_CMP, [C_None], [PF_None]) and
  216. (taicpu(hp1).oper[1]^.typ = top_const) and
  217. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  218. (taicpu(hp1).oper[1]^.val = 0) { and
  219. GetNextInstruction(hp1, hp2) and
  220. (tai(hp2).typ = ait_instruction) and
  221. // be careful here, following instructions could use other flags
  222. // however after a jump fpc never depends on the value of flags
  223. (taicpu(hp2).opcode = A_B) and
  224. (taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL])} then
  225. begin
  226. taicpu(p).oppostfix:=PF_S;
  227. asml.remove(hp1);
  228. hp1.free;
  229. end
  230. else
  231. *)
  232. case taicpu(p).opcode of
  233. A_STR:
  234. begin
  235. { change
  236. str reg1,ref
  237. ldr reg2,ref
  238. into
  239. str reg1,ref
  240. mov reg2,reg1
  241. }
  242. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  243. (taicpu(p).oppostfix=PF_None) and
  244. GetNextInstruction(p,hp1) and
  245. MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
  246. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  247. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  248. begin
  249. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  250. begin
  251. asml.insertbefore(tai_comment.Create(strpnew('Peephole StrLdr2StrMov 1 done')), hp1);
  252. asml.remove(hp1);
  253. hp1.free;
  254. end
  255. else
  256. begin
  257. taicpu(hp1).opcode:=A_MOV;
  258. taicpu(hp1).oppostfix:=PF_None;
  259. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  260. asml.insertbefore(tai_comment.Create(strpnew('Peephole StrLdr2StrMov 2 done')), hp1);
  261. end;
  262. result := true;
  263. end;
  264. end;
  265. A_LDR:
  266. begin
  267. { change
  268. ldr reg1,ref
  269. ldr reg2,ref
  270. into
  271. ldr reg1,ref
  272. mov reg2,reg1
  273. }
  274. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  275. GetNextInstruction(p,hp1) and
  276. MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [taicpu(p).oppostfix]) and
  277. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  278. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
  279. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
  280. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  281. begin
  282. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  283. begin
  284. asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2Ldr done')), hp1);
  285. asml.remove(hp1);
  286. hp1.free;
  287. end
  288. else
  289. begin
  290. asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2LdrMov done')), hp1);
  291. taicpu(hp1).opcode:=A_MOV;
  292. taicpu(hp1).oppostfix:=PF_None;
  293. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  294. end;
  295. result := true;
  296. end;
  297. { Remove superfluous mov after ldr
  298. changes
  299. ldr reg1, ref
  300. mov reg2, reg1
  301. to
  302. ldr reg2, ref
  303. conditions are:
  304. * reg1 must be released after mov
  305. * mov can not contain shifterops
  306. * ldr+mov have the same conditions
  307. * mov does not set flags
  308. }
  309. if GetNextInstruction(p, hp1) then
  310. RemoveSuperfluousMove(p, hp1, 'LdrMov2Ldr');
  311. end;
  312. A_MOV:
  313. begin
  314. { fold
  315. mov reg1,reg0, shift imm1
  316. mov reg1,reg1, shift imm2
  317. to
  318. mov reg1,reg0, shift imm1+imm2
  319. }
  320. if (taicpu(p).ops=3) and
  321. (taicpu(p).oper[2]^.typ = top_shifterop) and
  322. (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
  323. getnextinstruction(p,hp1) and
  324. MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and
  325. (taicpu(hp1).ops=3) and
  326. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
  327. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
  328. (taicpu(hp1).oper[2]^.typ = top_shifterop) and
  329. (taicpu(hp1).oper[2]^.shifterop^.rs = NR_NO) then
  330. begin
  331. { fold
  332. mov reg1,reg0, lsl 16
  333. mov reg1,reg1, lsr 16
  334. strh reg1, ...
  335. dealloc reg1
  336. to
  337. strh reg1, ...
  338. dealloc reg1
  339. }
  340. if (taicpu(p).oper[2]^.shifterop^.shiftmode=SM_LSL) and
  341. (taicpu(p).oper[2]^.shifterop^.shiftimm=16) and
  342. (taicpu(hp1).oper[2]^.shifterop^.shiftmode in [SM_LSR,SM_ASR]) and
  343. (taicpu(hp1).oper[2]^.shifterop^.shiftimm=16) and
  344. getnextinstruction(hp1,hp2) and
  345. MatchInstruction(hp2, A_STR, [taicpu(p).condition], [PF_H]) and
  346. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^.reg) then
  347. begin
  348. CopyUsedRegs(TmpUsedRegs);
  349. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  350. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  351. if not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg,hp2,TmpUsedRegs)) then
  352. begin
  353. asml.insertbefore(tai_comment.Create(strpnew('Peephole optimizer removed superfluous 16 Bit zero extension')), hp1);
  354. taicpu(hp2).loadreg(0,taicpu(p).oper[1]^.reg);
  355. asml.remove(p);
  356. asml.remove(hp1);
  357. p.free;
  358. hp1.free;
  359. p:=hp2;
  360. end;
  361. ReleaseUsedRegs(TmpUsedRegs);
  362. end
  363. { fold
  364. mov reg1,reg0, shift imm1
  365. mov reg1,reg1, shift imm2
  366. to
  367. mov reg1,reg0, shift imm1+imm2
  368. }
  369. else if (taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(hp1).oper[2]^.shifterop^.shiftmode) then
  370. begin
  371. inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(hp1).oper[2]^.shifterop^.shiftimm);
  372. { avoid overflows }
  373. if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
  374. case taicpu(p).oper[2]^.shifterop^.shiftmode of
  375. SM_ROR:
  376. taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
  377. SM_ASR:
  378. taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
  379. SM_LSR,
  380. SM_LSL:
  381. begin
  382. hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
  383. InsertLLItem(p.previous, p.next, hp1);
  384. p.free;
  385. p:=hp1;
  386. end;
  387. else
  388. internalerror(2008072803);
  389. end;
  390. asml.insertbefore(tai_comment.Create(strpnew('Peephole ShiftShift2Shift done')), p);
  391. asml.remove(hp1);
  392. hp1.free;
  393. result := true;
  394. end;
  395. end;
  396. {
  397. This changes the very common
  398. mov r0, #0
  399. str r0, [...]
  400. mov r0, #0
  401. str r0, [...]
  402. and removes all superfluous mov instructions
  403. }
  404. if (taicpu(p).ops = 2) and
  405. (taicpu(p).oper[1]^.typ = top_const) and
  406. GetNextInstruction(p,hp1) then
  407. begin
  408. while (tai(p).typ = ait_instruction) and
  409. (taicpu(p).opcode = A_STR) and
  410. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) and
  411. GetNextInstruction(hp1, hp2) and
  412. MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [PF_None]) and
  413. (taicpu(hp2).ops = 2) and
  414. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^) and
  415. MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) do
  416. begin
  417. asml.insertbefore(tai_comment.Create(strpnew('Peephole MovStrMov done')), hp2);
  418. GetNextInstruction(hp2,hp1);
  419. asml.remove(hp2);
  420. hp2.free;
  421. if not assigned(hp1) then break;
  422. end;
  423. end;
  424. {
  425. change
  426. mov r1, r0
  427. add r1, r1, #1
  428. to
  429. add r1, r0, #1
  430. Todo: Make it work for mov+cmp too
  431. }
  432. if (taicpu(p).ops = 2) and
  433. (taicpu(p).oper[1]^.typ = top_reg) and
  434. (taicpu(p).oppostfix = PF_NONE) and
  435. GetNextInstruction(p, hp1) and
  436. (tai(hp1).typ = ait_instruction) and
  437. (taicpu(hp1).opcode in [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
  438. A_AND, A_BIC, A_EOR, A_ORR, A_MOV, A_MVN]) and
  439. {MOV and MVN might only have 2 ops}
  440. (taicpu(hp1).ops = 3) and
  441. (taicpu(hp1).condition in [C_NONE, taicpu(hp1).condition]) and
  442. MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
  443. (taicpu(hp1).oper[1]^.typ = top_reg) and
  444. (taicpu(hp1).oper[2]^.typ in [top_reg, top_const, top_shifterop]) then
  445. begin
  446. { When we get here we still don't know if the registers match}
  447. for I:=1 to 2 do
  448. {
  449. If the first loop was successful p will be replaced with hp1.
  450. The checks will still be ok, because all required information
  451. will also be in hp1 then.
  452. }
  453. if MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg) then
  454. begin
  455. asml.insertbefore(tai_comment.Create(strpnew('Peephole RedundantMovProcess done')), hp1);
  456. taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
  457. if p<>hp1 then
  458. begin
  459. asml.remove(p);
  460. p.free;
  461. p:=hp1;
  462. end;
  463. end;
  464. end;
  465. {
  466. Often we see shifts and then a superfluous mov to another register
  467. In the future this might be handled in RedundantMovProcess when it uses RegisterTracking
  468. }
  469. if GetNextInstruction(p, hp1) then
  470. RemoveSuperfluousMove(p, hp1, 'MovMov2Mov');
  471. end;
  472. A_ADD,
  473. A_ADC,
  474. A_RSB,
  475. A_RSC,
  476. A_SUB,
  477. A_SBC,
  478. A_AND,
  479. A_BIC,
  480. A_EOR,
  481. A_ORR,
  482. A_MLA,
  483. A_MUL:
  484. begin
  485. {
  486. change
  487. and reg2,reg1,const1
  488. and reg2,reg2,const2
  489. to
  490. and reg2,reg1,(const1 and const2)
  491. }
  492. if (taicpu(p).opcode = A_AND) and
  493. (taicpu(p).oper[1]^.typ = top_reg) and
  494. (taicpu(p).oper[2]^.typ = top_const) and
  495. GetNextInstruction(p, hp1) and
  496. MatchInstruction(hp1, A_AND, [taicpu(p).condition], [PF_None]) and
  497. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
  498. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
  499. (taicpu(hp1).oper[2]^.typ = top_const) then
  500. begin
  501. asml.insertbefore(tai_comment.Create(strpnew('Peephole AndAnd2And done')), p);
  502. taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
  503. taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
  504. asml.remove(hp1);
  505. hp1.free;
  506. end;
  507. {
  508. change
  509. add reg1, ...
  510. mov reg2, reg1
  511. to
  512. add reg2, ...
  513. }
  514. if GetNextInstruction(p, hp1) then
  515. RemoveSuperfluousMove(p, hp1, 'DataMov2Data');
  516. end;
  517. A_CMP:
  518. begin
  519. {
  520. change
  521. cmp reg,const1
  522. moveq reg,const1
  523. movne reg,const2
  524. to
  525. cmp reg,const1
  526. movne reg,const2
  527. }
  528. if (taicpu(p).oper[1]^.typ = top_const) and
  529. GetNextInstruction(p, hp1) and
  530. MatchInstruction(hp1, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
  531. (taicpu(hp1).oper[1]^.typ = top_const) and
  532. GetNextInstruction(hp1, hp2) and
  533. MatchInstruction(hp2, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
  534. (taicpu(hp1).oper[1]^.typ = top_const) then
  535. begin
  536. RemoveRedundantMove(p, hp1, asml);
  537. RemoveRedundantMove(p, hp2, asml);
  538. end;
  539. end;
  540. end;
  541. end;
  542. end;
  543. end;
  544. { instructions modifying the CPSR can be only the last instruction }
  545. function MustBeLast(p : tai) : boolean;
  546. begin
  547. Result:=(p.typ=ait_instruction) and
  548. ((taicpu(p).opcode in [A_BL,A_BLX,A_CMP,A_CMN,A_SWI,A_TEQ,A_TST,A_CMF,A_CMFE {,A_MSR}]) or
  549. ((taicpu(p).ops>=1) and (taicpu(p).oper[0]^.typ=top_reg) and (taicpu(p).oper[0]^.reg=NR_PC)) or
  550. (taicpu(p).oppostfix=PF_S));
  551. end;
  552. procedure TCpuAsmOptimizer.PeepHoleOptPass2;
  553. var
  554. p,hp1,hp2: tai;
  555. l : longint;
  556. condition : tasmcond;
  557. hp3: tai;
  558. WasLast: boolean;
  559. { UsedRegs, TmpUsedRegs: TRegSet; }
  560. begin
  561. p := BlockStart;
  562. { UsedRegs := []; }
  563. while (p <> BlockEnd) Do
  564. begin
  565. { UpdateUsedRegs(UsedRegs, tai(p.next)); }
  566. case p.Typ Of
  567. Ait_Instruction:
  568. begin
  569. case taicpu(p).opcode Of
  570. A_B:
  571. if taicpu(p).condition<>C_None then
  572. begin
  573. { check for
  574. Bxx xxx
  575. <several instructions>
  576. xxx:
  577. }
  578. l:=0;
  579. WasLast:=False;
  580. GetNextInstruction(p, hp1);
  581. while assigned(hp1) and
  582. (l<=4) and
  583. CanBeCond(hp1) and
  584. { stop on labels }
  585. not(hp1.typ=ait_label) do
  586. begin
  587. inc(l);
  588. if MustBeLast(hp1) then
  589. begin
  590. WasLast:=True;
  591. GetNextInstruction(hp1,hp1);
  592. break;
  593. end
  594. else
  595. GetNextInstruction(hp1,hp1);
  596. end;
  597. if assigned(hp1) then
  598. begin
  599. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  600. begin
  601. if (l<=4) and (l>0) then
  602. begin
  603. condition:=inverse_cond(taicpu(p).condition);
  604. hp2:=p;
  605. GetNextInstruction(p,hp1);
  606. p:=hp1;
  607. repeat
  608. if hp1.typ=ait_instruction then
  609. taicpu(hp1).condition:=condition;
  610. if MustBeLast(hp1) then
  611. begin
  612. GetNextInstruction(hp1,hp1);
  613. break;
  614. end
  615. else
  616. GetNextInstruction(hp1,hp1);
  617. until not(assigned(hp1)) or
  618. not(CanBeCond(hp1)) or
  619. (hp1.typ=ait_label);
  620. { wait with removing else GetNextInstruction could
  621. ignore the label if it was the only usage in the
  622. jump moved away }
  623. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  624. asml.remove(hp2);
  625. hp2.free;
  626. continue;
  627. end;
  628. end
  629. else
  630. { do not perform further optimizations if there is inctructon
  631. in block #1 which can not be optimized.
  632. }
  633. if not WasLast then
  634. begin
  635. { check further for
  636. Bcc xxx
  637. <several instructions 1>
  638. B yyy
  639. xxx:
  640. <several instructions 2>
  641. yyy:
  642. }
  643. { hp2 points to jmp yyy }
  644. hp2:=hp1;
  645. { skip hp1 to xxx }
  646. GetNextInstruction(hp1, hp1);
  647. if assigned(hp2) and
  648. assigned(hp1) and
  649. (l<=3) and
  650. (hp2.typ=ait_instruction) and
  651. (taicpu(hp2).is_jmp) and
  652. (taicpu(hp2).condition=C_None) and
  653. { real label and jump, no further references to the
  654. label are allowed }
  655. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  656. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  657. begin
  658. l:=0;
  659. { skip hp1 to <several moves 2> }
  660. GetNextInstruction(hp1, hp1);
  661. while assigned(hp1) and
  662. CanBeCond(hp1) do
  663. begin
  664. inc(l);
  665. GetNextInstruction(hp1, hp1);
  666. end;
  667. { hp1 points to yyy: }
  668. if assigned(hp1) and
  669. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  670. begin
  671. condition:=inverse_cond(taicpu(p).condition);
  672. GetNextInstruction(p,hp1);
  673. hp3:=p;
  674. p:=hp1;
  675. repeat
  676. if hp1.typ=ait_instruction then
  677. taicpu(hp1).condition:=condition;
  678. GetNextInstruction(hp1,hp1);
  679. until not(assigned(hp1)) or
  680. not(CanBeCond(hp1));
  681. { hp2 is still at jmp yyy }
  682. GetNextInstruction(hp2,hp1);
  683. { hp2 is now at xxx: }
  684. condition:=inverse_cond(condition);
  685. GetNextInstruction(hp1,hp1);
  686. { hp1 is now at <several movs 2> }
  687. repeat
  688. taicpu(hp1).condition:=condition;
  689. GetNextInstruction(hp1,hp1);
  690. until not(assigned(hp1)) or
  691. not(CanBeCond(hp1)) or
  692. (hp1.typ=ait_label);
  693. {
  694. asml.remove(hp1.next)
  695. hp1.next.free;
  696. asml.remove(hp1);
  697. hp1.free;
  698. }
  699. { remove Bcc }
  700. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  701. asml.remove(hp3);
  702. hp3.free;
  703. { remove jmp }
  704. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  705. asml.remove(hp2);
  706. hp2.free;
  707. continue;
  708. end;
  709. end;
  710. end;
  711. end;
  712. end;
  713. end;
  714. end;
  715. end;
  716. p := tai(p.next)
  717. end;
  718. end;
  719. function TCpuAsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
  720. begin
  721. If (p1.typ = ait_instruction) and (taicpu(p1).opcode=A_BL) then
  722. Result:=true
  723. else
  724. Result:=inherited RegInInstruction(Reg, p1);
  725. end;
  726. const
  727. { set of opcode which might or do write to memory }
  728. { TODO : extend armins.dat to contain r/w info }
  729. opcode_could_mem_write = [A_B,A_BL,A_BLX,A_BKPT,A_BX,A_STR,A_STRB,A_STRBT,
  730. A_STRH,A_STRT,A_STF,A_SFM,A_STM,A_FSTS,A_FSTD];
  731. function TCpuPreRegallocScheduler.PeepHoleOptPass1Cpu(var p: tai): boolean;
  732. { TODO : schedule also forward }
  733. { TODO : schedule distance > 1 }
  734. var
  735. hp1,hp2,hp3,hp4,hp5 : tai;
  736. list : TAsmList;
  737. begin
  738. result:=true;
  739. list:=TAsmList.Create;
  740. p := BlockStart;
  741. { UsedRegs := []; }
  742. while (p <> BlockEnd) Do
  743. begin
  744. if (p.typ=ait_instruction) and
  745. GetNextInstruction(p,hp1) and
  746. (hp1.typ=ait_instruction) and
  747. { for now we don't reschedule if the previous instruction changes potentially a memory location }
  748. ( (not(taicpu(p).opcode in opcode_could_mem_write) and
  749. not(RegModifiedByInstruction(NR_PC,p)) and
  750. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH])
  751. ) or
  752. ((taicpu(p).opcode in [A_STM,A_STRB,A_STRH,A_STR]) and
  753. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
  754. ((taicpu(hp1).oper[1]^.ref^.base=NR_PC) or
  755. (assigned(taicpu(hp1).oper[1]^.ref^.symboldata) and
  756. (taicpu(hp1).oper[1]^.ref^.offset=0)
  757. )
  758. ) or
  759. { try to prove that the memory accesses don't overlapp }
  760. ((taicpu(p).opcode in [A_STRB,A_STRH,A_STR]) and
  761. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
  762. (taicpu(p).oper[1]^.ref^.base=taicpu(hp1).oper[1]^.ref^.base) and
  763. (taicpu(p).oppostfix=PF_None) and
  764. (taicpu(hp1).oppostfix=PF_None) and
  765. (taicpu(p).oper[1]^.ref^.index=NR_NO) and
  766. (taicpu(hp1).oper[1]^.ref^.index=NR_NO) and
  767. { get operand sizes and check if the offset distance is large enough to ensure no overlapp }
  768. (abs(taicpu(p).oper[1]^.ref^.offset-taicpu(hp1).oper[1]^.ref^.offset)>=max(tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)],tcgsize2size[reg_cgsize(taicpu(hp1).oper[0]^.reg)]))
  769. )
  770. )
  771. ) and
  772. GetNextInstruction(hp1,hp2) and
  773. (hp2.typ=ait_instruction) and
  774. { loaded register used by next instruction? }
  775. (RegInInstruction(taicpu(hp1).oper[0]^.reg,hp2)) and
  776. { loaded register not used by previous instruction? }
  777. not(RegInInstruction(taicpu(hp1).oper[0]^.reg,p)) and
  778. { same condition? }
  779. (taicpu(p).condition=taicpu(hp1).condition) and
  780. { first instruction might not change the register used as base }
  781. ((taicpu(hp1).oper[1]^.ref^.base=NR_NO) or
  782. not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.base,p))
  783. ) and
  784. { first instruction might not change the register used as index }
  785. ((taicpu(hp1).oper[1]^.ref^.index=NR_NO) or
  786. not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.index,p))
  787. ) then
  788. begin
  789. hp3:=tai(p.Previous);
  790. hp5:=tai(p.next);
  791. asml.Remove(p);
  792. { if there is a reg. dealloc instruction associated with p, move it together with p }
  793. { before the instruction? }
  794. while assigned(hp3) and (hp3.typ<>ait_instruction) do
  795. begin
  796. if (hp3.typ=ait_regalloc) and (tai_regalloc(hp3).ratype in [ra_dealloc]) and
  797. RegInInstruction(tai_regalloc(hp3).reg,p) then
  798. begin
  799. hp4:=hp3;
  800. hp3:=tai(hp3.Previous);
  801. asml.Remove(hp4);
  802. list.Concat(hp4);
  803. end
  804. else
  805. hp3:=tai(hp3.Previous);
  806. end;
  807. list.Concat(p);
  808. { after the instruction? }
  809. while assigned(hp5) and (hp5.typ<>ait_instruction) do
  810. begin
  811. if (hp5.typ=ait_regalloc) and (tai_regalloc(hp5).ratype in [ra_dealloc]) and
  812. RegInInstruction(tai_regalloc(hp5).reg,p) then
  813. begin
  814. hp4:=hp5;
  815. hp5:=tai(hp5.next);
  816. asml.Remove(hp4);
  817. list.Concat(hp4);
  818. end
  819. else
  820. hp5:=tai(hp5.Next);
  821. end;
  822. asml.Remove(hp1);
  823. {$ifdef DEBUG_PREREGSCHEDULER}
  824. asml.InsertBefore(tai_comment.Create(strpnew('Rescheduled')),hp2);
  825. {$endif DEBUG_PREREGSCHEDULER}
  826. asml.InsertBefore(hp1,hp2);
  827. asml.InsertListBefore(hp2,list);
  828. end;
  829. p := tai(p.next)
  830. end;
  831. list.Free;
  832. end;
  833. procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
  834. begin
  835. { TODO: Add optimizer code }
  836. end;
  837. begin
  838. casmoptimizer:=TCpuAsmOptimizer;
  839. cpreregallocscheduler:=TCpuPreRegallocScheduler;
  840. End.