cpuinfo.pas 4.7 KB

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  1. {
  2. Copyright (c) 1998-2000 by Florian Klaempfl
  3. Basic Processor information
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. Unit cpuinfo;
  18. {$i fpcdefs.inc}
  19. Interface
  20. uses
  21. globtype;
  22. Type
  23. bestreal = extended;
  24. {$if FPC_FULLVERSION>20700}
  25. {$ifdef FPC_HAS_TYPE_EXTENDED}
  26. bestrealrec = TExtended80Rec;
  27. {$else}
  28. bestrealrec = TDoubleRec;
  29. {$endif}
  30. {$endif FPC_FULLVERSION>20700}
  31. ts32real = single;
  32. ts64real = double;
  33. ts80real = extended;
  34. ts128real = type extended;
  35. ts64comp = type extended;
  36. pbestreal=^bestreal;
  37. tcputype =
  38. (cpu_none,
  39. cpu_athlon64,
  40. cpu_core_i,
  41. cpu_core_avx,
  42. cpu_core_avx2
  43. );
  44. tfputype =
  45. (fpu_none,
  46. // fpu_soft, { generic }
  47. fpu_sse64,
  48. fpu_sse3,
  49. fpu_ssse3,
  50. fpu_sse41,
  51. fpu_sse42,
  52. fpu_avx,
  53. fpu_avx2
  54. );
  55. tcontrollertype =
  56. (ct_none
  57. );
  58. Const
  59. { Is there support for dealing with multiple microcontrollers available }
  60. { for this platform? }
  61. ControllerSupport = true;
  62. { Size of native extended type }
  63. extended_size = 10;
  64. { Size of a multimedia register }
  65. mmreg_size = 16;
  66. { target cpu string (used by compiler options) }
  67. target_cpu_string = 'x86_64';
  68. { We know that there are fields after sramsize
  69. but we don't care about this warning }
  70. {$PUSH}
  71. {$WARN 3177 OFF}
  72. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  73. (
  74. (controllertypestr:''; controllerunitstr:''; flashbase:0; flashsize:0; srambase:0; sramsize:0));
  75. {$POP}
  76. { calling conventions supported by the code generator }
  77. supported_calling_conventions : tproccalloptions = [
  78. pocall_internproc,
  79. { pocall_compilerproc,
  80. pocall_inline,}
  81. pocall_register,
  82. pocall_safecall,
  83. pocall_stdcall,
  84. pocall_cdecl,
  85. pocall_cppdecl,
  86. pocall_mwpascal
  87. ];
  88. cputypestr : array[tcputype] of string[10] = ('',
  89. 'ATHLON64',
  90. 'COREI',
  91. 'COREAVX',
  92. 'COREAVX2'
  93. );
  94. fputypestr : array[tfputype] of string[6] = ('',
  95. // 'SOFT',
  96. 'SSE64',
  97. 'SSE3',
  98. 'SSSE3',
  99. 'SSE41',
  100. 'SSE42',
  101. 'AVX',
  102. 'AVX2'
  103. );
  104. sse_singlescalar = [fpu_sse64..fpu_avx2];
  105. sse_doublescalar = [fpu_sse64..fpu_avx2];
  106. fpu_avx_instructionsets = [fpu_avx,fpu_avx2];
  107. { Supported optimizations, only used for information }
  108. supported_optimizerswitches = genericlevel1optimizerswitches+
  109. genericlevel2optimizerswitches+
  110. genericlevel3optimizerswitches-
  111. { no need to write info about those }
  112. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  113. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_stackframe,cs_userbp,
  114. cs_opt_tailrecursion,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  115. level1optimizerswitches = genericlevel1optimizerswitches;
  116. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  117. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  118. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  119. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_userbp];
  120. type
  121. tcpuflags =
  122. (CPUX86_HAS_SSEUNIT,
  123. CPUX86_HAS_BMI1,
  124. CPUX86_HAS_BMI2,
  125. CPUX86_HAS_POPCNT,
  126. CPUX86_HAS_AVXUNIT,
  127. CPUX86_HAS_LZCNT,
  128. CPUX86_HAS_MOVBE,
  129. CPUX86_HAS_FMA,
  130. CPUX86_HAS_FMA4
  131. );
  132. const
  133. cpu_capabilities : array[tcputype] of set of tcpuflags = (
  134. { cpu_none } [],
  135. { Athlon64 } [CPUX86_HAS_SSEUNIT],
  136. { cpu_core_i } [CPUX86_HAS_SSEUNIT,CPUX86_HAS_POPCNT],
  137. { cpu_core_avx } [CPUX86_HAS_SSEUNIT,CPUX86_HAS_POPCNT,CPUX86_HAS_AVXUNIT],
  138. { cpu_core_avx2 } [CPUX86_HAS_SSEUNIT,CPUX86_HAS_POPCNT,CPUX86_HAS_AVXUNIT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE,CPUX86_HAS_FMA]
  139. );
  140. Implementation
  141. end.