cgcpu.pas 90 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2002 by Florian Klaempfl
  4. This unit implements the code generator for the PowerPC
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,
  23. cgbase,cgobj,
  24. aasmbase,aasmcpu,aasmtai,
  25. cpubase,cpuinfo,node,cg64f32,rgcpu,
  26. parabase;
  27. type
  28. tcgppc = class(tcg)
  29. procedure init_register_allocators;override;
  30. procedure done_register_allocators;override;
  31. { passing parameters, per default the parameter is pushed }
  32. { nr gives the number of the parameter (enumerated from }
  33. { left to right), this allows to move the parameter to }
  34. { register, if the cpu supports register calling }
  35. { conventions }
  36. procedure a_param_const(list : taasmoutput;size : tcgsize;a : aint;const paraloc : tcgpara);override;
  37. procedure a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const paraloc : tcgpara);override;
  38. procedure a_paramaddr_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);override;
  39. procedure a_call_name(list : taasmoutput;const s : string);override;
  40. procedure a_call_reg(list : taasmoutput;reg: tregister); override;
  41. procedure a_op_const_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister); override;
  42. procedure a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  43. procedure a_op_const_reg_reg(list: taasmoutput; op: TOpCg;
  44. size: tcgsize; a: aint; src, dst: tregister); override;
  45. procedure a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
  46. size: tcgsize; src1, src2, dst: tregister); override;
  47. { move instructions }
  48. procedure a_load_const_reg(list : taasmoutput; size: tcgsize; a : aint;reg : tregister);override;
  49. procedure a_load_reg_ref(list : taasmoutput; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  50. procedure a_load_ref_reg(list : taasmoutput; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  51. procedure a_load_reg_reg(list : taasmoutput; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  52. { fpu move instructions }
  53. procedure a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister); override;
  54. procedure a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister); override;
  55. procedure a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference); override;
  56. { comparison operations }
  57. procedure a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  58. l : tasmlabel);override;
  59. procedure a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  60. procedure a_jmp_name(list : taasmoutput;const s : string); override;
  61. procedure a_jmp_always(list : taasmoutput;l: tasmlabel); override;
  62. procedure a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel); override;
  63. procedure g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  64. procedure g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);override;
  65. procedure g_proc_exit(list : taasmoutput;parasize : longint;nostackframe:boolean); override;
  66. procedure a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);override;
  67. procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aint);override;
  68. procedure g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef); override;
  69. { find out whether a is of the form 11..00..11b or 00..11...00. If }
  70. { that's the case, we can use rlwinm to do an AND operation }
  71. function get_rlwi_const(a: aint; var l1, l2: longint): boolean;
  72. procedure a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
  73. private
  74. (* NOT IN USE: *)
  75. procedure g_stackframe_entry_mac(list : taasmoutput;localsize : longint);
  76. (* NOT IN USE: *)
  77. procedure g_return_from_proc_mac(list : taasmoutput;parasize : aint);
  78. { Make sure ref is a valid reference for the PowerPC and sets the }
  79. { base to the value of the index if (base = R_NO). }
  80. { Returns true if the reference contained a base, index and an }
  81. { offset or symbol, in which case the base will have been changed }
  82. { to a tempreg (which has to be freed by the caller) containing }
  83. { the sum of part of the original reference }
  84. function fixref(list: taasmoutput; var ref: treference): boolean;
  85. { returns whether a reference can be used immediately in a powerpc }
  86. { instruction }
  87. function issimpleref(const ref: treference): boolean;
  88. { contains the common code of a_load_reg_ref and a_load_ref_reg }
  89. procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
  90. ref: treference);
  91. { creates the correct branch instruction for a given combination }
  92. { of asmcondflags and destination addressing mode }
  93. procedure a_jmp(list: taasmoutput; op: tasmop;
  94. c: tasmcondflag; crval: longint; l: tasmlabel);
  95. function save_regs(list : taasmoutput):longint;
  96. procedure restore_regs(list : taasmoutput);
  97. function get_darwin_call_stub(const s: string): tasmsymbol;
  98. end;
  99. tcg64fppc = class(tcg64f32)
  100. procedure a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);override;
  101. procedure a_op64_const_reg(list : taasmoutput;op:TOpCG;value : int64;reg : tregister64);override;
  102. procedure a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : int64;regsrc,regdst : tregister64);override;
  103. procedure a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);override;
  104. end;
  105. const
  106. TOpCG2AsmOpConstLo: Array[topcg] of TAsmOp = (A_NONE,A_ADDI,A_ANDI_,A_DIVWU,
  107. A_DIVW,A_MULLW, A_MULLW, A_NONE,A_NONE,A_ORI,
  108. A_SRAWI,A_SLWI,A_SRWI,A_SUBI,A_XORI);
  109. TOpCG2AsmOpConstHi: Array[topcg] of TAsmOp = (A_NONE,A_ADDIS,A_ANDIS_,
  110. A_DIVWU,A_DIVW, A_MULLW,A_MULLW,A_NONE,A_NONE,
  111. A_ORIS,A_NONE, A_NONE,A_NONE,A_SUBIS,A_XORIS);
  112. TOpCmp2AsmCond: Array[topcmp] of TAsmCondFlag = (C_NONE,C_EQ,C_GT,
  113. C_LT,C_GE,C_LE,C_NE,C_LE,C_LT,C_GE,C_GT);
  114. implementation
  115. uses
  116. globals,verbose,systems,cutils,
  117. symconst,symdef,symsym,
  118. rgobj,tgobj,cpupi,procinfo,paramgr,
  119. cgutils;
  120. procedure tcgppc.init_register_allocators;
  121. begin
  122. inherited init_register_allocators;
  123. if target_info.system=system_powerpc_darwin then
  124. begin
  125. if pi_needs_got in current_procinfo.flags then
  126. begin
  127. current_procinfo.got:=NR_R31;
  128. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  129. [RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  130. RS_R9,RS_R10,RS_R11,RS_R12,RS_R30,RS_R29,
  131. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  132. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  133. RS_R14,RS_R13],first_int_imreg,[]);
  134. end
  135. else
  136. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  137. [RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  138. RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
  139. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  140. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  141. RS_R14,RS_R13],first_int_imreg,[]);
  142. end
  143. else
  144. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  145. [RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  146. RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
  147. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  148. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  149. RS_R14,RS_R13],first_int_imreg,[]);
  150. case target_info.abi of
  151. abi_powerpc_aix:
  152. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  153. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,
  154. RS_F10,RS_F11,RS_F12,RS_F13,RS_F31,RS_F30,RS_F29,RS_F28,RS_F27,
  155. RS_F26,RS_F25,RS_F24,RS_F23,RS_F22,RS_F21,RS_F20,RS_F19,RS_F18,
  156. RS_F17,RS_F16,RS_F15,RS_F14],first_fpu_imreg,[]);
  157. abi_powerpc_sysv:
  158. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  159. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,
  160. RS_F31,RS_F30,RS_F29,RS_F28,RS_F27,RS_F26,RS_F25,RS_F24,RS_F23,
  161. RS_F22,RS_F21,RS_F20,RS_F19,RS_F18,RS_F17,RS_F16,RS_F15,RS_F14,
  162. RS_F13,RS_F12,RS_F11,RS_F10],first_fpu_imreg,[]);
  163. else
  164. internalerror(2003122903);
  165. end;
  166. {$warning FIX ME}
  167. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
  168. [RS_M0,RS_M1,RS_M2],first_mm_imreg,[]);
  169. end;
  170. procedure tcgppc.done_register_allocators;
  171. begin
  172. rg[R_INTREGISTER].free;
  173. rg[R_FPUREGISTER].free;
  174. rg[R_MMREGISTER].free;
  175. inherited done_register_allocators;
  176. end;
  177. procedure tcgppc.a_param_const(list : taasmoutput;size : tcgsize;a : aint;const paraloc : tcgpara);
  178. var
  179. ref: treference;
  180. begin
  181. paraloc.check_simple_location;
  182. case paraloc.location^.loc of
  183. LOC_REGISTER,LOC_CREGISTER:
  184. a_load_const_reg(list,size,a,paraloc.location^.register);
  185. LOC_REFERENCE:
  186. begin
  187. reference_reset(ref);
  188. ref.base:=paraloc.location^.reference.index;
  189. ref.offset:=paraloc.location^.reference.offset;
  190. a_load_const_ref(list,size,a,ref);
  191. end;
  192. else
  193. internalerror(2002081101);
  194. end;
  195. end;
  196. procedure tcgppc.a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const paraloc : tcgpara);
  197. var
  198. ref: treference;
  199. tmpreg: tregister;
  200. begin
  201. paraloc.check_simple_location;
  202. case paraloc.location^.loc of
  203. LOC_REGISTER,LOC_CREGISTER:
  204. a_load_ref_reg(list,size,size,r,paraloc.location^.register);
  205. LOC_REFERENCE:
  206. begin
  207. reference_reset_base(ref,paraloc.location^.reference.index,paraloc.location^.reference.offset);
  208. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  209. a_load_ref_reg(list,size,size,r,tmpreg);
  210. a_load_reg_ref(list,size,size,tmpreg,ref);
  211. end;
  212. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  213. case size of
  214. OS_F32, OS_F64:
  215. a_loadfpu_ref_reg(list,size,r,paraloc.location^.register);
  216. else
  217. internalerror(2002072801);
  218. end;
  219. else
  220. internalerror(2002081103);
  221. end;
  222. end;
  223. procedure tcgppc.a_paramaddr_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);
  224. var
  225. ref: treference;
  226. tmpreg: tregister;
  227. begin
  228. paraloc.check_simple_location;
  229. case paraloc.location^.loc of
  230. LOC_REGISTER,LOC_CREGISTER:
  231. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  232. LOC_REFERENCE:
  233. begin
  234. reference_reset(ref);
  235. ref.base := paraloc.location^.reference.index;
  236. ref.offset := paraloc.location^.reference.offset;
  237. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  238. a_loadaddr_ref_reg(list,r,tmpreg);
  239. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  240. end;
  241. else
  242. internalerror(2002080701);
  243. end;
  244. end;
  245. function tcgppc.get_darwin_call_stub(const s: string): tasmsymbol;
  246. var
  247. stubname: string;
  248. href: treference;
  249. l1: tasmsymbol;
  250. begin
  251. { function declared in the current unit? }
  252. result := objectlibrary.getasmsymbol(s);
  253. if not(assigned(result)) then
  254. begin
  255. stubname := 'L'+s+'$stub';
  256. result := objectlibrary.getasmsymbol(stubname);
  257. end;
  258. if assigned(result) then
  259. exit;
  260. if not(assigned(importssection)) then
  261. importssection:=TAAsmoutput.create;
  262. importsSection.concat(Tai_section.Create(sec_data,'',0));
  263. importsSection.concat(Tai_direct.create(strpnew('.section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16')));
  264. importsSection.concat(Tai_align.Create(4));
  265. result := objectlibrary.newasmsymbol(stubname,AB_EXTERNAL,AT_FUNCTION);
  266. importsSection.concat(Tai_symbol.Create(result,0));
  267. importsSection.concat(Tai_direct.create(strpnew((#9+'.indirect_symbol ')+s)));
  268. l1 := objectlibrary.newasmsymbol('L'+s+'$lazy_ptr',AB_EXTERNAL,AT_FUNCTION);
  269. reference_reset_symbol(href,l1,0);
  270. {$ifdef powerpc}
  271. href.refaddr := addr_hi;
  272. importsSection.concat(taicpu.op_reg_ref(A_LIS,NR_R11,href));
  273. href.refaddr := addr_lo;
  274. href.base := NR_R11;
  275. importsSection.concat(taicpu.op_reg_ref(A_LWZU,NR_R12,href));
  276. importsSection.concat(taicpu.op_reg(A_MTCTR,NR_R12));
  277. importsSection.concat(taicpu.op_none(A_BCTR));
  278. {$else powerpc}
  279. internalerror(2004010502);
  280. {$endif powerpc}
  281. importsSection.concat(Tai_section.Create(sec_data,'',0));
  282. importsSection.concat(Tai_direct.create(strpnew('.lazy_symbol_pointer')));
  283. importsSection.concat(Tai_symbol.Create(l1,0));
  284. importsSection.concat(Tai_direct.create(strpnew((#9+'.indirect_symbol ')+s)));
  285. importsSection.concat(tai_const.createname(strpnew('dyld_stub_binding_helper'),AT_FUNCTION,0));
  286. end;
  287. { calling a procedure by name }
  288. procedure tcgppc.a_call_name(list : taasmoutput;const s : string);
  289. var
  290. href : treference;
  291. begin
  292. { MacOS: The linker on MacOS (PPCLink) inserts a call to glue code,
  293. if it is a cross-TOC call. If so, it also replaces the NOP
  294. with some restore code.}
  295. if (target_info.system <> system_powerpc_darwin) then
  296. begin
  297. list.concat(taicpu.op_sym(A_BL,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION)));
  298. if target_info.system=system_powerpc_macos then
  299. list.concat(taicpu.op_none(A_NOP));
  300. end
  301. else
  302. begin
  303. list.concat(taicpu.op_sym(A_BL,get_darwin_call_stub(s)));
  304. end;
  305. {
  306. the compiler does not properly set this flag anymore in pass 1, and
  307. for now we only need it after pass 2 (I hope) (JM)
  308. if not(pi_do_call in current_procinfo.flags) then
  309. internalerror(2003060703);
  310. }
  311. include(current_procinfo.flags,pi_do_call);
  312. end;
  313. { calling a procedure by address }
  314. procedure tcgppc.a_call_reg(list : taasmoutput;reg: tregister);
  315. var
  316. tmpreg : tregister;
  317. tmpref : treference;
  318. begin
  319. if target_info.system=system_powerpc_macos then
  320. begin
  321. {Generate instruction to load the procedure address from
  322. the transition vector.}
  323. //TODO: Support cross-TOC calls.
  324. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  325. reference_reset(tmpref);
  326. tmpref.offset := 0;
  327. //tmpref.symaddr := refs_full;
  328. tmpref.base:= reg;
  329. list.concat(taicpu.op_reg_ref(A_LWZ,tmpreg,tmpref));
  330. list.concat(taicpu.op_reg(A_MTCTR,tmpreg));
  331. end
  332. else
  333. list.concat(taicpu.op_reg(A_MTCTR,reg));
  334. list.concat(taicpu.op_none(A_BCTRL));
  335. //if target_info.system=system_powerpc_macos then
  336. // //NOP is not needed here.
  337. // list.concat(taicpu.op_none(A_NOP));
  338. include(current_procinfo.flags,pi_do_call);
  339. {
  340. if not(pi_do_call in current_procinfo.flags) then
  341. internalerror(2003060704);
  342. }
  343. //list.concat(tai_comment.create(strpnew('***** a_call_reg')));
  344. end;
  345. {********************** load instructions ********************}
  346. procedure tcgppc.a_load_const_reg(list : taasmoutput; size: TCGSize; a : aint; reg : TRegister);
  347. begin
  348. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  349. internalerror(2002090902);
  350. if (a >= low(smallint)) and
  351. (a <= high(smallint)) then
  352. list.concat(taicpu.op_reg_const(A_LI,reg,smallint(a)))
  353. else if ((a and $ffff) <> 0) then
  354. begin
  355. list.concat(taicpu.op_reg_const(A_LI,reg,smallint(a and $ffff)));
  356. if ((a shr 16) <> 0) or
  357. (smallint(a and $ffff) < 0) then
  358. list.concat(taicpu.op_reg_reg_const(A_ADDIS,reg,reg,
  359. smallint((a shr 16)+ord(smallint(a and $ffff) < 0))))
  360. end
  361. else
  362. list.concat(taicpu.op_reg_const(A_LIS,reg,smallint(a shr 16)));
  363. end;
  364. procedure tcgppc.a_load_reg_ref(list : taasmoutput; fromsize, tosize: TCGSize; reg : tregister;const ref : treference);
  365. const
  366. StoreInstr: Array[OS_8..OS_32,boolean, boolean] of TAsmOp =
  367. { indexed? updating?}
  368. (((A_STB,A_STBU),(A_STBX,A_STBUX)),
  369. ((A_STH,A_STHU),(A_STHX,A_STHUX)),
  370. ((A_STW,A_STWU),(A_STWX,A_STWUX)));
  371. var
  372. op: TAsmOp;
  373. ref2: TReference;
  374. begin
  375. ref2 := ref;
  376. fixref(list,ref2);
  377. if tosize in [OS_S8..OS_S16] then
  378. { storing is the same for signed and unsigned values }
  379. tosize := tcgsize(ord(tosize)-(ord(OS_S8)-ord(OS_8)));
  380. { 64 bit stuff should be handled separately }
  381. if tosize in [OS_64,OS_S64] then
  382. internalerror(200109236);
  383. op := storeinstr[tcgsize2unsigned[tosize],ref2.index<>NR_NO,false];
  384. a_load_store(list,op,reg,ref2);
  385. End;
  386. procedure tcgppc.a_load_ref_reg(list : taasmoutput; fromsize,tosize : tcgsize;const ref: treference;reg : tregister);
  387. const
  388. LoadInstr: Array[OS_8..OS_S32,boolean, boolean] of TAsmOp =
  389. { indexed? updating?}
  390. (((A_LBZ,A_LBZU),(A_LBZX,A_LBZUX)),
  391. ((A_LHZ,A_LHZU),(A_LHZX,A_LHZUX)),
  392. ((A_LWZ,A_LWZU),(A_LWZX,A_LWZUX)),
  393. { 64bit stuff should be handled separately }
  394. ((A_NONE,A_NONE),(A_NONE,A_NONE)),
  395. { 128bit stuff too }
  396. ((A_NONE,A_NONE),(A_NONE,A_NONE)),
  397. { there's no load-byte-with-sign-extend :( }
  398. ((A_LBZ,A_LBZU),(A_LBZX,A_LBZUX)),
  399. ((A_LHA,A_LHAU),(A_LHAX,A_LHAUX)),
  400. ((A_LWZ,A_LWZU),(A_LWZX,A_LWZUX)));
  401. var
  402. op: tasmop;
  403. tmpreg: tregister;
  404. ref2, tmpref: treference;
  405. begin
  406. { TODO: optimize/take into consideration fromsize/tosize. Will }
  407. { probably only matter for OS_S8 loads though }
  408. if not(fromsize in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  409. internalerror(2002090902);
  410. ref2 := ref;
  411. fixref(list,ref2);
  412. { the caller is expected to have adjusted the reference already }
  413. { in this case }
  414. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  415. fromsize := tosize;
  416. op := loadinstr[fromsize,ref2.index<>NR_NO,false];
  417. a_load_store(list,op,reg,ref2);
  418. { sign extend shortint if necessary, since there is no }
  419. { load instruction that does that automatically (JM) }
  420. if fromsize = OS_S8 then
  421. list.concat(taicpu.op_reg_reg(A_EXTSB,reg,reg));
  422. end;
  423. procedure tcgppc.a_load_reg_reg(list : taasmoutput;fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  424. var
  425. instr: taicpu;
  426. begin
  427. case tosize of
  428. OS_8:
  429. instr := taicpu.op_reg_reg_const_const_const(A_RLWINM,
  430. reg2,reg1,0,31-8+1,31);
  431. OS_S8:
  432. instr := taicpu.op_reg_reg(A_EXTSB,reg2,reg1);
  433. OS_16:
  434. instr := taicpu.op_reg_reg_const_const_const(A_RLWINM,
  435. reg2,reg1,0,31-16+1,31);
  436. OS_S16:
  437. instr := taicpu.op_reg_reg(A_EXTSH,reg2,reg1);
  438. OS_32,OS_S32:
  439. instr := taicpu.op_reg_reg(A_MR,reg2,reg1);
  440. else internalerror(2002090901);
  441. end;
  442. list.concat(instr);
  443. rg[R_INTREGISTER].add_move_instruction(instr);
  444. end;
  445. procedure tcgppc.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister);
  446. var
  447. instr: taicpu;
  448. begin
  449. instr := taicpu.op_reg_reg(A_FMR,reg2,reg1);
  450. list.concat(instr);
  451. rg[R_FPUREGISTER].add_move_instruction(instr);
  452. end;
  453. procedure tcgppc.a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister);
  454. const
  455. FpuLoadInstr: Array[OS_F32..OS_F64,boolean, boolean] of TAsmOp =
  456. { indexed? updating?}
  457. (((A_LFS,A_LFSU),(A_LFSX,A_LFSUX)),
  458. ((A_LFD,A_LFDU),(A_LFDX,A_LFDUX)));
  459. var
  460. op: tasmop;
  461. ref2: treference;
  462. begin
  463. { several functions call this procedure with OS_32 or OS_64 }
  464. { so this makes life easier (FK) }
  465. case size of
  466. OS_32,OS_F32:
  467. size:=OS_F32;
  468. OS_64,OS_F64,OS_C64:
  469. size:=OS_F64;
  470. else
  471. internalerror(200201121);
  472. end;
  473. ref2 := ref;
  474. fixref(list,ref2);
  475. op := fpuloadinstr[size,ref2.index <> NR_NO,false];
  476. a_load_store(list,op,reg,ref2);
  477. end;
  478. procedure tcgppc.a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference);
  479. const
  480. FpuStoreInstr: Array[OS_F32..OS_F64,boolean, boolean] of TAsmOp =
  481. { indexed? updating?}
  482. (((A_STFS,A_STFSU),(A_STFSX,A_STFSUX)),
  483. ((A_STFD,A_STFDU),(A_STFDX,A_STFDUX)));
  484. var
  485. op: tasmop;
  486. ref2: treference;
  487. begin
  488. if not(size in [OS_F32,OS_F64]) then
  489. internalerror(200201122);
  490. ref2 := ref;
  491. fixref(list,ref2);
  492. op := fpustoreinstr[size,ref2.index <> NR_NO,false];
  493. a_load_store(list,op,reg,ref2);
  494. end;
  495. procedure tcgppc.a_op_const_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister);
  496. begin
  497. a_op_const_reg_reg(list,op,size,a,reg,reg);
  498. end;
  499. procedure tcgppc.a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  500. begin
  501. a_op_reg_reg_reg(list,op,size,src,dst,dst);
  502. end;
  503. procedure tcgppc.a_op_const_reg_reg(list: taasmoutput; op: TOpCg;
  504. size: tcgsize; a: aint; src, dst: tregister);
  505. var
  506. l1,l2: longint;
  507. oplo, ophi: tasmop;
  508. scratchreg: tregister;
  509. useReg, gotrlwi: boolean;
  510. procedure do_lo_hi;
  511. begin
  512. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,word(a)));
  513. list.concat(taicpu.op_reg_reg_const(ophi,dst,dst,word(a shr 16)));
  514. end;
  515. begin
  516. if op = OP_SUB then
  517. begin
  518. a_op_const_reg_reg(list,OP_ADD,size,-a,src,dst);
  519. exit;
  520. end;
  521. ophi := TOpCG2AsmOpConstHi[op];
  522. oplo := TOpCG2AsmOpConstLo[op];
  523. gotrlwi := get_rlwi_const(a,l1,l2);
  524. if (op in [OP_AND,OP_OR,OP_XOR]) then
  525. begin
  526. if (a = 0) then
  527. begin
  528. if op = OP_AND then
  529. list.concat(taicpu.op_reg_const(A_LI,dst,0))
  530. else
  531. a_load_reg_reg(list,size,size,src,dst);
  532. exit;
  533. end
  534. else if (a = -1) then
  535. begin
  536. case op of
  537. OP_OR:
  538. list.concat(taicpu.op_reg_const(A_LI,dst,-1));
  539. OP_XOR:
  540. list.concat(taicpu.op_reg_reg(A_NOT,dst,src));
  541. OP_AND:
  542. a_load_reg_reg(list,size,size,src,dst);
  543. end;
  544. exit;
  545. end
  546. else if (aword(a) <= high(word)) and
  547. ((op <> OP_AND) or
  548. not gotrlwi) then
  549. begin
  550. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,word(a)));
  551. exit;
  552. end;
  553. { all basic constant instructions also have a shifted form that }
  554. { works only on the highest 16bits, so if lo(a) is 0, we can }
  555. { use that one }
  556. if (word(a) = 0) and
  557. (not(op = OP_AND) or
  558. not gotrlwi) then
  559. begin
  560. list.concat(taicpu.op_reg_reg_const(ophi,dst,src,word(a shr 16)));
  561. exit;
  562. end;
  563. end
  564. else if (op = OP_ADD) then
  565. if a = 0 then
  566. begin
  567. a_load_reg_reg(list,size,size,src,dst);
  568. exit
  569. end
  570. else if (a >= low(smallint)) and
  571. (a <= high(smallint)) then
  572. begin
  573. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,smallint(a)));
  574. exit;
  575. end;
  576. { otherwise, the instructions we can generate depend on the }
  577. { operation }
  578. useReg := false;
  579. case op of
  580. OP_DIV,OP_IDIV:
  581. if (a = 0) then
  582. internalerror(200208103)
  583. else if (a = 1) then
  584. begin
  585. a_load_reg_reg(list,OS_INT,OS_INT,src,dst);
  586. exit
  587. end
  588. else if ispowerof2(a,l1) then
  589. begin
  590. case op of
  591. OP_DIV:
  592. list.concat(taicpu.op_reg_reg_const(A_SRWI,dst,src,l1));
  593. OP_IDIV:
  594. begin
  595. list.concat(taicpu.op_reg_reg_const(A_SRAWI,dst,src,l1));
  596. list.concat(taicpu.op_reg_reg(A_ADDZE,dst,dst));
  597. end;
  598. end;
  599. exit;
  600. end
  601. else
  602. usereg := true;
  603. OP_IMUL, OP_MUL:
  604. if (a = 0) then
  605. begin
  606. list.concat(taicpu.op_reg_const(A_LI,dst,0));
  607. exit
  608. end
  609. else if (a = 1) then
  610. begin
  611. a_load_reg_reg(list,OS_INT,OS_INT,src,dst);
  612. exit
  613. end
  614. else if ispowerof2(a,l1) then
  615. list.concat(taicpu.op_reg_reg_const(A_SLWI,dst,src,l1))
  616. else if (longint(a) >= low(smallint)) and
  617. (longint(a) <= high(smallint)) then
  618. list.concat(taicpu.op_reg_reg_const(A_MULLI,dst,src,smallint(a)))
  619. else
  620. usereg := true;
  621. OP_ADD:
  622. begin
  623. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,smallint(a)));
  624. list.concat(taicpu.op_reg_reg_const(ophi,dst,dst,
  625. smallint((a shr 16) + ord(smallint(a) < 0))));
  626. end;
  627. OP_OR:
  628. { try to use rlwimi }
  629. if gotrlwi and
  630. (src = dst) then
  631. begin
  632. scratchreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  633. list.concat(taicpu.op_reg_const(A_LI,scratchreg,-1));
  634. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,dst,
  635. scratchreg,0,l1,l2));
  636. end
  637. else
  638. do_lo_hi;
  639. OP_AND:
  640. { try to use rlwinm }
  641. if gotrlwi then
  642. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,dst,
  643. src,0,l1,l2))
  644. else
  645. useReg := true;
  646. OP_XOR:
  647. do_lo_hi;
  648. OP_SHL,OP_SHR,OP_SAR:
  649. begin
  650. if (a and 31) <> 0 Then
  651. list.concat(taicpu.op_reg_reg_const(
  652. TOpCG2AsmOpConstLo[Op],dst,src,a and 31))
  653. else
  654. a_load_reg_reg(list,size,size,src,dst);
  655. if (a shr 5) <> 0 then
  656. internalError(68991);
  657. end
  658. else
  659. internalerror(200109091);
  660. end;
  661. { if all else failed, load the constant in a register and then }
  662. { perform the operation }
  663. if useReg then
  664. begin
  665. scratchreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  666. a_load_const_reg(list,OS_32,a,scratchreg);
  667. a_op_reg_reg_reg(list,op,OS_32,scratchreg,src,dst);
  668. end;
  669. end;
  670. procedure tcgppc.a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
  671. size: tcgsize; src1, src2, dst: tregister);
  672. const
  673. op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
  674. (A_NONE,A_ADD,A_AND,A_DIVWU,A_DIVW,A_MULLW,A_MULLW,A_NEG,A_NOT,A_OR,
  675. A_SRAW,A_SLW,A_SRW,A_SUB,A_XOR);
  676. begin
  677. case op of
  678. OP_NEG,OP_NOT:
  679. begin
  680. list.concat(taicpu.op_reg_reg(op_reg_reg_opcg2asmop[op],dst,src1));
  681. if (op = OP_NOT) and
  682. not(size in [OS_32,OS_S32]) then
  683. { zero/sign extend result again }
  684. a_load_reg_reg(list,OS_32,size,dst,dst);
  685. end;
  686. else
  687. list.concat(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1));
  688. end;
  689. end;
  690. {*************** compare instructructions ****************}
  691. procedure tcgppc.a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  692. l : tasmlabel);
  693. var
  694. p: taicpu;
  695. scratch_register: TRegister;
  696. signed: boolean;
  697. begin
  698. signed := cmp_op in [OC_GT,OC_LT,OC_GTE,OC_LTE];
  699. { in the following case, we generate more efficient code when }
  700. { signed is true }
  701. if (cmp_op in [OC_EQ,OC_NE]) and
  702. (aword(a) > $ffff) then
  703. signed := true;
  704. if signed then
  705. if (a >= low(smallint)) and (a <= high(smallint)) Then
  706. list.concat(taicpu.op_reg_reg_const(A_CMPWI,NR_CR0,reg,a))
  707. else
  708. begin
  709. scratch_register := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  710. a_load_const_reg(list,OS_32,a,scratch_register);
  711. list.concat(taicpu.op_reg_reg_reg(A_CMPW,NR_CR0,reg,scratch_register));
  712. end
  713. else
  714. if (aword(a) <= $ffff) then
  715. list.concat(taicpu.op_reg_reg_const(A_CMPLWI,NR_CR0,reg,aword(a)))
  716. else
  717. begin
  718. scratch_register := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  719. a_load_const_reg(list,OS_32,a,scratch_register);
  720. list.concat(taicpu.op_reg_reg_reg(A_CMPLW,NR_CR0,reg,scratch_register));
  721. end;
  722. a_jmp(list,A_BC,TOpCmp2AsmCond[cmp_op],0,l);
  723. end;
  724. procedure tcgppc.a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;
  725. reg1,reg2 : tregister;l : tasmlabel);
  726. var
  727. p: taicpu;
  728. op: tasmop;
  729. begin
  730. if cmp_op in [OC_GT,OC_LT,OC_GTE,OC_LTE] then
  731. op := A_CMPW
  732. else
  733. op := A_CMPLW;
  734. list.concat(taicpu.op_reg_reg_reg(op,NR_CR0,reg2,reg1));
  735. a_jmp(list,A_BC,TOpCmp2AsmCond[cmp_op],0,l);
  736. end;
  737. procedure tcgppc.a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
  738. begin
  739. a_jmp(list,A_BC,TOpCmp2AsmCond[cond],0,l);
  740. end;
  741. procedure tcgppc.a_jmp_name(list : taasmoutput;const s : string);
  742. var
  743. p : taicpu;
  744. begin
  745. p := taicpu.op_sym(A_B,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION));
  746. p.is_jmp := true;
  747. list.concat(p)
  748. end;
  749. procedure tcgppc.a_jmp_always(list : taasmoutput;l: tasmlabel);
  750. begin
  751. a_jmp(list,A_B,C_None,0,l);
  752. end;
  753. procedure tcgppc.a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel);
  754. var
  755. c: tasmcond;
  756. begin
  757. c := flags_to_cond(f);
  758. a_jmp(list,A_BC,c.cond,c.cr-RS_CR0,l);
  759. end;
  760. procedure tcgppc.g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister);
  761. var
  762. testbit: byte;
  763. bitvalue: boolean;
  764. begin
  765. { get the bit to extract from the conditional register + its }
  766. { requested value (0 or 1) }
  767. testbit := ((f.cr-RS_CR0) * 4);
  768. case f.flag of
  769. F_EQ,F_NE:
  770. begin
  771. inc(testbit,2);
  772. bitvalue := f.flag = F_EQ;
  773. end;
  774. F_LT,F_GE:
  775. begin
  776. bitvalue := f.flag = F_LT;
  777. end;
  778. F_GT,F_LE:
  779. begin
  780. inc(testbit);
  781. bitvalue := f.flag = F_GT;
  782. end;
  783. else
  784. internalerror(200112261);
  785. end;
  786. { load the conditional register in the destination reg }
  787. list.concat(taicpu.op_reg(A_MFCR,reg));
  788. { we will move the bit that has to be tested to bit 0 by rotating }
  789. { left }
  790. testbit := (testbit + 1) and 31;
  791. { extract bit }
  792. list.concat(taicpu.op_reg_reg_const_const_const(
  793. A_RLWINM,reg,reg,testbit,31,31));
  794. { if we need the inverse, xor with 1 }
  795. if not bitvalue then
  796. list.concat(taicpu.op_reg_reg_const(A_XORI,reg,reg,1));
  797. end;
  798. (*
  799. procedure tcgppc.g_cond2reg(list: taasmoutput; const f: TAsmCond; reg: TRegister);
  800. var
  801. testbit: byte;
  802. bitvalue: boolean;
  803. begin
  804. { get the bit to extract from the conditional register + its }
  805. { requested value (0 or 1) }
  806. case f.simple of
  807. false:
  808. begin
  809. { we don't generate this in the compiler }
  810. internalerror(200109062);
  811. end;
  812. true:
  813. case f.cond of
  814. C_None:
  815. internalerror(200109063);
  816. C_LT..C_NU:
  817. begin
  818. testbit := (ord(f.cr) - ord(R_CR0))*4;
  819. inc(testbit,AsmCondFlag2BI[f.cond]);
  820. bitvalue := AsmCondFlagTF[f.cond];
  821. end;
  822. C_T,C_F,C_DNZT,C_DNZF,C_DZT,C_DZF:
  823. begin
  824. testbit := f.crbit
  825. bitvalue := AsmCondFlagTF[f.cond];
  826. end;
  827. else
  828. internalerror(200109064);
  829. end;
  830. end;
  831. { load the conditional register in the destination reg }
  832. list.concat(taicpu.op_reg_reg(A_MFCR,reg));
  833. { we will move the bit that has to be tested to bit 31 -> rotate }
  834. { left by bitpos+1 (remember, this is big-endian!) }
  835. if bitpos <> 31 then
  836. inc(bitpos)
  837. else
  838. bitpos := 0;
  839. { extract bit }
  840. list.concat(taicpu.op_reg_reg_const_const_const(
  841. A_RLWINM,reg,reg,bitpos,31,31));
  842. { if we need the inverse, xor with 1 }
  843. if not bitvalue then
  844. list.concat(taicpu.op_reg_reg_const(A_XORI,reg,reg,1));
  845. end;
  846. *)
  847. { *********** entry/exit code and address loading ************ }
  848. procedure tcgppc.g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);
  849. { generated the entry code of a procedure/function. Note: localsize is the }
  850. { sum of the size necessary for local variables and the maximum possible }
  851. { combined size of ALL the parameters of a procedure called by the current }
  852. { one. }
  853. { This procedure may be called before, as well as after g_return_from_proc }
  854. { is called. NOTE registers are not to be allocated through the register }
  855. { allocator here, because the register colouring has already occured !! }
  856. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  857. href,href2 : treference;
  858. usesfpr,usesgpr,gotgot : boolean;
  859. parastart : aint;
  860. l : tasmlabel;
  861. regcounter2, firstfpureg: Tsuperregister;
  862. hp: tparaitem;
  863. cond : tasmcond;
  864. instr : taicpu;
  865. size: tcgsize;
  866. begin
  867. { CR and LR only have to be saved in case they are modified by the current }
  868. { procedure, but currently this isn't checked, so save them always }
  869. { following is the entry code as described in "Altivec Programming }
  870. { Interface Manual", bar the saving of AltiVec registers }
  871. a_reg_alloc(list,NR_STACK_POINTER_REG);
  872. a_reg_alloc(list,NR_R0);
  873. usesfpr:=false;
  874. if not (po_assembler in current_procinfo.procdef.procoptions) then
  875. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  876. case target_info.abi of
  877. abi_powerpc_aix:
  878. firstfpureg := RS_F14;
  879. abi_powerpc_sysv:
  880. firstfpureg := RS_F9;
  881. else
  882. internalerror(2003122903);
  883. end;
  884. for regcounter:=firstfpureg to RS_F31 do
  885. begin
  886. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  887. begin
  888. usesfpr:= true;
  889. firstregfpu:=regcounter;
  890. break;
  891. end;
  892. end;
  893. usesgpr:=false;
  894. if not (po_assembler in current_procinfo.procdef.procoptions) then
  895. for regcounter2:=RS_R13 to RS_R31 do
  896. begin
  897. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  898. begin
  899. usesgpr:=true;
  900. firstreggpr:=regcounter2;
  901. break;
  902. end;
  903. end;
  904. { save link register? }
  905. if not (po_assembler in current_procinfo.procdef.procoptions) then
  906. if (pi_do_call in current_procinfo.flags) then
  907. begin
  908. { save return address... }
  909. list.concat(taicpu.op_reg(A_MFLR,NR_R0));
  910. { ... in caller's frame }
  911. case target_info.abi of
  912. abi_powerpc_aix:
  913. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_AIX);
  914. abi_powerpc_sysv:
  915. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_SYSV);
  916. end;
  917. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  918. a_reg_dealloc(list,NR_R0);
  919. end;
  920. { save the CR if necessary in callers frame. }
  921. if not (po_assembler in current_procinfo.procdef.procoptions) then
  922. if target_info.abi = abi_powerpc_aix then
  923. if false then { Not needed at the moment. }
  924. begin
  925. a_reg_alloc(list,NR_R0);
  926. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_CR));
  927. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  928. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  929. a_reg_dealloc(list,NR_R0);
  930. end;
  931. { !!! always allocate space for all registers for now !!! }
  932. if not (po_assembler in current_procinfo.procdef.procoptions) then
  933. { if usesfpr or usesgpr then }
  934. begin
  935. a_reg_alloc(list,NR_R12);
  936. { save end of fpr save area }
  937. list.concat(taicpu.op_reg_reg(A_MR,NR_R12,NR_STACK_POINTER_REG));
  938. end;
  939. if (not nostackframe) and
  940. (localsize <> 0) then
  941. begin
  942. if (localsize <= high(smallint)) then
  943. begin
  944. reference_reset_base(href,NR_STACK_POINTER_REG,-localsize);
  945. a_load_store(list,A_STWU,NR_STACK_POINTER_REG,href);
  946. end
  947. else
  948. begin
  949. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  950. { can't use getregisterint here, the register colouring }
  951. { is already done when we get here }
  952. href.index := NR_R11;
  953. a_reg_alloc(list,href.index);
  954. a_load_const_reg(list,OS_S32,-localsize,href.index);
  955. a_load_store(list,A_STWUX,NR_STACK_POINTER_REG,href);
  956. a_reg_dealloc(list,href.index);
  957. end;
  958. end;
  959. { no GOT pointer loaded yet }
  960. gotgot:=false;
  961. if usesfpr then
  962. begin
  963. { save floating-point registers
  964. if (cs_create_pic in aktmoduleswitches) and not(usesgpr) then
  965. begin
  966. a_call_name(objectlibrary.newasmsymbol('_savefpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14)+'_g',AB_EXTERNAL,AT_FUNCTION));
  967. gotgot:=true;
  968. end
  969. else
  970. a_call_name(objectlibrary.newasmsymbol('_savefpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14),AB_EXTERNAL,AT_FUNCTION));
  971. }
  972. reference_reset_base(href,NR_R12,-8);
  973. for regcounter:=firstregfpu to RS_F31 do
  974. begin
  975. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  976. begin
  977. a_loadfpu_reg_ref(list,OS_F64,newreg(R_FPUREGISTER,regcounter,R_SUBNONE),href);
  978. dec(href.offset,8);
  979. end;
  980. end;
  981. { compute end of gpr save area }
  982. a_op_const_reg(list,OP_ADD,OS_ADDR,href.offset+8,NR_R12);
  983. end;
  984. { save gprs and fetch GOT pointer }
  985. if usesgpr then
  986. begin
  987. {
  988. if cs_create_pic in aktmoduleswitches then
  989. begin
  990. a_call_name(objectlibrary.newasmsymbol('_savegpr_'+tostr(ord(firstreggpr)-ord(R_14)+14)+'_g',AB_EXTERNAL,AT_FUNCTION));
  991. gotgot:=true;
  992. end
  993. else
  994. a_call_name(objectlibrary.newasmsymbol('_savegpr_'+tostr(ord(firstreggpr)-ord(R_14)+14),AB_EXTERNAL,AT_FUNCTION))
  995. }
  996. reference_reset_base(href,NR_R12,-4);
  997. for regcounter2:=RS_R13 to RS_R31 do
  998. begin
  999. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1000. begin
  1001. usesgpr:=true;
  1002. a_load_reg_ref(list,OS_INT,OS_INT,newreg(R_INTREGISTER,regcounter2,R_SUBNONE),href);
  1003. dec(href.offset,4);
  1004. end;
  1005. end;
  1006. {
  1007. r.enum:=R_INTREGISTER;
  1008. r.:=;
  1009. reference_reset_base(href,NR_R12,-((NR_R31-firstreggpr) shr 8+1)*4);
  1010. list.concat(taicpu.op_reg_ref(A_STMW,firstreggpr,href));
  1011. }
  1012. end;
  1013. if assigned(current_procinfo.procdef.parast) then
  1014. begin
  1015. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1016. begin
  1017. { copy memory parameters to local parast }
  1018. hp:=tparaitem(current_procinfo.procdef.para.first);
  1019. while assigned(hp) do
  1020. begin
  1021. if (hp.paraloc[calleeside].location^.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
  1022. begin
  1023. if assigned(hp.paraloc[callerside].location^.next) then
  1024. internalerror(2004091210);
  1025. case tvarsym(hp.parasym).localloc.loc of
  1026. LOC_REFERENCE:
  1027. begin
  1028. reference_reset_base(href,tvarsym(hp.parasym).localloc.reference.base,tvarsym(hp.parasym).localloc.reference.offset);
  1029. reference_reset_base(href2,NR_R12,hp.paraloc[callerside].location^.reference.offset);
  1030. { we can't use functions here which allocate registers (FK)
  1031. cg.a_load_ref_ref(list,hp.paraloc[calleeside].size,hp.paraloc[calleeside].size,href2,href);
  1032. }
  1033. case hp.paraloc[calleeside].size of
  1034. OS_F32:
  1035. size := OS_32;
  1036. OS_64,OS_S64:
  1037. size := OS_F64;
  1038. else
  1039. size := hp.paraloc[calleeside].size;
  1040. end;
  1041. case size of
  1042. OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32:
  1043. begin
  1044. cg.a_load_ref_reg(list,size,size,href2,NR_R0);
  1045. cg.a_load_reg_ref(list,size,size,NR_R0,href);
  1046. end;
  1047. OS_F64:
  1048. begin
  1049. cg.a_loadfpu_ref_reg(list,size,href2,NR_F0);
  1050. cg.a_loadfpu_reg_ref(list,size,NR_F0,href);
  1051. end;
  1052. else
  1053. internalerror(2004070910);
  1054. end;
  1055. end;
  1056. {
  1057. LOC_CREGISTER:
  1058. begin
  1059. reference_reset_base(href2,NR_R12,hp.paraloc[callerside].location^.reference.offset);
  1060. cg.a_load_ref_reg(list,hp.paraloc[calleeside].size,hp.paraloc[calleeside].size,href2,tvarsym(hp.parasym).localloc.register);
  1061. end;
  1062. LOC_CFPUREGISTER:
  1063. begin
  1064. reference_reset_base(href2,NR_R12,hp.paraloc[callerside].location^.reference.offset);
  1065. cg.a_loadfpu_ref_reg(list,hp.paraloc[calleeside].size,href2,tvarsym(hp.parasym).localloc.register);
  1066. end;
  1067. else
  1068. internalerror(2004070911);
  1069. }
  1070. end;
  1071. end;
  1072. hp := tparaitem(hp.next);
  1073. end;
  1074. end;
  1075. end;
  1076. if usesfpr or usesgpr then
  1077. a_reg_dealloc(list,NR_R12);
  1078. { if we didn't get the GOT pointer till now, we've to calculate it now }
  1079. if not(gotgot) and (pi_needs_got in current_procinfo.flags) then
  1080. case target_info.system of
  1081. system_powerpc_darwin:
  1082. begin
  1083. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_LR));
  1084. fillchar(cond,sizeof(cond),0);
  1085. cond.simple:=false;
  1086. cond.bo:=20;
  1087. cond.bi:=31;
  1088. instr:=taicpu.op_sym(A_BCL,current_procinfo.gotlabel);
  1089. instr.setcondition(cond);
  1090. list.concat(instr);
  1091. a_label(list,current_procinfo.gotlabel);
  1092. list.concat(taicpu.op_reg_reg(A_MFSPR,current_procinfo.got,NR_LR));
  1093. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_LR,NR_R0));
  1094. end;
  1095. else
  1096. begin
  1097. a_reg_alloc(list,NR_R31);
  1098. { place GOT ptr in r31 }
  1099. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R31,NR_LR));
  1100. end;
  1101. end;
  1102. { save the CR if necessary ( !!! always done currently ) }
  1103. { still need to find out where this has to be done for SystemV
  1104. a_reg_alloc(list,R_0);
  1105. list.concat(taicpu.op_reg_reg(A_MFSPR,R_0,R_CR);
  1106. list.concat(taicpu.op_reg_ref(A_STW,scratch_register,
  1107. new_reference(STACK_POINTER_REG,LA_CR)));
  1108. a_reg_dealloc(list,R_0); }
  1109. { now comes the AltiVec context save, not yet implemented !!! }
  1110. end;
  1111. procedure tcgppc.g_proc_exit(list : taasmoutput;parasize : longint;nostackframe:boolean);
  1112. { This procedure may be called before, as well as after g_stackframe_entry }
  1113. { is called. NOTE registers are not to be allocated through the register }
  1114. { allocator here, because the register colouring has already occured !! }
  1115. var
  1116. regcounter,firstregfpu,firstreggpr: TsuperRegister;
  1117. href : treference;
  1118. usesfpr,usesgpr,genret : boolean;
  1119. regcounter2, firstfpureg:Tsuperregister;
  1120. localsize: aint;
  1121. begin
  1122. { AltiVec context restore, not yet implemented !!! }
  1123. usesfpr:=false;
  1124. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1125. begin
  1126. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1127. case target_info.abi of
  1128. abi_powerpc_aix:
  1129. firstfpureg := RS_F14;
  1130. abi_powerpc_sysv:
  1131. firstfpureg := RS_F9;
  1132. else
  1133. internalerror(2003122903);
  1134. end;
  1135. for regcounter:=firstfpureg to RS_F31 do
  1136. begin
  1137. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1138. begin
  1139. usesfpr:=true;
  1140. firstregfpu:=regcounter;
  1141. break;
  1142. end;
  1143. end;
  1144. end;
  1145. usesgpr:=false;
  1146. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1147. for regcounter2:=RS_R13 to RS_R31 do
  1148. begin
  1149. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1150. begin
  1151. usesgpr:=true;
  1152. firstreggpr:=regcounter2;
  1153. break;
  1154. end;
  1155. end;
  1156. localsize:= tppcprocinfo(current_procinfo).calc_stackframe_size;
  1157. { no return (blr) generated yet }
  1158. genret:=true;
  1159. if usesgpr or usesfpr then
  1160. begin
  1161. { address of gpr save area to r11 }
  1162. { (register allocator is no longer valid at this time and an add of 0 }
  1163. { is translated into a move, which is then registered with the register }
  1164. { allocator, causing a crash }
  1165. if (localsize <> 0) then
  1166. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,localsize,NR_STACK_POINTER_REG,NR_R12)
  1167. else
  1168. list.concat(taicpu.op_reg_reg(A_MR,NR_R12,NR_STACK_POINTER_REG));
  1169. if usesfpr then
  1170. begin
  1171. reference_reset_base(href,NR_R12,-8);
  1172. for regcounter := firstregfpu to RS_F31 do
  1173. begin
  1174. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1175. begin
  1176. a_loadfpu_ref_reg(list,OS_F64,href,newreg(R_FPUREGISTER,regcounter,R_SUBNONE));
  1177. dec(href.offset,8);
  1178. end;
  1179. end;
  1180. inc(href.offset,4);
  1181. end
  1182. else
  1183. reference_reset_base(href,NR_R12,-4);
  1184. for regcounter2:=RS_R13 to RS_R31 do
  1185. begin
  1186. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1187. begin
  1188. usesgpr:=true;
  1189. a_load_ref_reg(list,OS_INT,OS_INT,href,newreg(R_INTREGISTER,regcounter2,R_SUBNONE));
  1190. dec(href.offset,4);
  1191. end;
  1192. end;
  1193. (*
  1194. reference_reset_base(href,r2,-((NR_R31-ord(firstreggpr)) shr 8+1)*4);
  1195. list.concat(taicpu.op_reg_ref(A_LMW,firstreggpr,href));
  1196. *)
  1197. end;
  1198. (*
  1199. { restore fprs and return }
  1200. if usesfpr then
  1201. begin
  1202. { address of fpr save area to r11 }
  1203. r:=NR_R12;
  1204. list.concat(taicpu.op_reg_reg_const(A_ADDI,r,r,(ord(R_F31)-ord(firstregfpu.enum)+1)*8));
  1205. {
  1206. if (pi_do_call in current_procinfo.flags) then
  1207. a_call_name(objectlibrary.newasmsymbol('_restfpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14)+
  1208. '_x',AB_EXTERNAL,AT_FUNCTION))
  1209. else
  1210. { leaf node => lr haven't to be restored }
  1211. a_call_name('_restfpr_'+tostr(ord(firstregfpu.enum)-ord(R_F14)+14)+
  1212. '_l');
  1213. genret:=false;
  1214. }
  1215. end;
  1216. *)
  1217. { if we didn't generate the return code, we've to do it now }
  1218. if genret then
  1219. begin
  1220. { adjust r1 }
  1221. { (register allocator is no longer valid at this time and an add of 0 }
  1222. { is translated into a move, which is then registered with the register }
  1223. { allocator, causing a crash }
  1224. if (not nostackframe) and
  1225. (localsize <> 0) then
  1226. a_op_const_reg(list,OP_ADD,OS_ADDR,localsize,NR_R1);
  1227. { load link register? }
  1228. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1229. begin
  1230. if (pi_do_call in current_procinfo.flags) then
  1231. begin
  1232. case target_info.abi of
  1233. abi_powerpc_aix:
  1234. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_AIX);
  1235. abi_powerpc_sysv:
  1236. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_SYSV);
  1237. end;
  1238. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1239. list.concat(taicpu.op_reg(A_MTLR,NR_R0));
  1240. end;
  1241. { restore the CR if necessary from callers frame}
  1242. if target_info.abi = abi_powerpc_aix then
  1243. if false then { Not needed at the moment. }
  1244. begin
  1245. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1246. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1247. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_CR));
  1248. a_reg_dealloc(list,NR_R0);
  1249. end;
  1250. end;
  1251. list.concat(taicpu.op_none(A_BLR));
  1252. end;
  1253. end;
  1254. function tcgppc.save_regs(list : taasmoutput):longint;
  1255. {Generates code which saves used non-volatile registers in
  1256. the save area right below the address the stackpointer point to.
  1257. Returns the actual used save area size.}
  1258. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  1259. usesfpr,usesgpr: boolean;
  1260. href : treference;
  1261. offset: aint;
  1262. regcounter2, firstfpureg: Tsuperregister;
  1263. begin
  1264. usesfpr:=false;
  1265. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1266. begin
  1267. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1268. case target_info.abi of
  1269. abi_powerpc_aix:
  1270. firstfpureg := RS_F14;
  1271. abi_powerpc_sysv:
  1272. firstfpureg := RS_F9;
  1273. else
  1274. internalerror(2003122903);
  1275. end;
  1276. for regcounter:=firstfpureg to RS_F31 do
  1277. begin
  1278. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1279. begin
  1280. usesfpr:=true;
  1281. firstregfpu:=regcounter;
  1282. break;
  1283. end;
  1284. end;
  1285. end;
  1286. usesgpr:=false;
  1287. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1288. for regcounter2:=RS_R13 to RS_R31 do
  1289. begin
  1290. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1291. begin
  1292. usesgpr:=true;
  1293. firstreggpr:=regcounter2;
  1294. break;
  1295. end;
  1296. end;
  1297. offset:= 0;
  1298. { save floating-point registers }
  1299. if usesfpr then
  1300. for regcounter := firstregfpu to RS_F31 do
  1301. begin
  1302. offset:= offset - 8;
  1303. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1304. list.concat(taicpu.op_reg_ref(A_STFD, tregister(regcounter), href));
  1305. end;
  1306. (* Optimiztion in the future: a_call_name(list,'_savefXX'); *)
  1307. { save gprs in gpr save area }
  1308. if usesgpr then
  1309. if firstreggpr < RS_R30 then
  1310. begin
  1311. offset:= offset - 4 * (RS_R31 - firstreggpr + 1);
  1312. reference_reset_base(href,NR_STACK_POINTER_REG,offset);
  1313. list.concat(taicpu.op_reg_ref(A_STMW,tregister(firstreggpr),href));
  1314. {STMW stores multiple registers}
  1315. end
  1316. else
  1317. begin
  1318. for regcounter := firstreggpr to RS_R31 do
  1319. begin
  1320. offset:= offset - 4;
  1321. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1322. list.concat(taicpu.op_reg_ref(A_STW, newreg(R_INTREGISTER,regcounter,R_SUBWHOLE), href));
  1323. end;
  1324. end;
  1325. { now comes the AltiVec context save, not yet implemented !!! }
  1326. save_regs:= -offset;
  1327. end;
  1328. procedure tcgppc.restore_regs(list : taasmoutput);
  1329. {Generates code which restores used non-volatile registers from
  1330. the save area right below the address the stackpointer point to.}
  1331. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  1332. usesfpr,usesgpr: boolean;
  1333. href : treference;
  1334. offset: integer;
  1335. regcounter2, firstfpureg: Tsuperregister;
  1336. begin
  1337. usesfpr:=false;
  1338. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1339. begin
  1340. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1341. case target_info.abi of
  1342. abi_powerpc_aix:
  1343. firstfpureg := RS_F14;
  1344. abi_powerpc_sysv:
  1345. firstfpureg := RS_F9;
  1346. else
  1347. internalerror(2003122903);
  1348. end;
  1349. for regcounter:=firstfpureg to RS_F31 do
  1350. begin
  1351. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1352. begin
  1353. usesfpr:=true;
  1354. firstregfpu:=regcounter;
  1355. break;
  1356. end;
  1357. end;
  1358. end;
  1359. usesgpr:=false;
  1360. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1361. for regcounter2:=RS_R13 to RS_R31 do
  1362. begin
  1363. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1364. begin
  1365. usesgpr:=true;
  1366. firstreggpr:=regcounter2;
  1367. break;
  1368. end;
  1369. end;
  1370. offset:= 0;
  1371. { restore fp registers }
  1372. if usesfpr then
  1373. for regcounter := firstregfpu to RS_F31 do
  1374. begin
  1375. offset:= offset - 8;
  1376. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1377. list.concat(taicpu.op_reg_ref(A_LFD, newreg(R_FPUREGISTER,regcounter,R_SUBWHOLE), href));
  1378. end;
  1379. (* Optimiztion in the future: a_call_name(list,'_restfXX'); *)
  1380. { restore gprs }
  1381. if usesgpr then
  1382. if firstreggpr < RS_R30 then
  1383. begin
  1384. offset:= offset - 4 * (RS_R31 - firstreggpr + 1);
  1385. reference_reset_base(href,NR_STACK_POINTER_REG,offset); //-220
  1386. list.concat(taicpu.op_reg_ref(A_LMW,tregister(firstreggpr),href));
  1387. {LMW loads multiple registers}
  1388. end
  1389. else
  1390. begin
  1391. for regcounter := firstreggpr to RS_R31 do
  1392. begin
  1393. offset:= offset - 4;
  1394. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1395. list.concat(taicpu.op_reg_ref(A_LWZ, newreg(R_INTREGISTER,regcounter,R_SUBWHOLE), href));
  1396. end;
  1397. end;
  1398. { now comes the AltiVec context restore, not yet implemented !!! }
  1399. end;
  1400. procedure tcgppc.g_stackframe_entry_mac(list : taasmoutput;localsize : longint);
  1401. (* NOT IN USE *)
  1402. { generated the entry code of a procedure/function. Note: localsize is the }
  1403. { sum of the size necessary for local variables and the maximum possible }
  1404. { combined size of ALL the parameters of a procedure called by the current }
  1405. { one }
  1406. const
  1407. macosLinkageAreaSize = 24;
  1408. var regcounter: TRegister;
  1409. href : treference;
  1410. registerSaveAreaSize : longint;
  1411. begin
  1412. if (localsize mod 8) <> 0 then
  1413. internalerror(58991);
  1414. { CR and LR only have to be saved in case they are modified by the current }
  1415. { procedure, but currently this isn't checked, so save them always }
  1416. { following is the entry code as described in "Altivec Programming }
  1417. { Interface Manual", bar the saving of AltiVec registers }
  1418. a_reg_alloc(list,NR_STACK_POINTER_REG);
  1419. a_reg_alloc(list,NR_R0);
  1420. { save return address in callers frame}
  1421. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_LR));
  1422. { ... in caller's frame }
  1423. reference_reset_base(href,NR_STACK_POINTER_REG,8);
  1424. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  1425. a_reg_dealloc(list,NR_R0);
  1426. { save non-volatile registers in callers frame}
  1427. registerSaveAreaSize:= save_regs(list);
  1428. { save the CR if necessary in callers frame ( !!! always done currently ) }
  1429. a_reg_alloc(list,NR_R0);
  1430. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_CR));
  1431. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1432. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  1433. a_reg_dealloc(list,NR_R0);
  1434. (*
  1435. { save pointer to incoming arguments }
  1436. list.concat(taicpu.op_reg_reg_const(A_ORI,R_31,STACK_POINTER_REG,0));
  1437. *)
  1438. (*
  1439. a_reg_alloc(list,R_12);
  1440. { 0 or 8 based on SP alignment }
  1441. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,
  1442. R_12,STACK_POINTER_REG,0,28,28));
  1443. { add in stack length }
  1444. list.concat(taicpu.op_reg_reg_const(A_SUBFIC,R_12,R_12,
  1445. -localsize));
  1446. { establish new alignment }
  1447. list.concat(taicpu.op_reg_reg_reg(A_STWUX,STACK_POINTER_REG,STACK_POINTER_REG,R_12));
  1448. a_reg_dealloc(list,R_12);
  1449. *)
  1450. { allocate stack frame }
  1451. localsize:= align(localsize + macosLinkageAreaSize + registerSaveAreaSize, 16);
  1452. inc(localsize,tg.lasttemp);
  1453. localsize:=align(localsize,16);
  1454. //tppcprocinfo(current_procinfo).localsize:=localsize;
  1455. if (localsize <> 0) then
  1456. begin
  1457. if (localsize <= high(smallint)) then
  1458. begin
  1459. reference_reset_base(href,NR_STACK_POINTER_REG,-localsize);
  1460. a_load_store(list,A_STWU,NR_STACK_POINTER_REG,href);
  1461. end
  1462. else
  1463. begin
  1464. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1465. href.index := NR_R11;
  1466. a_reg_alloc(list,href.index);
  1467. a_load_const_reg(list,OS_S32,-localsize,href.index);
  1468. a_load_store(list,A_STWUX,NR_STACK_POINTER_REG,href);
  1469. a_reg_dealloc(list,href.index);
  1470. end;
  1471. end;
  1472. end;
  1473. procedure tcgppc.g_return_from_proc_mac(list : taasmoutput;parasize : aint);
  1474. (* NOT IN USE *)
  1475. var
  1476. href : treference;
  1477. begin
  1478. a_reg_alloc(list,NR_R0);
  1479. { restore stack pointer }
  1480. reference_reset_base(href,NR_STACK_POINTER_REG,LA_SP);
  1481. list.concat(taicpu.op_reg_ref(A_LWZ,NR_STACK_POINTER_REG,href));
  1482. (*
  1483. list.concat(taicpu.op_reg_reg_const(A_ORI,NR_STACK_POINTER_REG,R_31,0));
  1484. *)
  1485. { restore the CR if necessary from callers frame
  1486. ( !!! always done currently ) }
  1487. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1488. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1489. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_CR));
  1490. a_reg_dealloc(list,NR_R0);
  1491. (*
  1492. { restore return address from callers frame }
  1493. reference_reset_base(href,STACK_POINTER_REG,8);
  1494. list.concat(taicpu.op_reg_ref(A_LWZ,R_0,href));
  1495. *)
  1496. { restore non-volatile registers from callers frame }
  1497. restore_regs(list);
  1498. (*
  1499. { return to caller }
  1500. list.concat(taicpu.op_reg_reg(A_MTSPR,R_0,R_LR));
  1501. list.concat(taicpu.op_none(A_BLR));
  1502. *)
  1503. { restore return address from callers frame }
  1504. reference_reset_base(href,NR_STACK_POINTER_REG,8);
  1505. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1506. { return to caller }
  1507. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_LR));
  1508. list.concat(taicpu.op_none(A_BLR));
  1509. end;
  1510. procedure tcgppc.a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);
  1511. var
  1512. ref2, tmpref: treference;
  1513. tmpreg:Tregister;
  1514. begin
  1515. ref2 := ref;
  1516. fixref(list,ref2);
  1517. if assigned(ref2.symbol) then
  1518. begin
  1519. if target_info.system = system_powerpc_macos then
  1520. begin
  1521. if macos_direct_globals then
  1522. begin
  1523. reference_reset(tmpref);
  1524. tmpref.offset := ref2.offset;
  1525. tmpref.symbol := ref2.symbol;
  1526. tmpref.base := NR_NO;
  1527. list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,NR_RTOC,tmpref));
  1528. end
  1529. else
  1530. begin
  1531. reference_reset(tmpref);
  1532. tmpref.symbol := ref2.symbol;
  1533. tmpref.offset := 0;
  1534. tmpref.base := NR_RTOC;
  1535. list.concat(taicpu.op_reg_ref(A_LWZ,r,tmpref));
  1536. if ref2.offset <> 0 then
  1537. begin
  1538. reference_reset(tmpref);
  1539. tmpref.offset := ref2.offset;
  1540. tmpref.base:= r;
  1541. list.concat(taicpu.op_reg_ref(A_LA,r,tmpref));
  1542. end;
  1543. end;
  1544. if ref2.base <> NR_NO then
  1545. list.concat(taicpu.op_reg_reg_reg(A_ADD,r,r,ref2.base));
  1546. //list.concat(tai_comment.create(strpnew('*** a_loadaddr_ref_reg')));
  1547. end
  1548. else
  1549. begin
  1550. { add the symbol's value to the base of the reference, and if the }
  1551. { reference doesn't have a base, create one }
  1552. reference_reset(tmpref);
  1553. tmpref.offset := ref2.offset;
  1554. tmpref.symbol := ref2.symbol;
  1555. tmpref.relsymbol := ref2.relsymbol;
  1556. tmpref.refaddr := addr_hi;
  1557. if ref2.base<> NR_NO then
  1558. begin
  1559. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,r,
  1560. ref2.base,tmpref));
  1561. end
  1562. else
  1563. list.concat(taicpu.op_reg_ref(A_LIS,r,tmpref));
  1564. tmpref.base := NR_NO;
  1565. tmpref.refaddr := addr_lo;
  1566. { can be folded with one of the next instructions by the }
  1567. { optimizer probably }
  1568. list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,r,tmpref));
  1569. end
  1570. end
  1571. else if ref2.offset <> 0 Then
  1572. if ref2.base <> NR_NO then
  1573. a_op_const_reg_reg(list,OP_ADD,OS_32,ref2.offset,ref2.base,r)
  1574. { FixRef makes sure that "(ref.index <> R_NO) and (ref.offset <> 0)" never}
  1575. { occurs, so now only ref.offset has to be loaded }
  1576. else
  1577. a_load_const_reg(list,OS_32,ref2.offset,r)
  1578. else if ref.index <> NR_NO Then
  1579. list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref2.base,ref2.index))
  1580. else if (ref2.base <> NR_NO) and
  1581. (r <> ref2.base) then
  1582. a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref2.base,r)
  1583. else
  1584. list.concat(taicpu.op_reg_const(A_LI,r,0));
  1585. end;
  1586. { ************* concatcopy ************ }
  1587. {$ifndef ppc603}
  1588. const
  1589. maxmoveunit = 8;
  1590. {$else ppc603}
  1591. const
  1592. maxmoveunit = 4;
  1593. {$endif ppc603}
  1594. procedure tcgppc.g_concatcopy(list : taasmoutput;const source,dest : treference;len : aint);
  1595. var
  1596. countreg: TRegister;
  1597. src, dst: TReference;
  1598. lab: tasmlabel;
  1599. count, count2: aint;
  1600. orgsrc, orgdst: boolean;
  1601. size: tcgsize;
  1602. begin
  1603. {$ifdef extdebug}
  1604. if len > high(longint) then
  1605. internalerror(2002072704);
  1606. {$endif extdebug}
  1607. { make sure short loads are handled as optimally as possible }
  1608. if (len <= maxmoveunit) and
  1609. (byte(len) in [1,2,4,8]) then
  1610. begin
  1611. if len < 8 then
  1612. begin
  1613. size := int_cgsize(len);
  1614. a_load_ref_ref(list,size,size,source,dest);
  1615. end
  1616. else
  1617. begin
  1618. a_reg_alloc(list,NR_F0);
  1619. a_loadfpu_ref_reg(list,OS_F64,source,NR_F0);
  1620. a_loadfpu_reg_ref(list,OS_F64,NR_F0,dest);
  1621. a_reg_dealloc(list,NR_F0);
  1622. end;
  1623. exit;
  1624. end;
  1625. count := len div maxmoveunit;
  1626. reference_reset(src);
  1627. reference_reset(dst);
  1628. { load the address of source into src.base }
  1629. if (count > 4) or
  1630. not issimpleref(source) or
  1631. ((source.index <> NR_NO) and
  1632. ((source.offset + longint(len)) > high(smallint))) then
  1633. begin
  1634. src.base := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1635. a_loadaddr_ref_reg(list,source,src.base);
  1636. orgsrc := false;
  1637. end
  1638. else
  1639. begin
  1640. src := source;
  1641. orgsrc := true;
  1642. end;
  1643. { load the address of dest into dst.base }
  1644. if (count > 4) or
  1645. not issimpleref(dest) or
  1646. ((dest.index <> NR_NO) and
  1647. ((dest.offset + longint(len)) > high(smallint))) then
  1648. begin
  1649. dst.base := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1650. a_loadaddr_ref_reg(list,dest,dst.base);
  1651. orgdst := false;
  1652. end
  1653. else
  1654. begin
  1655. dst := dest;
  1656. orgdst := true;
  1657. end;
  1658. {$ifndef ppc603}
  1659. if count > 4 then
  1660. { generate a loop }
  1661. begin
  1662. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1663. { have to be set to 8. I put an Inc there so debugging may be }
  1664. { easier (should offset be different from zero here, it will be }
  1665. { easy to notice in the generated assembler }
  1666. inc(dst.offset,8);
  1667. inc(src.offset,8);
  1668. list.concat(taicpu.op_reg_reg_const(A_SUBI,src.base,src.base,8));
  1669. list.concat(taicpu.op_reg_reg_const(A_SUBI,dst.base,dst.base,8));
  1670. countreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1671. a_load_const_reg(list,OS_32,count,countreg);
  1672. { explicitely allocate R_0 since it can be used safely here }
  1673. { (for holding date that's being copied) }
  1674. a_reg_alloc(list,NR_F0);
  1675. objectlibrary.getlabel(lab);
  1676. a_label(list, lab);
  1677. list.concat(taicpu.op_reg_reg_const(A_SUBIC_,countreg,countreg,1));
  1678. list.concat(taicpu.op_reg_ref(A_LFDU,NR_F0,src));
  1679. list.concat(taicpu.op_reg_ref(A_STFDU,NR_F0,dst));
  1680. a_jmp(list,A_BC,C_NE,0,lab);
  1681. a_reg_dealloc(list,NR_F0);
  1682. len := len mod 8;
  1683. end;
  1684. count := len div 8;
  1685. if count > 0 then
  1686. { unrolled loop }
  1687. begin
  1688. a_reg_alloc(list,NR_F0);
  1689. for count2 := 1 to count do
  1690. begin
  1691. a_loadfpu_ref_reg(list,OS_F64,src,NR_F0);
  1692. a_loadfpu_reg_ref(list,OS_F64,NR_F0,dst);
  1693. inc(src.offset,8);
  1694. inc(dst.offset,8);
  1695. end;
  1696. a_reg_dealloc(list,NR_F0);
  1697. len := len mod 8;
  1698. end;
  1699. if (len and 4) <> 0 then
  1700. begin
  1701. a_reg_alloc(list,NR_R0);
  1702. a_load_ref_reg(list,OS_32,OS_32,src,NR_R0);
  1703. a_load_reg_ref(list,OS_32,OS_32,NR_R0,dst);
  1704. inc(src.offset,4);
  1705. inc(dst.offset,4);
  1706. a_reg_dealloc(list,NR_R0);
  1707. end;
  1708. {$else not ppc603}
  1709. if count > 4 then
  1710. { generate a loop }
  1711. begin
  1712. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1713. { have to be set to 4. I put an Inc there so debugging may be }
  1714. { easier (should offset be different from zero here, it will be }
  1715. { easy to notice in the generated assembler }
  1716. inc(dst.offset,4);
  1717. inc(src.offset,4);
  1718. list.concat(taicpu.op_reg_reg_const(A_SUBI,src.base,src.base,4));
  1719. list.concat(taicpu.op_reg_reg_const(A_SUBI,dst.base,dst.base,4));
  1720. countreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1721. a_load_const_reg(list,OS_32,count,countreg);
  1722. { explicitely allocate R_0 since it can be used safely here }
  1723. { (for holding date that's being copied) }
  1724. a_reg_alloc(list,NR_R0);
  1725. objectlibrary.getlabel(lab);
  1726. a_label(list, lab);
  1727. list.concat(taicpu.op_reg_reg_const(A_SUBIC_,countreg,countreg,1));
  1728. list.concat(taicpu.op_reg_ref(A_LWZU,NR_R0,src));
  1729. list.concat(taicpu.op_reg_ref(A_STWU,NR_R0,dst));
  1730. a_jmp(list,A_BC,C_NE,0,lab);
  1731. a_reg_dealloc(list,NR_R0);
  1732. len := len mod 4;
  1733. end;
  1734. count := len div 4;
  1735. if count > 0 then
  1736. { unrolled loop }
  1737. begin
  1738. a_reg_alloc(list,NR_R0);
  1739. for count2 := 1 to count do
  1740. begin
  1741. a_load_ref_reg(list,OS_32,OS_32,src,NR_R0);
  1742. a_load_reg_ref(list,OS_32,OS_32,NR_R0,dst);
  1743. inc(src.offset,4);
  1744. inc(dst.offset,4);
  1745. end;
  1746. a_reg_dealloc(list,NR_R0);
  1747. len := len mod 4;
  1748. end;
  1749. {$endif not ppc603}
  1750. { copy the leftovers }
  1751. if (len and 2) <> 0 then
  1752. begin
  1753. a_reg_alloc(list,NR_R0);
  1754. a_load_ref_reg(list,OS_16,OS_16,src,NR_R0);
  1755. a_load_reg_ref(list,OS_16,OS_16,NR_R0,dst);
  1756. inc(src.offset,2);
  1757. inc(dst.offset,2);
  1758. a_reg_dealloc(list,NR_R0);
  1759. end;
  1760. if (len and 1) <> 0 then
  1761. begin
  1762. a_reg_alloc(list,NR_R0);
  1763. a_load_ref_reg(list,OS_8,OS_8,src,NR_R0);
  1764. a_load_reg_ref(list,OS_8,OS_8,NR_R0,dst);
  1765. a_reg_dealloc(list,NR_R0);
  1766. end;
  1767. end;
  1768. procedure tcgppc.g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef);
  1769. var
  1770. hl : tasmlabel;
  1771. begin
  1772. if not(cs_check_overflow in aktlocalswitches) then
  1773. exit;
  1774. objectlibrary.getlabel(hl);
  1775. if not ((def.deftype=pointerdef) or
  1776. ((def.deftype=orddef) and
  1777. (torddef(def).typ in [u64bit,u16bit,u32bit,u8bit,uchar,
  1778. bool8bit,bool16bit,bool32bit]))) then
  1779. begin
  1780. list.concat(taicpu.op_reg(A_MCRXR,NR_CR7));
  1781. a_jmp(list,A_BC,C_NO,7,hl)
  1782. end
  1783. else
  1784. a_jmp_cond(list,OC_AE,hl);
  1785. a_call_name(list,'FPC_OVERFLOW');
  1786. a_label(list,hl);
  1787. end;
  1788. {***************** This is private property, keep out! :) *****************}
  1789. function tcgppc.issimpleref(const ref: treference): boolean;
  1790. begin
  1791. if (ref.base = NR_NO) and
  1792. (ref.index <> NR_NO) then
  1793. internalerror(200208101);
  1794. result :=
  1795. not(assigned(ref.symbol)) and
  1796. (((ref.index = NR_NO) and
  1797. (ref.offset >= low(smallint)) and
  1798. (ref.offset <= high(smallint))) or
  1799. ((ref.index <> NR_NO) and
  1800. (ref.offset = 0)));
  1801. end;
  1802. function tcgppc.fixref(list: taasmoutput; var ref: treference): boolean;
  1803. var
  1804. tmpreg: tregister;
  1805. orgindex: tregister;
  1806. begin
  1807. result := false;
  1808. if (ref.base = NR_NO) then
  1809. begin
  1810. ref.base := ref.index;
  1811. ref.base := NR_NO;
  1812. end;
  1813. if (ref.base <> NR_NO) then
  1814. begin
  1815. if (ref.index <> NR_NO) and
  1816. ((ref.offset <> 0) or assigned(ref.symbol)) then
  1817. begin
  1818. result := true;
  1819. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1820. list.concat(taicpu.op_reg_reg_reg(
  1821. A_ADD,tmpreg,ref.base,ref.index));
  1822. ref.index := NR_NO;
  1823. ref.base := tmpreg;
  1824. end
  1825. end
  1826. else
  1827. if ref.index <> NR_NO then
  1828. internalerror(200208102);
  1829. end;
  1830. { find out whether a is of the form 11..00..11b or 00..11...00. If }
  1831. { that's the case, we can use rlwinm to do an AND operation }
  1832. function tcgppc.get_rlwi_const(a: aint; var l1, l2: longint): boolean;
  1833. var
  1834. temp : longint;
  1835. testbit : aint;
  1836. compare: boolean;
  1837. begin
  1838. get_rlwi_const := false;
  1839. if (a = 0) or (a = -1) then
  1840. exit;
  1841. { start with the lowest bit }
  1842. testbit := 1;
  1843. { check its value }
  1844. compare := boolean(a and testbit);
  1845. { find out how long the run of bits with this value is }
  1846. { (it's impossible that all bits are 1 or 0, because in that case }
  1847. { this function wouldn't have been called) }
  1848. l1 := 31;
  1849. while (((a and testbit) <> 0) = compare) do
  1850. begin
  1851. testbit := testbit shl 1;
  1852. dec(l1);
  1853. end;
  1854. { check the length of the run of bits that comes next }
  1855. compare := not compare;
  1856. l2 := l1;
  1857. while (((a and testbit) <> 0) = compare) and
  1858. (l2 >= 0) do
  1859. begin
  1860. testbit := testbit shl 1;
  1861. dec(l2);
  1862. end;
  1863. { and finally the check whether the rest of the bits all have the }
  1864. { same value }
  1865. compare := not compare;
  1866. temp := l2;
  1867. if temp >= 0 then
  1868. if (a shr (31-temp)) <> ((-ord(compare)) shr (31-temp)) then
  1869. exit;
  1870. { we have done "not(not(compare))", so compare is back to its }
  1871. { initial value. If the lowest bit was 0, a is of the form }
  1872. { 00..11..00 and we need "rlwinm reg,reg,0,l2+1,l1", (+1 }
  1873. { because l2 now contains the position of the last zero of the }
  1874. { first run instead of that of the first 1) so switch l1 and l2 }
  1875. { in that case (we will generate "rlwinm reg,reg,0,l1,l2") }
  1876. if not compare then
  1877. begin
  1878. temp := l1;
  1879. l1 := l2+1;
  1880. l2 := temp;
  1881. end
  1882. else
  1883. { otherwise, l1 currently contains the position of the last }
  1884. { zero instead of that of the first 1 of the second run -> +1 }
  1885. inc(l1);
  1886. { the following is the same as "if l1 = -1 then l1 := 31;" }
  1887. l1 := l1 and 31;
  1888. l2 := l2 and 31;
  1889. get_rlwi_const := true;
  1890. end;
  1891. procedure tcgppc.a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
  1892. ref: treference);
  1893. var
  1894. tmpreg: tregister;
  1895. tmpref: treference;
  1896. largeOffset: Boolean;
  1897. begin
  1898. tmpreg := NR_NO;
  1899. if target_info.system = system_powerpc_macos then
  1900. begin
  1901. largeOffset:= (cardinal(ref.offset-low(smallint)) >
  1902. high(smallint)-low(smallint));
  1903. if assigned(ref.symbol) then
  1904. begin {Load symbol's value}
  1905. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1906. reference_reset(tmpref);
  1907. tmpref.symbol := ref.symbol;
  1908. tmpref.base := NR_RTOC;
  1909. if macos_direct_globals then
  1910. list.concat(taicpu.op_reg_ref(A_LA,tmpreg,tmpref))
  1911. else
  1912. list.concat(taicpu.op_reg_ref(A_LWZ,tmpreg,tmpref));
  1913. end;
  1914. if largeOffset then
  1915. begin {Add hi part of offset}
  1916. reference_reset(tmpref);
  1917. if Smallint(Lo(ref.offset)) < 0 then
  1918. tmpref.offset := Hi(ref.offset) + 1 {Compensate when lo part is negative}
  1919. else
  1920. tmpref.offset := Hi(ref.offset);
  1921. if (tmpreg <> NR_NO) then
  1922. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,tmpreg, tmpreg,tmpref))
  1923. else
  1924. begin
  1925. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1926. list.concat(taicpu.op_reg_ref(A_LIS,tmpreg,tmpref));
  1927. end;
  1928. end;
  1929. if (tmpreg <> NR_NO) then
  1930. begin
  1931. {Add content of base register}
  1932. if ref.base <> NR_NO then
  1933. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,
  1934. ref.base,tmpreg));
  1935. {Make ref ready to be used by op}
  1936. ref.symbol:= nil;
  1937. ref.base:= tmpreg;
  1938. if largeOffset then
  1939. ref.offset := Smallint(Lo(ref.offset));
  1940. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1941. //list.concat(tai_comment.create(strpnew('*** a_load_store indirect global')));
  1942. end
  1943. else
  1944. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1945. end
  1946. else {if target_info.system <> system_powerpc_macos}
  1947. begin
  1948. if assigned(ref.symbol) or
  1949. (cardinal(ref.offset-low(smallint)) >
  1950. high(smallint)-low(smallint)) then
  1951. begin
  1952. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1953. reference_reset(tmpref);
  1954. tmpref.symbol := ref.symbol;
  1955. tmpref.relsymbol := ref.relsymbol;
  1956. tmpref.offset := ref.offset;
  1957. tmpref.refaddr := addr_hi;
  1958. if ref.base <> NR_NO then
  1959. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,tmpreg,
  1960. ref.base,tmpref))
  1961. else
  1962. list.concat(taicpu.op_reg_ref(A_LIS,tmpreg,tmpref));
  1963. ref.base := tmpreg;
  1964. ref.refaddr := addr_lo;
  1965. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1966. end
  1967. else
  1968. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1969. end;
  1970. end;
  1971. procedure tcgppc.a_jmp(list: taasmoutput; op: tasmop; c: tasmcondflag;
  1972. crval: longint; l: tasmlabel);
  1973. var
  1974. p: taicpu;
  1975. begin
  1976. p := taicpu.op_sym(op,objectlibrary.newasmsymbol(l.name,AB_EXTERNAL,AT_FUNCTION));
  1977. if op <> A_B then
  1978. create_cond_norm(c,crval,p.condition);
  1979. p.is_jmp := true;
  1980. list.concat(p)
  1981. end;
  1982. procedure tcg64fppc.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
  1983. begin
  1984. a_op64_reg_reg_reg(list,op,regsrc,regdst,regdst);
  1985. end;
  1986. procedure tcg64fppc.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : int64;reg : tregister64);
  1987. begin
  1988. a_op64_const_reg_reg(list,op,value,reg,reg);
  1989. end;
  1990. procedure tcg64fppc.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);
  1991. begin
  1992. case op of
  1993. OP_AND,OP_OR,OP_XOR:
  1994. begin
  1995. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
  1996. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
  1997. end;
  1998. OP_ADD:
  1999. begin
  2000. list.concat(taicpu.op_reg_reg_reg(A_ADDC,regdst.reglo,regsrc1.reglo,regsrc2.reglo));
  2001. list.concat(taicpu.op_reg_reg_reg(A_ADDE,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  2002. end;
  2003. OP_SUB:
  2004. begin
  2005. list.concat(taicpu.op_reg_reg_reg(A_SUBC,regdst.reglo,regsrc2.reglo,regsrc1.reglo));
  2006. list.concat(taicpu.op_reg_reg_reg(A_SUBFE,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  2007. end;
  2008. else
  2009. internalerror(2002072801);
  2010. end;
  2011. end;
  2012. procedure tcg64fppc.a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : int64;regsrc,regdst : tregister64);
  2013. const
  2014. ops: array[boolean,1..3] of tasmop = ((A_ADDIC,A_ADDC,A_ADDZE),
  2015. (A_SUBIC,A_SUBC,A_ADDME));
  2016. var
  2017. tmpreg: tregister;
  2018. tmpreg64: tregister64;
  2019. issub: boolean;
  2020. begin
  2021. case op of
  2022. OP_AND,OP_OR,OP_XOR:
  2023. begin
  2024. cg.a_op_const_reg_reg(list,op,OS_32,aint(value),regsrc.reglo,regdst.reglo);
  2025. cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
  2026. regdst.reghi);
  2027. end;
  2028. OP_ADD, OP_SUB:
  2029. begin
  2030. if (value < 0) then
  2031. begin
  2032. if op = OP_ADD then
  2033. op := OP_SUB
  2034. else
  2035. op := OP_ADD;
  2036. value := -value;
  2037. end;
  2038. if (longint(value) <> 0) then
  2039. begin
  2040. issub := op = OP_SUB;
  2041. if (value > 0) and
  2042. (value-ord(issub) <= 32767) then
  2043. begin
  2044. list.concat(taicpu.op_reg_reg_const(ops[issub,1],
  2045. regdst.reglo,regsrc.reglo,longint(value)));
  2046. list.concat(taicpu.op_reg_reg(ops[issub,3],
  2047. regdst.reghi,regsrc.reghi));
  2048. end
  2049. else if ((value shr 32) = 0) then
  2050. begin
  2051. tmpreg := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2052. cg.a_load_const_reg(list,OS_32,cardinal(value),tmpreg);
  2053. list.concat(taicpu.op_reg_reg_reg(ops[issub,2],
  2054. regdst.reglo,regsrc.reglo,tmpreg));
  2055. list.concat(taicpu.op_reg_reg(ops[issub,3],
  2056. regdst.reghi,regsrc.reghi));
  2057. end
  2058. else
  2059. begin
  2060. tmpreg64.reglo := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2061. tmpreg64.reghi := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2062. a_load64_const_reg(list,value,tmpreg64);
  2063. a_op64_reg_reg_reg(list,op,tmpreg64,regsrc,regdst);
  2064. end
  2065. end
  2066. else
  2067. begin
  2068. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reglo,regdst.reglo);
  2069. cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
  2070. regdst.reghi);
  2071. end;
  2072. end;
  2073. else
  2074. internalerror(2002072802);
  2075. end;
  2076. end;
  2077. begin
  2078. cg := tcgppc.create;
  2079. cg64 :=tcg64fppc.create;
  2080. end.
  2081. {
  2082. $Log$
  2083. Revision 1.182 2004-10-24 20:01:08 peter
  2084. * remove saveregister calling convention
  2085. Revision 1.181 2004/10/24 11:53:45 peter
  2086. * fixed compilation with removed loadref
  2087. Revision 1.180 2004/10/20 07:32:42 jonas
  2088. + support for nostackframe directive
  2089. Revision 1.179 2004/10/11 07:13:14 jonas
  2090. * include pi_do_call if we generate a call instead of internalerroring
  2091. (workaround)
  2092. Revision 1.178 2004/09/25 14:23:54 peter
  2093. * ungetregister is now only used for cpuregisters, renamed to
  2094. ungetcpuregister
  2095. * renamed (get|unget)explicitregister(s) to ..cpuregister
  2096. * removed location-release/reference_release
  2097. Revision 1.177 2004/09/21 17:25:12 peter
  2098. * paraloc branch merged
  2099. Revision 1.176.4.2 2004/09/18 20:21:08 jonas
  2100. * fixed ppc, but still needs fix in tgobj
  2101. Revision 1.176.4.1 2004/09/10 11:10:08 florian
  2102. * first part of ppc fixes
  2103. Revision 1.176 2004/07/17 14:48:20 jonas
  2104. * fixed op_const_reg_reg for (OP_ADD,0,reg1,reg2)
  2105. Revision 1.175 2004/07/09 21:45:24 jonas
  2106. * fixed passing of fpu paras on the stack
  2107. * fixed number of fpu parameters passed in registers
  2108. * skip corresponding integer registers when using an fpu register for a
  2109. parameter under the AIX abi
  2110. Revision 1.174 2004/07/01 18:00:00 jonas
  2111. * fixed several errors due to aword -> aint change
  2112. Revision 1.173 2004/06/20 08:55:32 florian
  2113. * logs truncated
  2114. Revision 1.172 2004/06/17 16:55:46 peter
  2115. * powerpc compiles again
  2116. Revision 1.171 2004/06/02 17:18:10 jonas
  2117. * parameters passed on the stack now also work as register variables
  2118. Revision 1.170 2004/05/31 18:08:41 jonas
  2119. * changed calling of external procedures to be the same as under gcc
  2120. (don't worry about all the generated stubs, they're optimized away
  2121. by the linker)
  2122. -> side effect: no need anymore to use special declarations for
  2123. external C functions under Darwin compared to other platforms
  2124. (it's still necessary for variables though)
  2125. Revision 1.169 2004/04/04 17:50:36 olle
  2126. * macos: fixed large offsets in references
  2127. Revision 1.168 2004/03/06 21:37:45 florian
  2128. * fixed ppc compilation
  2129. }