popt386.pas 86 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1993-98 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. Interface
  20. Uses Aasm;
  21. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  22. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  23. Implementation
  24. Uses
  25. globtype,systems,
  26. globals,verbose,hcodegen,
  27. cpubase,cpuasm,DAOpt386;
  28. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  29. Begin
  30. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  31. RegUsedAfterInstruction := Reg in UsedRegs
  32. End;
  33. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  34. {First pass of peepholeoptimizations}
  35. Var
  36. l : longint;
  37. p ,hp1, hp2 : pai;
  38. {$ifdef foropt}
  39. hp3, hp4: pai;
  40. {$endif foropt}
  41. TmpBool1, TmpBool2: Boolean;
  42. TmpRef: PReference;
  43. UsedRegs, TmpUsedRegs: TRegSet;
  44. Procedure GetFinalDestination(hp: paicpu);
  45. {traces sucessive jumps to their final destination and sets it, e.g.
  46. je l1 je l3
  47. <code> <code>
  48. l1: becomes l1:
  49. je l2 je l3
  50. <code> <code>
  51. l2: l2:
  52. jmp l3 jmp l3}
  53. Var p1: pai;
  54. Function SkipLabels(hp: Pai): Pai;
  55. {skips all labels and returns the next "real" instruction; it is
  56. assumed that hp is of the type ait_label}
  57. Begin
  58. While assigned(hp^.next) and
  59. (pai(hp^.next)^.typ In SkipInstr + [ait_label]) Do
  60. hp := pai(hp^.next);
  61. If assigned(hp^.next)
  62. Then SkipLabels := pai(hp^.next)
  63. Else SkipLabels := hp;
  64. End;
  65. Begin
  66. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  67. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  68. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  69. Begin
  70. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  71. p1 := SkipLabels(p1);
  72. If (pai(p1)^.typ = ait_instruction) and
  73. (paicpu(p1)^.is_jmp) and
  74. (paicpu(p1)^.condition = hp^.condition) Then
  75. Begin
  76. GetFinalDestination(paicpu(p1));
  77. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  78. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  79. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  80. End;
  81. End;
  82. End;
  83. Function DoSubAddOpt(var p: Pai): Boolean;
  84. Begin
  85. DoSubAddOpt := False;
  86. If GetLastInstruction(p, hp1) And
  87. (hp1^.typ = ait_instruction) And
  88. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  89. Case Paicpu(hp1)^.opcode Of
  90. A_DEC:
  91. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  92. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  93. Begin
  94. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  95. AsmL^.Remove(hp1);
  96. Dispose(hp1, Done)
  97. End;
  98. A_SUB:
  99. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  100. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  101. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  102. Begin
  103. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  104. AsmL^.Remove(hp1);
  105. Dispose(hp1, Done)
  106. End;
  107. A_ADD:
  108. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  109. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  110. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  111. Begin
  112. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  113. AsmL^.Remove(hp1);
  114. Dispose(hp1, Done);
  115. If (Paicpu(p)^.oper[0].val = 0) Then
  116. Begin
  117. hp1 := Pai(p^.next);
  118. AsmL^.Remove(p);
  119. Dispose(p, Done);
  120. If Not GetLastInstruction(hp1, p) Then
  121. p := hp1;
  122. DoSubAddOpt := True;
  123. End
  124. End;
  125. End;
  126. End;
  127. Begin
  128. P := BlockStart;
  129. UsedRegs := [];
  130. While (P <> BlockEnd) Do
  131. Begin
  132. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  133. Case P^.Typ Of
  134. ait_instruction:
  135. Begin
  136. { Handle Jmp Optimizations }
  137. if Paicpu(p)^.is_jmp then
  138. begin
  139. {the following if-block removes all code between a jmp and the next label,
  140. because it can never be executed}
  141. If (paicpu(p)^.opcode = A_JMP) Then
  142. Begin
  143. While GetNextInstruction(p, hp1) and
  144. ((hp1^.typ <> ait_label) or
  145. { skip unused labels, they're not referenced anywhere }
  146. Not(Pai_Label(hp1)^.l^.is_used)) Do
  147. If (hp1^.typ <> ait_label) Then
  148. Begin
  149. AsmL^.Remove(hp1);
  150. Dispose(hp1, done);
  151. End;
  152. End;
  153. If GetNextInstruction(p, hp1) then
  154. Begin
  155. If (pai(hp1)^.typ=ait_instruction) and
  156. (paicpu(hp1)^.opcode=A_JMP) and
  157. GetNextInstruction(hp1, hp2) And
  158. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  159. Then
  160. Begin
  161. if paicpu(p)^.opcode=A_Jcc then
  162. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  163. else
  164. begin
  165. If (LabDif <> 0) Then
  166. GetFinalDestination(paicpu(p));
  167. p:=pai(p^.next);
  168. continue;
  169. end;
  170. Dec(pai_label(hp2)^.l^.refs);
  171. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  172. Inc(paicpu(p)^.oper[0].sym^.refs);
  173. asml^.remove(hp1);
  174. dispose(hp1,done);
  175. If (LabDif <> 0) Then
  176. GetFinalDestination(paicpu(p));
  177. end
  178. else
  179. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  180. Begin
  181. hp2:=pai(hp1^.next);
  182. asml^.remove(p);
  183. dispose(p,done);
  184. p:=hp2;
  185. continue;
  186. end
  187. Else
  188. If (LabDif <> 0) Then
  189. GetFinalDestination(paicpu(p));
  190. end
  191. end
  192. else
  193. { All other optimizes }
  194. begin
  195. For l := 0 to 2 Do
  196. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  197. With Paicpu(p)^.oper[l].ref^ Do
  198. Begin
  199. If (base = R_NO) And
  200. (index <> R_NO) And
  201. (scalefactor in [0,1])
  202. Then
  203. Begin
  204. base := index;
  205. index := R_NO
  206. End
  207. End;
  208. Case Paicpu(p)^.opcode Of
  209. A_AND:
  210. Begin
  211. If (Paicpu(p)^.oper[0].typ = top_const) And
  212. (Paicpu(p)^.oper[1].typ = top_reg) And
  213. GetNextInstruction(p, hp1) And
  214. (Pai(hp1)^.typ = ait_instruction) And
  215. (Paicpu(hp1)^.opcode = A_AND) And
  216. (Paicpu(hp1)^.oper[0].typ = top_const) And
  217. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  218. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  219. Then
  220. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  221. Begin
  222. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  223. AsmL^.Remove(hp1);
  224. Dispose(hp1, Done)
  225. End
  226. Else
  227. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  228. jump}
  229. If (Paicpu(p)^.oper[1].typ = top_reg) And
  230. GetNextInstruction(p, hp1) And
  231. (hp1^.typ = ait_instruction) And
  232. (Paicpu(hp1)^.is_jmp) and
  233. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  234. Paicpu(p)^.opcode := A_TEST;
  235. End;
  236. A_CMP:
  237. Begin
  238. If (Paicpu(p)^.oper[0].typ = top_const) And
  239. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  240. (Paicpu(p)^.oper[0].val = 0) Then
  241. {$ifdef foropt}
  242. If GetNextInstruction(p, hp1) And
  243. (hp1^.typ = ait_instruction) And
  244. (Paicpu(hp1)^.is_jmp) and
  245. (paicpu(hp1)^.opcode=A_Jcc) and
  246. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  247. GetNextInstruction(hp1,hp2) and
  248. (hp2^.typ = ait_instruction) and
  249. (Paicpu(hp2)^.opcode = A_DEC) And
  250. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  251. GetNextInstruction(hp2, hp3) And
  252. (hp3^.typ = ait_instruction) and
  253. (Paicpu(hp3)^.is_jmp) and
  254. (Paicpu(hp3)^.opcode = A_JMP) And
  255. GetNextInstruction(hp3, hp4) And
  256. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  257. Then
  258. Begin
  259. Paicpu(hp2)^.Opcode := A_SUB;
  260. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  261. Paicpu(hp2)^.LoadConst(0,1);
  262. Paicpu(hp2)^.ops:=2;
  263. Paicpu(hp3)^.Opcode := A_Jcc;
  264. Case paicpu(hp1)^.condition of
  265. C_LE: Paicpu(hp3)^.condition := C_GE;
  266. C_BE: Paicpu(hp3)^.condition := C_AE;
  267. End;
  268. AsmL^.Remove(p);
  269. AsmL^.Remove(hp1);
  270. Dispose(p, Done);
  271. Dispose(hp1, Done);
  272. p := hp2;
  273. continue;
  274. End
  275. Else
  276. {$endif foropt}
  277. {change "cmp $0, %reg" to "test %reg, %reg"}
  278. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  279. Begin
  280. Paicpu(p)^.opcode := A_TEST;
  281. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  282. End;
  283. End;
  284. A_FLD:
  285. Begin
  286. If (Paicpu(p)^.oper[0].typ = top_ref) And
  287. GetNextInstruction(p, hp2) And
  288. (hp2^.typ = Ait_Instruction) And
  289. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  290. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  291. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  292. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  293. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  294. If GetLastInstruction(p, hp1) And
  295. (hp1^.typ = Ait_Instruction) And
  296. ((Paicpu(hp1)^.opcode = A_FLD) Or
  297. (Paicpu(hp1)^.opcode = A_FST)) And
  298. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  299. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  300. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  301. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  302. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  303. { change to
  304. fld/fst mem1 (hp1) fld/fst mem1
  305. fld mem1 (p) fadd/
  306. faddp/ fmul st, st
  307. fmulp st, st1 (hp2) }
  308. Begin
  309. AsmL^.Remove(p);
  310. Dispose(p, Done);
  311. p := hp1;
  312. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  313. Paicpu(hp2)^.opcode := A_FADD
  314. Else
  315. Paicpu(hp2)^.opcode := A_FMUL;
  316. Paicpu(hp2)^.oper[1].reg := R_ST;
  317. End
  318. Else
  319. { change to
  320. fld/fst mem1 (hp1) fld/fst mem1
  321. fld mem1 (p) fld st}
  322. Begin
  323. Paicpu(p)^.changeopsize(S_FL);
  324. Paicpu(p)^.loadreg(0,R_ST);
  325. End
  326. Else
  327. Begin
  328. Case Paicpu(hp2)^.opcode Of
  329. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  330. { change to
  331. fld/fst mem1 (hp1) fld/fst mem1
  332. fld mem2 (p) fxxx mem2
  333. fxxxp st, st1 (hp2) }
  334. Begin
  335. Case Paicpu(hp2)^.opcode Of
  336. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  337. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  338. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  339. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  340. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  341. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  342. End;
  343. AsmL^.Remove(hp2);
  344. Dispose(hp2, Done)
  345. End
  346. End
  347. End
  348. End;
  349. A_FSTP,A_FISTP:
  350. Begin
  351. If (Paicpu(p)^.oper[0].typ = top_ref) And
  352. GetNextInstruction(p, hp1) And
  353. (Pai(hp1)^.typ = ait_instruction) And
  354. (((Paicpu(hp1)^.opcode = A_FLD) And
  355. (Paicpu(p)^.opcode = A_FSTP)) Or
  356. ((Paicpu(p)^.opcode = A_FISTP) And
  357. (Paicpu(hp1)^.opcode = A_FILD))) And
  358. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  359. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  360. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  361. Then
  362. Begin
  363. If GetNextInstruction(hp1, hp2) And
  364. (hp2^.typ = ait_instruction) And
  365. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  366. (Paicpu(hp2)^.opcode = A_RET)) And
  367. (Paicpu(p)^.oper[0].ref^.Base = ProcInfo.FramePointer) And
  368. (Paicpu(p)^.oper[0].ref^.Offset >= ProcInfo.RetOffset) And
  369. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  370. Then
  371. Begin
  372. AsmL^.Remove(p);
  373. AsmL^.Remove(hp1);
  374. Dispose(p, Done);
  375. Dispose(hp1, Done);
  376. p := hp2;
  377. Continue
  378. End
  379. Else
  380. {fst can't store an extended value!}
  381. If (Paicpu(p)^.opsize <> S_FX) And
  382. (Paicpu(p)^.opsize <> S_IQ) Then
  383. Begin
  384. If (Paicpu(p)^.opcode = A_FSTP) Then
  385. Paicpu(p)^.opcode := A_FST
  386. Else Paicpu(p)^.opcode := A_FIST;
  387. AsmL^.Remove(hp1);
  388. Dispose(hp1, done)
  389. End
  390. End;
  391. End;
  392. A_IMUL:
  393. {changes certain "imul const, %reg"'s to lea sequences}
  394. Begin
  395. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  396. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  397. (Paicpu(p)^.opsize = S_L) Then
  398. If (Paicpu(p)^.oper[0].val = 1) Then
  399. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  400. {remove "imul $1, reg"}
  401. Begin
  402. hp1 := Pai(p^.Next);
  403. AsmL^.Remove(p);
  404. Dispose(p, Done);
  405. p := hp1;
  406. Continue;
  407. End
  408. Else
  409. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  410. Begin
  411. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  412. hp1^.fileinfo := p^.fileinfo;
  413. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  414. Dispose(p, Done);
  415. p := hp1;
  416. End
  417. Else If
  418. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  419. (Paicpu(p)^.oper[2].typ = Top_None)) And
  420. (aktoptprocessor < ClassP6) And
  421. (Paicpu(p)^.oper[0].val <= 12) And
  422. Not(CS_LittleSize in aktglobalswitches) And
  423. (Not(GetNextInstruction(p, hp1)) Or
  424. {GetNextInstruction(p, hp1) And}
  425. Not((Pai(hp1)^.typ = ait_instruction) And
  426. ((paicpu(hp1)^.opcode=A_Jcc) and
  427. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  428. Then
  429. Begin
  430. New(TmpRef);
  431. Reset_reference(tmpref^);
  432. Case Paicpu(p)^.oper[0].val Of
  433. 3: Begin
  434. {imul 3, reg1, reg2 to
  435. lea (reg1,reg1,2), reg2
  436. imul 3, reg1 to
  437. lea (reg1,reg1,2), reg1}
  438. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  439. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  440. TmpRef^.ScaleFactor := 2;
  441. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  442. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  443. Else
  444. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  445. hp1^.fileinfo := p^.fileinfo;
  446. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  447. Dispose(p, Done);
  448. p := hp1;
  449. End;
  450. 5: Begin
  451. {imul 5, reg1, reg2 to
  452. lea (reg1,reg1,4), reg2
  453. imul 5, reg1 to
  454. lea (reg1,reg1,4), reg1}
  455. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  456. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  457. TmpRef^.ScaleFactor := 4;
  458. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  459. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  460. Else
  461. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  462. hp1^.fileinfo:= p^.fileinfo;
  463. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  464. Dispose(p, Done);
  465. p := hp1;
  466. End;
  467. 6: Begin
  468. {imul 6, reg1, reg2 to
  469. lea (,reg1,2), reg2
  470. lea (reg2,reg1,4), reg2
  471. imul 6, reg1 to
  472. lea (reg1,reg1,2), reg1
  473. add reg1, reg1}
  474. If (aktoptprocessor <= Class386)
  475. Then
  476. Begin
  477. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  478. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  479. Then
  480. Begin
  481. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  482. TmpRef^.ScaleFactor := 4;
  483. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  484. End
  485. Else
  486. Begin
  487. Dispose(TmpRef);
  488. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  489. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  490. End;
  491. hp1^.fileinfo := p^.fileinfo;
  492. InsertLLItem(AsmL,p, p^.next, hp1);
  493. New(TmpRef);
  494. Reset_reference(tmpref^);
  495. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  496. TmpRef^.ScaleFactor := 2;
  497. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  498. Then
  499. Begin
  500. TmpRef^.base := R_NO;
  501. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  502. Paicpu(p)^.oper[2].reg));
  503. End
  504. Else
  505. Begin
  506. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  507. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  508. End;
  509. hp1^.fileinfo := p^.fileinfo;
  510. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  511. Dispose(p, Done);
  512. p := Pai(hp1^.next);
  513. End
  514. Else Dispose(TmpRef);
  515. End;
  516. 9: Begin
  517. {imul 9, reg1, reg2 to
  518. lea (reg1,reg1,8), reg2
  519. imul 9, reg1 to
  520. lea (reg1,reg1,8), reg1}
  521. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  522. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  523. TmpRef^.ScaleFactor := 8;
  524. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  525. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  526. Else
  527. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  528. hp1^.fileinfo := p^.fileinfo;
  529. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  530. Dispose(p, Done);
  531. p := hp1;
  532. End;
  533. 10: Begin
  534. {imul 10, reg1, reg2 to
  535. lea (reg1,reg1,4), reg2
  536. add reg2, reg2
  537. imul 10, reg1 to
  538. lea (reg1,reg1,4), reg1
  539. add reg1, reg1}
  540. If (aktoptprocessor <= Class386) Then
  541. Begin
  542. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  543. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  544. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  545. Else
  546. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  547. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  548. hp1^.fileinfo := p^.fileinfo;
  549. InsertLLItem(AsmL,p, p^.next, hp1);
  550. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  551. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  552. TmpRef^.ScaleFactor := 4;
  553. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  554. Then
  555. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg))
  556. Else
  557. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  558. hp1^.fileinfo := p^.fileinfo;
  559. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  560. Dispose(p, Done);
  561. p := Pai(hp1^.next);
  562. End
  563. Else Dispose(TmpRef);
  564. End;
  565. 12: Begin
  566. {imul 12, reg1, reg2 to
  567. lea (,reg1,4), reg2
  568. lea (,reg1,8) reg2
  569. imul 12, reg1 to
  570. lea (reg1,reg1,2), reg1
  571. lea (,reg1,4), reg1}
  572. If (aktoptprocessor <= Class386)
  573. Then
  574. Begin
  575. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  576. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  577. Begin
  578. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  579. TmpRef^.ScaleFactor := 8;
  580. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  581. End
  582. Else
  583. Begin
  584. TmpRef^.base := R_NO;
  585. TmpRef^.ScaleFactor := 4;
  586. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  587. End;
  588. hp1^.fileinfo := p^.fileinfo;
  589. InsertLLItem(AsmL,p, p^.next, hp1);
  590. New(TmpRef);
  591. Reset_reference(tmpref^);
  592. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  593. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  594. Begin
  595. TmpRef^.base := R_NO;
  596. TmpRef^.ScaleFactor := 4;
  597. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  598. End
  599. Else
  600. Begin
  601. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  602. TmpRef^.ScaleFactor := 2;
  603. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  604. End;
  605. hp1^.fileinfo := p^.fileinfo;
  606. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  607. Dispose(p, Done);
  608. p := Pai(hp1^.next);
  609. End
  610. Else Dispose(TmpRef);
  611. End
  612. Else Dispose(TmpRef);
  613. End;
  614. End;
  615. End;
  616. A_LEA:
  617. Begin
  618. {removes seg register prefixes from LEA operations, as they
  619. don't do anything}
  620. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  621. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  622. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  623. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  624. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  625. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  626. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  627. Then
  628. Begin
  629. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  630. Paicpu(p)^.oper[1].reg));
  631. hp1^.fileinfo := p^.fileinfo;
  632. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  633. Dispose(p, Done);
  634. p := hp1;
  635. Continue;
  636. End
  637. Else
  638. Begin
  639. hp1 := Pai(p^.Next);
  640. AsmL^.Remove(p);
  641. Dispose(p, Done);
  642. p := hp1;
  643. Continue;
  644. End;
  645. End;
  646. A_MOV:
  647. Begin
  648. TmpUsedRegs := UsedRegs;
  649. If (Paicpu(p)^.oper[1].typ = top_reg) And
  650. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  651. GetNextInstruction(p, hp1) And
  652. (Pai(hp1)^.typ = ait_instruction) And
  653. (Paicpu(hp1)^.opcode = A_MOV) And
  654. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  655. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  656. Then
  657. {we have "mov x, %treg; mov %treg, y}
  658. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  659. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  660. Case Paicpu(p)^.oper[0].typ Of
  661. top_reg:
  662. Begin
  663. { change "mov %reg, %treg; mov %treg, y"
  664. to "mov %reg, y" }
  665. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  666. AsmL^.Remove(p);
  667. Dispose(p, Done);
  668. p := hp1;
  669. continue;
  670. End;
  671. top_ref:
  672. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  673. Begin
  674. { change "mov mem, %treg; mov %treg, %reg"
  675. to "mov mem, %reg" }
  676. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  677. AsmL^.Remove(hp1);
  678. Dispose(hp1, Done);
  679. continue;
  680. End;
  681. End
  682. Else
  683. {remove an instruction which never makes sense: we've got
  684. "mov mem, %reg1; mov %reg1, %edi" and then EDI isn't used anymore!}
  685. { Begin
  686. If (Paicpu(hp1)^.oper[1].reg = R_EDI) And
  687. Not(GetNextInstruction(hp1, hp2) And
  688. (Pai(hp2)^.typ = ait_instruction) And
  689. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  690. (Paicpu(hp2)^.oper[1] = Pointer(R_ESI))) Then
  691. Begin
  692. AsmL^.Remove(hp1);
  693. Dispose(hp1, Done);
  694. Continue;
  695. End
  696. End}
  697. Else
  698. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  699. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  700. penalty}
  701. If (Paicpu(p)^.oper[0].typ = top_reg) And
  702. (Paicpu(p)^.oper[1].typ = top_reg) And
  703. GetNextInstruction(p,hp1) And
  704. (Pai(hp1)^.typ = ait_instruction) And
  705. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  706. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  707. Then
  708. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  709. Begin
  710. If ((Paicpu(hp1)^.opcode = A_OR) Or
  711. (Paicpu(hp1)^.opcode = A_TEST)) And
  712. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  713. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  714. Then
  715. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  716. Begin
  717. TmpUsedRegs := UsedRegs;
  718. If GetNextInstruction(hp1, hp2) And
  719. (hp2^.typ = ait_instruction) And
  720. paicpu(hp2)^.is_jmp and
  721. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  722. Then
  723. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  724. "test %reg1, %reg1; jxx"}
  725. Begin
  726. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  727. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  728. AsmL^.Remove(p);
  729. Dispose(p, done);
  730. p := hp1;
  731. continue
  732. End
  733. Else
  734. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  735. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  736. Begin
  737. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  738. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  739. End;
  740. End
  741. { Else
  742. If (Paicpu(p^.next)^.opcode
  743. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  744. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  745. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  746. End
  747. Else
  748. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  749. x >= RetOffset) as it doesn't do anything (it writes either to a
  750. parameter or to the temporary storage room for the function
  751. result)}
  752. If GetNextInstruction(p, hp1) And
  753. (Pai(hp1)^.typ = ait_instruction)
  754. Then
  755. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  756. (Paicpu(hp1)^.opcode = A_RET)) And
  757. (Paicpu(p)^.oper[1].typ = top_ref) And
  758. (Paicpu(p)^.oper[1].ref^.base = ProcInfo.FramePointer) And
  759. (Paicpu(p)^.oper[1].ref^.offset >= ProcInfo.RetOffset) And
  760. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  761. (Paicpu(p)^.oper[0].typ = top_reg)
  762. Then
  763. Begin
  764. AsmL^.Remove(p);
  765. Dispose(p, done);
  766. p := hp1;
  767. End
  768. Else
  769. If (Paicpu(p)^.oper[0].typ = top_reg) And
  770. (Paicpu(p)^.oper[1].typ = top_ref) And
  771. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  772. (Paicpu(hp1)^.opcode = A_CMP) And
  773. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  774. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  775. Then
  776. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  777. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  778. { Next instruction is also a MOV ? }
  779. If GetNextInstruction(p, hp1) And
  780. (pai(hp1)^.typ = ait_instruction) and
  781. (Paicpu(hp1)^.opcode = A_MOV) and
  782. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  783. Then
  784. Begin
  785. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  786. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  787. Then
  788. {mov reg1, mem1 or mov mem1, reg1
  789. mov mem2, reg2 mov reg2, mem2}
  790. Begin
  791. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  792. {mov reg1, mem1 or mov mem1, reg1
  793. mov mem2, reg1 mov reg2, mem1}
  794. Begin
  795. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  796. { Removes the second statement from
  797. mov reg1, mem1
  798. mov mem1, reg1 }
  799. Begin
  800. AsmL^.remove(hp1);
  801. Dispose(hp1,done);
  802. End
  803. Else
  804. Begin
  805. TmpUsedRegs := UsedRegs;
  806. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  807. If (Paicpu(p)^.oper[0].typ = top_reg) And
  808. { mov reg1, mem1
  809. mov mem2, reg1 }
  810. GetNextInstruction(hp1, hp2) And
  811. (hp2^.typ = ait_instruction) And
  812. (Paicpu(hp2)^.opcode = A_CMP) And
  813. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  814. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  815. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  816. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  817. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  818. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  819. { change to
  820. mov reg1, mem1 mov reg1, mem1
  821. mov mem2, reg1 cmp reg1, mem2
  822. cmp mem1, reg1 }
  823. Begin
  824. AsmL^.Remove(hp2);
  825. Dispose(hp2, Done);
  826. Paicpu(hp1)^.opcode := A_CMP;
  827. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  828. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  829. End;
  830. End;
  831. End
  832. Else
  833. Begin
  834. If GetNextInstruction(hp1, hp2) And
  835. (Paicpu(p)^.oper[0].typ = top_ref) And
  836. (Paicpu(p)^.oper[1].typ = top_reg) And
  837. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  838. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  839. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  840. (Pai(hp2)^.typ = ait_instruction) And
  841. (Paicpu(hp2)^.opcode = A_MOV) And
  842. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  843. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  844. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  845. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^)
  846. Then
  847. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI])
  848. Then
  849. { mov mem1, %edi
  850. mov %edi, mem2
  851. mov mem2, reg2
  852. to:
  853. mov mem1, reg2
  854. mov reg2, mem2}
  855. Begin
  856. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  857. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  858. AsmL^.Remove(hp2);
  859. Dispose(hp2,Done);
  860. End
  861. Else
  862. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  863. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  864. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  865. Then
  866. { mov mem1, reg1 mov mem1, reg1
  867. mov reg1, mem2 mov reg1, mem2
  868. mov mem2, reg2 mov mem2, reg1
  869. to: to:
  870. mov mem1, reg1 mov mem1, reg1
  871. mov mem1, reg2 mov reg1, mem2
  872. mov reg1, mem2
  873. or (if mem1 depends on reg1
  874. and/or if mem2 depends on reg2)
  875. to:
  876. mov mem1, reg1
  877. mov reg1, mem2
  878. mov reg1, reg2
  879. }
  880. Begin
  881. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  882. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  883. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  884. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  885. End
  886. Else
  887. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  888. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  889. Else
  890. Begin
  891. AsmL^.Remove(hp2);
  892. Dispose(hp2, Done);
  893. End
  894. End;
  895. End
  896. Else
  897. (* {movl [mem1],reg1
  898. movl [mem1],reg2
  899. to:
  900. movl [mem1],reg1
  901. movl reg1,reg2 }
  902. If (Paicpu(p)^.oper[0].typ = top_ref) and
  903. (Paicpu(p)^.oper[1].typ = top_reg) and
  904. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  905. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  906. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  907. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  908. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  909. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  910. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  911. Else*)
  912. { movl const1,[mem1]
  913. movl [mem1],reg1
  914. to:
  915. movl const1,reg1
  916. movl reg1,[mem1] }
  917. If (Paicpu(p)^.oper[0].typ = top_const) and
  918. (Paicpu(p)^.oper[1].typ = top_ref) and
  919. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  920. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  921. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  922. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  923. Begin
  924. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  925. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  926. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  927. End
  928. End;
  929. {changes "mov $0, %reg" into "xor %reg, %reg"}
  930. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  931. (Paicpu(p)^.oper[0].val = 0) And
  932. (Paicpu(p)^.oper[1].typ = Top_Reg)
  933. Then
  934. Begin
  935. Paicpu(p)^.opcode := A_XOR;
  936. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  937. End;
  938. End;
  939. A_MOVZX:
  940. Begin
  941. {removes superfluous And's after movzx's}
  942. If (Paicpu(p)^.oper[1].typ = top_reg) And
  943. GetNextInstruction(p, hp1) And
  944. (Pai(hp1)^.typ = ait_instruction) And
  945. (Paicpu(hp1)^.opcode = A_AND) And
  946. (Paicpu(hp1)^.oper[0].typ = top_const) And
  947. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  948. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  949. Then
  950. Case Paicpu(p)^.opsize Of
  951. S_BL, S_BW:
  952. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  953. Begin
  954. AsmL^.Remove(hp1);
  955. Dispose(hp1, Done);
  956. End;
  957. S_WL:
  958. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  959. Begin
  960. AsmL^.Remove(hp1);
  961. Dispose(hp1, Done);
  962. End;
  963. End;
  964. {changes some movzx constructs to faster synonims (all examples
  965. are given with eax/ax, but are also valid for other registers)}
  966. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  967. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  968. Case Paicpu(p)^.opsize of
  969. S_BW:
  970. Begin
  971. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  972. Not(CS_LittleSize In aktglobalswitches)
  973. Then
  974. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  975. Begin
  976. Paicpu(p)^.opcode := A_AND;
  977. Paicpu(p)^.changeopsize(S_W);
  978. Paicpu(p)^.LoadConst(0,$ff);
  979. End
  980. Else
  981. If GetNextInstruction(p, hp1) And
  982. (Pai(hp1)^.typ = ait_instruction) And
  983. (Paicpu(hp1)^.opcode = A_AND) And
  984. (Paicpu(hp1)^.oper[0].typ = top_const) And
  985. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  986. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  987. Then
  988. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  989. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  990. Begin
  991. Paicpu(p)^.opcode := A_MOV;
  992. Paicpu(p)^.changeopsize(S_W);
  993. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  994. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  995. End;
  996. End;
  997. S_BL:
  998. Begin
  999. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1000. Not(CS_LittleSize in aktglobalswitches)
  1001. Then
  1002. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1003. Begin
  1004. Paicpu(p)^.opcode := A_AND;
  1005. Paicpu(p)^.changeopsize(S_L);
  1006. Paicpu(p)^.loadconst(0,$ff)
  1007. End
  1008. Else
  1009. If GetNextInstruction(p, hp1) And
  1010. (Pai(hp1)^.typ = ait_instruction) And
  1011. (Paicpu(hp1)^.opcode = A_AND) And
  1012. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1013. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1014. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1015. Then
  1016. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1017. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1018. Begin
  1019. Paicpu(p)^.opcode := A_MOV;
  1020. Paicpu(p)^.changeopsize(S_L);
  1021. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1022. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1023. End
  1024. End;
  1025. S_WL:
  1026. Begin
  1027. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1028. Not(CS_LittleSize In aktglobalswitches)
  1029. Then
  1030. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1031. Begin
  1032. Paicpu(p)^.opcode := A_AND;
  1033. Paicpu(p)^.changeopsize(S_L);
  1034. Paicpu(p)^.LoadConst(0,$ffff);
  1035. End
  1036. Else
  1037. If GetNextInstruction(p, hp1) And
  1038. (Pai(hp1)^.typ = ait_instruction) And
  1039. (Paicpu(hp1)^.opcode = A_AND) And
  1040. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1041. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1042. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1043. Then
  1044. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1045. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1046. Begin
  1047. Paicpu(p)^.opcode := A_MOV;
  1048. Paicpu(p)^.changeopsize(S_L);
  1049. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1050. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1051. End;
  1052. End;
  1053. End
  1054. Else
  1055. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1056. Begin
  1057. If GetNextInstruction(p, hp1) And
  1058. (Pai(hp1)^.typ = ait_instruction) And
  1059. (Paicpu(hp1)^.opcode = A_AND) And
  1060. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1061. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1062. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1063. Begin
  1064. Paicpu(p)^.opcode := A_MOV;
  1065. Case Paicpu(p)^.opsize Of
  1066. S_BL:
  1067. Begin
  1068. Paicpu(p)^.changeopsize(S_L);
  1069. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1070. End;
  1071. S_WL:
  1072. Begin
  1073. Paicpu(p)^.changeopsize(S_L);
  1074. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1075. End;
  1076. S_BW:
  1077. Begin
  1078. Paicpu(p)^.changeopsize(S_W);
  1079. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1080. End;
  1081. End;
  1082. End;
  1083. End;
  1084. End;
  1085. A_POP:
  1086. Begin
  1087. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1088. GetNextInstruction(p, hp1) And
  1089. (pai(hp1)^.typ=ait_instruction) and
  1090. (Paicpu(hp1)^.opcode=A_PUSH) and
  1091. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1092. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1093. { This can't be done, because the register which is popped
  1094. can still be used after the push (PFV)
  1095. If (Not(cs_regalloc in aktglobalswitches)) Then
  1096. Begin
  1097. hp2:=pai(hp1^.next);
  1098. asml^.remove(p);
  1099. asml^.remove(hp1);
  1100. dispose(p,done);
  1101. dispose(hp1,done);
  1102. p:=hp2;
  1103. continue
  1104. End
  1105. Else }
  1106. Begin
  1107. { change it to a two op operation }
  1108. Paicpu(p)^.oper[1].typ:=top_none;
  1109. Paicpu(p)^.ops:=2;
  1110. Paicpu(p)^.opcode := A_MOV;
  1111. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1112. New(TmpRef);
  1113. Reset_reference(tmpref^);
  1114. TmpRef^.base := R_ESP;
  1115. Paicpu(p)^.LoadRef(0,TmpRef);
  1116. AsmL^.Remove(hp1);
  1117. Dispose(hp1, Done)
  1118. End;
  1119. end;
  1120. A_PUSH:
  1121. Begin
  1122. If (Paicpu(p)^.opsize = S_W) And
  1123. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1124. GetNextInstruction(p, hp1) And
  1125. (Pai(hp1)^.typ = ait_instruction) And
  1126. (Paicpu(hp1)^.opcode = A_PUSH) And
  1127. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1128. (Paicpu(hp1)^.opsize = S_W) Then
  1129. Begin
  1130. Paicpu(p)^.changeopsize(S_L);
  1131. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + Paicpu(hp1)^.oper[0].val);
  1132. AsmL^.Remove(hp1);
  1133. Dispose(hp1, Done)
  1134. End;
  1135. End;
  1136. A_SHL, A_SAL:
  1137. Begin
  1138. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1139. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1140. (Paicpu(p)^.opsize = S_L) And
  1141. (Paicpu(p)^.oper[0].val <= 3)
  1142. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1143. Then
  1144. Begin
  1145. TmpBool1 := True; {should we check the next instruction?}
  1146. TmpBool2 := False; {have we found an add/sub which could be
  1147. integrated in the lea?}
  1148. New(TmpRef);
  1149. Reset_reference(tmpref^);
  1150. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1151. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1152. While TmpBool1 And
  1153. GetNextInstruction(p, hp1) And
  1154. (Pai(hp1)^.typ = ait_instruction) And
  1155. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1156. (Paicpu(hp1)^.opcode = A_SUB)) And
  1157. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1158. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1159. Begin
  1160. TmpBool1 := False;
  1161. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1162. Then
  1163. Begin
  1164. TmpBool1 := True;
  1165. TmpBool2 := True;
  1166. If Paicpu(hp1)^.opcode = A_ADD Then
  1167. Inc(TmpRef^.offset, Paicpu(hp1)^.oper[0].val)
  1168. Else
  1169. Dec(TmpRef^.offset, Paicpu(hp1)^.oper[0].val);
  1170. AsmL^.Remove(hp1);
  1171. Dispose(hp1, Done);
  1172. End
  1173. Else
  1174. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1175. (Paicpu(hp1)^.opcode = A_ADD) And
  1176. (TmpRef^.base = R_NO) Then
  1177. Begin
  1178. TmpBool1 := True;
  1179. TmpBool2 := True;
  1180. TmpRef^.base := Paicpu(hp1)^.oper[0].reg;
  1181. AsmL^.Remove(hp1);
  1182. Dispose(hp1, Done);
  1183. End;
  1184. End;
  1185. If TmpBool2 Or
  1186. ((aktoptprocessor < ClassP6) And
  1187. (Paicpu(p)^.oper[0].val <= 3) And
  1188. Not(CS_LittleSize in aktglobalswitches))
  1189. Then
  1190. Begin
  1191. If Not(TmpBool2) And
  1192. (Paicpu(p)^.oper[0].val = 1)
  1193. Then
  1194. Begin
  1195. Dispose(TmpRef);
  1196. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1197. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1198. End
  1199. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  1200. Paicpu(p)^.oper[1].reg));
  1201. hp1^.fileinfo := p^.fileinfo;
  1202. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1203. Dispose(p, Done);
  1204. p := hp1;
  1205. End;
  1206. End
  1207. Else
  1208. If (aktoptprocessor < ClassP6) And
  1209. (Paicpu(p)^.oper[0].typ = top_const) And
  1210. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1211. If (Paicpu(p)^.oper[0].val = 1)
  1212. Then
  1213. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1214. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1215. (unlike shl, which is only pairable in the U pipe)}
  1216. Begin
  1217. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1218. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1219. hp1^.fileinfo := p^.fileinfo;
  1220. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1221. Dispose(p, done);
  1222. p := hp1;
  1223. End
  1224. Else If (Paicpu(p)^.opsize = S_L) and
  1225. (Paicpu(p)^.oper[0].val<= 3) Then
  1226. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1227. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1228. Begin
  1229. New(TmpRef);
  1230. Reset_reference(tmpref^);
  1231. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1232. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1233. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,TmpRef, Paicpu(p)^.oper[1].reg));
  1234. hp1^.fileinfo := p^.fileinfo;
  1235. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1236. Dispose(p, done);
  1237. p := hp1;
  1238. End
  1239. End;
  1240. A_SAR, A_SHR:
  1241. {changes the code sequence
  1242. shr/sar const1, x
  1243. shl const2, x
  1244. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1245. Begin
  1246. If GetNextInstruction(p, hp1) And
  1247. (pai(hp1)^.typ = ait_instruction) and
  1248. (Paicpu(hp1)^.opcode = A_SHL) and
  1249. (Paicpu(p)^.oper[0].typ = top_const) and
  1250. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1251. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1252. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1253. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1254. Then
  1255. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1256. Not(CS_LittleSize In aktglobalswitches)
  1257. Then
  1258. { shr/sar const1, %reg
  1259. shl const2, %reg
  1260. with const1 > const2 }
  1261. Begin
  1262. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1263. Paicpu(hp1)^.opcode := A_AND;
  1264. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1265. Case Paicpu(p)^.opsize Of
  1266. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1267. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1268. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1269. End;
  1270. End
  1271. Else
  1272. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1273. Not(CS_LittleSize In aktglobalswitches)
  1274. Then
  1275. { shr/sar const1, %reg
  1276. shl const2, %reg
  1277. with const1 < const2 }
  1278. Begin
  1279. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1280. Paicpu(p)^.opcode := A_AND;
  1281. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1282. Case Paicpu(p)^.opsize Of
  1283. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1284. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1285. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1286. End;
  1287. End
  1288. Else
  1289. { shr/sar const1, %reg
  1290. shl const2, %reg
  1291. with const1 = const2 }
  1292. Begin
  1293. Paicpu(p)^.opcode := A_AND;
  1294. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1295. Case Paicpu(p)^.opsize Of
  1296. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1297. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1298. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1299. End;
  1300. AsmL^.remove(hp1);
  1301. dispose(hp1, done);
  1302. End;
  1303. End;
  1304. A_SETcc :
  1305. Begin
  1306. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1307. GetNextInstruction(p, hp1) And
  1308. GetNextInstruction(hp1, hp2) And
  1309. (hp2^.typ = ait_instruction) And
  1310. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1311. (Paicpu(hp2)^.opcode = A_RET)) And
  1312. (Paicpu(p)^.oper[0].ref^.Base = ProcInfo.FramePointer) And
  1313. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1314. (Paicpu(p)^.oper[0].ref^.Offset >= ProcInfo.RetOffset) And
  1315. (hp1^.typ = ait_instruction) And
  1316. (Paicpu(hp1)^.opcode = A_MOV) And
  1317. (Paicpu(hp1)^.opsize = S_B) And
  1318. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1319. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1320. Begin
  1321. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1322. AsmL^.Remove(hp1);
  1323. Dispose(hp1, Done)
  1324. End
  1325. End;
  1326. A_SUB:
  1327. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1328. { * change "sub/add const1, reg" or "dec reg" followed by
  1329. "sub const2, reg" to one "sub ..., reg" }
  1330. Begin
  1331. If (Paicpu(p)^.oper[0].typ = top_const) And
  1332. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1333. If (Paicpu(p)^.oper[0].val = 2) And
  1334. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1335. Begin
  1336. hp1 := Pai(p^.next);
  1337. While Assigned(hp1) And
  1338. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1339. Not((Pai(hp1)^.typ = ait_instruction) And
  1340. ((Paicpu(hp1)^.opcode = A_CALL) or
  1341. (Paicpu(hp1)^.opcode = A_PUSH) or
  1342. ((Paicpu(hp1)^.opcode = A_MOV) And
  1343. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1344. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1345. hp1 := Pai(hp1^.next);
  1346. If Assigned(hp1) And
  1347. (Pai(hp1)^.typ = ait_instruction) And
  1348. (Paicpu(hp1)^.opcode = A_PUSH) And
  1349. (Paicpu(hp1)^.opsize = S_W)
  1350. Then
  1351. Begin
  1352. Paicpu(hp1)^.changeopsize(S_L);
  1353. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1354. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1355. hp1 := Pai(p^.next);
  1356. AsmL^.Remove(p);
  1357. Dispose(p, Done);
  1358. p := hp1;
  1359. Continue
  1360. End;
  1361. If DoSubAddOpt(p) Then continue;
  1362. End
  1363. Else If DoSubAddOpt(p) Then Continue
  1364. End;
  1365. A_TEST, A_OR:
  1366. {removes the line marked with (x) from the sequence
  1367. And/or/xor/add/sub/... $x, %y
  1368. test/or %y, %y (x)
  1369. j(n)z _Label
  1370. as the first instruction already adjusts the ZF}
  1371. Begin
  1372. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1373. If GetLastInstruction(p, hp1) And
  1374. (pai(hp1)^.typ = ait_instruction) Then
  1375. Case Paicpu(hp1)^.opcode Of
  1376. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1377. Begin
  1378. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1379. Begin
  1380. hp1 := pai(p^.next);
  1381. asml^.remove(p);
  1382. dispose(p, done);
  1383. p := pai(hp1);
  1384. continue
  1385. End;
  1386. End;
  1387. A_DEC, A_INC, A_NEG:
  1388. Begin
  1389. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1390. Begin
  1391. Case Paicpu(hp1)^.opcode Of
  1392. A_DEC, A_INC:
  1393. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1394. Begin
  1395. Case Paicpu(hp1)^.opcode Of
  1396. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1397. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1398. End;
  1399. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1400. Paicpu(hp1)^.LoadConst(0,1);
  1401. Paicpu(hp1)^.ops:=2;
  1402. End
  1403. End;
  1404. hp1 := pai(p^.next);
  1405. asml^.remove(p);
  1406. dispose(p, done);
  1407. p := pai(hp1);
  1408. continue
  1409. End;
  1410. End
  1411. End
  1412. Else
  1413. End;
  1414. End;
  1415. end; { if is_jmp }
  1416. End;
  1417. { ait_label:
  1418. Begin
  1419. If Not(Pai_Label(p)^.l^.is_used)
  1420. Then
  1421. Begin
  1422. hp1 := Pai(p^.next);
  1423. AsmL^.Remove(p);
  1424. Dispose(p, Done);
  1425. p := hp1;
  1426. Continue
  1427. End;
  1428. End;}
  1429. End;
  1430. p:=pai(p^.next);
  1431. end;
  1432. end;
  1433. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1434. var
  1435. p,hp1,hp2: pai;
  1436. Begin
  1437. P := BlockStart;
  1438. While (P <> BlockEnd) Do
  1439. Begin
  1440. Case P^.Typ Of
  1441. Ait_Instruction:
  1442. Begin
  1443. Case Paicpu(p)^.opcode Of
  1444. A_CALL:
  1445. If (AktOptProcessor < ClassP6) And
  1446. GetNextInstruction(p, hp1) And
  1447. (hp1^.typ = ait_instruction) And
  1448. (paicpu(hp1)^.opcode = A_JMP) Then
  1449. Begin
  1450. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1451. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1452. hp2^.fileinfo := p^.fileinfo;
  1453. InsertLLItem(AsmL, p^.previous, p, hp2);
  1454. Paicpu(p)^.opcode := A_JMP;
  1455. AsmL^.Remove(hp1);
  1456. Dispose(hp1, Done)
  1457. End;
  1458. A_MOV:
  1459. Begin
  1460. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1461. (Paicpu(p)^.oper[1].typ = top_reg) And
  1462. GetNextInstruction(p, hp1) And
  1463. (hp1^.typ = ait_Instruction) And
  1464. ((Paicpu(hp1)^.opcode = A_MOV) or
  1465. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1466. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1467. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1468. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1469. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1470. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1471. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1472. {mov reg1, reg2
  1473. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1474. Begin
  1475. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1476. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1477. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1478. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1479. AsmL^.Remove(p);
  1480. Dispose(p, Done);
  1481. p := hp1;
  1482. Continue;
  1483. End;
  1484. End;
  1485. A_MOVZX:
  1486. Begin
  1487. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1488. If (Paicpu(p)^.oper[0].typ = top_reg)
  1489. Then
  1490. Case Paicpu(p)^.opsize of
  1491. S_BL:
  1492. Begin
  1493. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1494. Not(CS_LittleSize in aktglobalswitches) And
  1495. (aktoptprocessor = ClassP5)
  1496. Then
  1497. {Change "movzbl %reg1, %reg2" to
  1498. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1499. PentiumMMX}
  1500. Begin
  1501. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1502. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1503. hp1^.fileinfo := p^.fileinfo;
  1504. InsertLLItem(AsmL,p^.previous, p, hp1);
  1505. Paicpu(p)^.opcode := A_MOV;
  1506. Paicpu(p)^.changeopsize(S_B);
  1507. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1508. End;
  1509. End;
  1510. End
  1511. Else
  1512. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1513. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1514. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1515. Not(CS_LittleSize in aktglobalswitches) And
  1516. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1517. (aktoptprocessor = ClassP5) And
  1518. (Paicpu(p)^.opsize = S_BL)
  1519. Then
  1520. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1521. Pentium and PentiumMMX}
  1522. Begin
  1523. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1524. Paicpu(p)^.oper[1].reg));
  1525. hp1^.fileinfo := p^.fileinfo;
  1526. Paicpu(p)^.opcode := A_MOV;
  1527. Paicpu(p)^.changeopsize(S_B);
  1528. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1529. InsertLLItem(AsmL,p^.previous, p, hp1);
  1530. End;
  1531. End;
  1532. End;
  1533. End;
  1534. End;
  1535. p := Pai(p^.next)
  1536. End;
  1537. End;
  1538. End.
  1539. {
  1540. $Log$
  1541. Revision 1.64 1999-08-25 12:00:02 jonas
  1542. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1543. Revision 1.63 1999/08/23 10:20:46 jonas
  1544. * fixed pop/push optmization
  1545. Revision 1.62 1999/08/10 12:30:00 pierre
  1546. * avoid unused locals
  1547. Revision 1.61 1999/08/05 15:02:48 jonas
  1548. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1549. Revision 1.60 1999/08/04 00:23:16 florian
  1550. * renamed i386asm and i386base to cpuasm and cpubase
  1551. Revision 1.59 1999/08/03 17:13:28 jonas
  1552. * fix for sar/shr-shl optimization
  1553. Revision 1.58 1999/07/30 18:17:55 jonas
  1554. * fix so (,reg) gets optimized to (reg)
  1555. Revision 1.57 1999/07/01 18:12:16 jonas
  1556. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1557. a movzx or movsx
  1558. Revision 1.56 1999/06/23 12:33:52 jonas
  1559. * merged
  1560. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1561. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1562. Revision 1.55 1999/06/18 09:55:31 peter
  1563. * merged
  1564. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1565. * pop;push -> mov (esp),reg always instead of being removed
  1566. Revision 1.54 1999/05/27 19:44:49 peter
  1567. * removed oldasm
  1568. * plabel -> pasmlabel
  1569. * -a switches to source writing automaticly
  1570. * assembler readers OOPed
  1571. * asmsymbol automaticly external
  1572. * jumptables and other label fixes for asm readers
  1573. Revision 1.53 1999/05/12 00:19:52 peter
  1574. * removed R_DEFAULT_SEG
  1575. * uniform float names
  1576. Revision 1.52 1999/05/05 16:19:04 jonas
  1577. + remove the segment prefixes from LEA instructions
  1578. Revision 1.51 1999/05/05 10:05:54 florian
  1579. * a delphi compiled compiler recompiles ppc
  1580. Revision 1.50 1999/05/02 21:33:55 florian
  1581. * several bugs regarding -Or fixed
  1582. Revision 1.49 1999/05/02 14:26:31 peter
  1583. * fixed dec -> sub $1 opt which didn't set ops=2
  1584. Revision 1.48 1999/05/01 13:24:34 peter
  1585. * merged nasm compiler
  1586. * old asm moved to oldasm/
  1587. Revision 1.5 1999/04/30 12:36:50 jonas
  1588. * fix from Brussels: call/jmp => push/jmp transformation didn't
  1589. count correctly the jmp references
  1590. Revision 1.4 1999/04/10 16:14:11 peter
  1591. * fixed optimizer
  1592. Revision 1.3 1999/04/09 08:33:18 peter
  1593. * fixed mov reg,treg;mov treg,x bug
  1594. Revision 1.2 1999/03/29 16:05:51 peter
  1595. * optimizer working for ag386bin
  1596. Revision 1.1 1999/03/26 00:01:15 peter
  1597. * first things for optimizer (compiles but cycle crashes)
  1598. Revision 1.39 1999/02/26 00:48:22 peter
  1599. * assembler writers fixed for ag386bin
  1600. Revision 1.38 1999/02/25 21:02:44 peter
  1601. * ag386bin updates
  1602. + coff writer
  1603. Revision 1.37 1999/02/22 02:15:30 peter
  1604. * updates for ag386bin
  1605. Revision 1.36 1999/01/04 22:04:15 jonas
  1606. + mov reg, mem1 to mov reg, mem1
  1607. mov mem2, reg cmp reg, mem2
  1608. cmp mem1, reg
  1609. # reg released
  1610. Revision 1.35 1999/01/04 12:58:55 jonas
  1611. * no fistp/fild optimization for S_IQ (fistq doesn't exist)
  1612. Revision 1.34 1998/12/29 18:48:17 jonas
  1613. + optimize pascal code surrounding assembler blocks
  1614. Revision 1.33 1998/12/23 15:16:21 jonas
  1615. * change "inc x/dec x; test x, x" to "add 1, x/sub 1,x" because inc and dec
  1616. don't affect the carry flag (test does). This *doesn't* fix the problem with
  1617. cardinal, that's a cg issue.
  1618. Revision 1.32 1998/12/16 12:09:29 jonas
  1619. * fixed fistp/fild optimization
  1620. Revision 1.31 1998/12/15 22:30:39 jonas
  1621. + change "sub/add const1, reg" or "dec reg" followed by "sub const2, reg" to one
  1622. "sub const3, reg"
  1623. * some small cleaning up
  1624. Revision 1.30 1998/12/15 15:43:20 jonas
  1625. * fixed bug in shr/shl optimization
  1626. Revision 1.29 1998/12/15 11:53:54 peter
  1627. * removed commentlevel
  1628. Revision 1.28 1998/12/14 22:01:45 jonas
  1629. - removed $ifdef ver0_99_11's
  1630. Revision 1.27 1998/12/11 00:03:35 peter
  1631. + globtype,tokens,version unit splitted from globals
  1632. Revision 1.26 1998/12/09 18:16:13 jonas
  1633. * corrected small syntax error in part between ifdef ver0_99_11
  1634. + added fistp/fild optimization between ifdef ver0_99_11
  1635. Revision 1.25 1998/12/02 16:23:29 jonas
  1636. * changed "if longintvar in set" to case or "if () or () .." statements
  1637. * tree.pas: changed inlinenumber (and associated constructor/vars) to a byte
  1638. Revision 1.24 1998/11/26 15:41:45 jonas
  1639. + change "setxx mem; movb mem, reg8" to "setxx reg8" if mem is a local
  1640. variable/parameter or function result (between $ifdef ver0_99_11)
  1641. Revision 1.23 1998/11/03 16:26:09 jonas
  1642. * "call x;jmp y" optimization not done anymore for P6 and equivalents
  1643. * made FPU optimizations simpler and more effective
  1644. Revision 1.22 1998/10/29 18:37:55 jonas
  1645. + change "call x; jmp y" to "push y; jmp x" (suggestion from Daniel)
  1646. Revision 1.19 1998/10/23 15:38:23 jonas
  1647. + some small FPU peephole optimizations (use value in FP regs instead of loading it
  1648. from memory if possible, mostly with var1+var1 and var1*var1)
  1649. Revision 1.18 1998/10/05 14:41:14 jonas
  1650. * fixed small memory leak
  1651. * fixed small inefficiency
  1652. * tested multiple line comments ability of my new MacCVS client :)
  1653. Revision 1.17 1998/10/02 17:29:56 jonas
  1654. + removal of "lea (reg), reg)", "imul $1, reg", change "mov reg1, reg2; mov (reg2), reg2" to "mov (reg1), reg2"
  1655. Revision 1.16 1998/10/01 20:19:57 jonas
  1656. * moved UpdateUsedRegs (+ bugfix) to daopt386
  1657. Revision 1.15 1998/09/30 12:18:29 peter
  1658. * fixed subl $2,esp;psuhw bug
  1659. Revision 1.14 1998/09/20 17:11:51 jonas
  1660. * released REGALLOC
  1661. Revision 1.13 1998/09/16 18:00:00 jonas
  1662. * optimizer now completely dependant on GetNext/GetLast instruction, works again with -dRegAlloc
  1663. Revision 1.12 1998/09/15 14:05:22 jonas
  1664. * fixed optimizer incompatibilities with freelabel code in psub
  1665. Revision 1.11 1998/08/28 10:57:02 peter
  1666. * removed warnings
  1667. Revision 1.10 1998/08/27 15:17:50 florian
  1668. * reinstated Jonas' bugfix
  1669. Revision 1.9 1998/08/25 16:58:59 pierre
  1670. * removed a line that add no sense and
  1671. introduce garbage in the asmlist
  1672. (uninitialized data !)
  1673. Revision 1.7 1998/08/19 16:07:53 jonas
  1674. * changed optimizer switches + cleanup of DestroyRefs in daopt386.pas
  1675. Revision 1.6 1998/08/10 14:50:14 peter
  1676. + localswitches, moduleswitches, globalswitches splitting
  1677. Revision 1.5 1998/08/06 19:40:28 jonas
  1678. * removed $ before and after Log in comment
  1679. Revision 1.4 1998/08/05 16:27:17 jonas
  1680. * fstp/fld bugfix (fstt does not exist)
  1681. Revision 1.3 1998/08/05 16:00:15 florian
  1682. * some fixes for ansi strings
  1683. * log to Log changed
  1684. }