freepascal.compiler/compiler/arm/armins.dat

;
; Table of assembler instructions for Free Pascal
; adapted from Netwide Assembler by Florian Klaempfl
;
;
; The Netwide Assembler is copyright (C) 1996 Simon Tatham and
; Julian Hall. All rights reserved. The software is
; redistributable under the licence given in the file "Licence"
; distributed in the NASM archive.
;
; Format of file: all four fields must be present on every functional
; line. Hence `void' for no-operand instructions, and `\0' for such
; as EQU. If the last three fields are all `ignore', no action is
; taken except to register the opcode as being present.
;
;
; 'ignore' means no instruc
; 'void'   means instruc with zero operands
;
; Third field has a first byte indicating how to
; put together the bits, and then some codes
; that may be used at will (see assemble.c)
;
; \1   - 24 bit pc-rel offset		[B, BL]
; \2   - 24 bit imm value		[SWI]
; \3   -  3 byte code			[BX]
;
; \4   - reg,reg,reg			[AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC]
; \5   - reg,reg,reg,<shift>reg		[-"-]
; \6   - reg,reg,reg,<shift>#imm	[-"-]
; \7   - reg,reg,#imm			[-"-]
;
; \x8  - reg,reg			[MOV,MVN]
; \x9  - reg,reg,<shift>reg		[-"-]
; \xA  - reg,reg,<shift>#imm		[-"-]
; \xB  - reg,#imm			[-"-]
;
; \xC  - reg,reg			[CMP,CMN,TEQ,TST]
; \xD  - reg,reg,<shift>reg		[-"-]
; \xE  - reg,reg,<shift>#imm		[-"-]
; \xF  - reg,#imm			[-"-]
;
; \xFx - floating point instructions
;        Floating point instruction format information, taken from the linux kernel,
;        for detailed tables, see aasmcpu.pas
;
;        ARM Floating Point Instruction Classes
;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
;        |c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT
;        |c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|1|0|  o f f s e t  | CPDT (copro 2)
;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
;        |c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO
;        |c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT
;        |c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons
;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
;
;        CPDT            data transfer instructions
;                        LDF, STF, LFM (copro 2), SFM (copro 2)
;
;        CPDO            dyadic arithmetic instructions
;                        ADF, MUF, SUF, RSF, DVF, RDF,
;                        POW, RPW, RMF, FML, FDV, FRD, POL
;
;        CPDO            monadic arithmetic instructions
;                        MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
;                        SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
;
;        CPRT            joint arithmetic/data transfer instructions
;                        FIX (arithmetic followed by load/store)
;                        FLT (load/store followed by arithmetic)
;                        CMF, CNF CMFE, CNFE (comparisons)
;                        WFS, RFS (write/read floating point status register)
;                        WFC, RFC (write/read floating point control register)
; \xF0 - CPDT
;        code 1: copro (1/2)
;        code 2: load/store bit
; \xF1 - CPDO
; \xF2 - CPDO monadic
; \xF3 - CPRT
; \xF4 - CPRT comparison
;
; \xFF - fix me
;

[NONE]
void                  void                            none

[ADCcc]
reglo,reglo                 \x60\x41\x40                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF1\x40\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEB\x40\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEB\x40\x0\x0            THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \4\x0\xA0                     ARM32,ARMv4
reg32,reg32,reg32,shifterop \6\x0\xA0                     ARM32,ARMv4
reg32,reg32,immshifter      \7\x2\xA0                     ARM32,ARMv4

[ADDcc]
reg32,reg32                 \x61\x44\x0                   THUMB,ARMv4T
reglo,reglo,reglo           \x60\x18\x0                   THUMB,ARMv4T

reglo,reglo,immshifter      \x60\x1C\x0                   THUMB,ARMv4T
reglo,immshifter            \x60\x30\x0                   THUMB,ARMv4T

reglo,regsp,immshifter      \x64\xA8\x00                  THUMB,ARMv4T
regsp,regsp,immshifter      \x64\xB0\x00                  THUMB,ARMv4T
reg32,regsp,reg32           \x64\x44\x68                  THUMB,ARMv4T
regsp,reg32                 \x64\x44\x85                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF1\x0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32           \x80\xEB\x0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEB\x0\x0\x0             THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \4\x0\x80                     ARM32,ARMv4
reg32,reg32,reg32,shifterop \6\x0\x80                     ARM32,ARMv4
reg32,reg32,immshifter      \7\x2\x80                     ARM32,ARMv4

[ADDWcc]
reg32,reg32,immshifter      \x81\xF2\x0\x0\x0             THUMB32,ARMv6T2

[ADFcc]

[ADRcc]
;reg32,immshifter           \x33\x2\x0F                   ARM32,ARMv4
;reg32,imm32                \x33\x2\x0F                   ARM32,ARMv4
reglo,immshifter            \x67\xA0\x0\2                 THUMB,ARMv4T
reglo,memam6                \x67\xA0\x0\2                 THUMB,ARMv4T

reg32,imm32                 \x81\xF2\xAF\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,immshifter            \x81\xF2\xAF\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,memam2                \x81\xF2\xAF\x0\x0            THUMB32,WIDE,ARMv6T2

reg32,memam2                \x33\x2\x0F                   ARM32,ARMv4

[ANDcc]
reglo,reglo                 \x60\x40\x00                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF0\x0\x0\x0             THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEA\x0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x0\x0\x0             THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \x4\x0\x00                    ARM32,ARMv4
reg32,reg32,reg32,shifterop \x6\x0\x00                    ARM32,ARMv4
reg32,reg32,immshifter      \x7\x2\x00                    ARM32,ARMv4

[Bcc]
imm24                       \x62\xE0\x0                   THUMB,ARMv4T
immshifter                  \x62\xE0\x0                   THUMB,ARMv4T
mem32                       \x62\xE0\x0                   THUMB,ARMv4T

imm24                       \x63\xD0\x0                   THUMB,ARMv4T
immshifter                  \x63\xD0\x0                   THUMB,ARMv4T
mem32                       \x63\xD0\x0                   THUMB,ARMv4T

imm24                       \x1\x0A                       ARM32,ARMv4
mem32                       \x1\x0A                       ARM32,ARMv4

[BICcc]
reglo,reglo                 \x60\x43\x80                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF0\x20\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEA\x20\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x20\x0\x0            THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \x6\x1\xC0                    ARM32,ARMv4
reg32,reg32,reg32,shifterop \x6\x1\xC0                    ARM32,ARMv4
reg32,reg32,immshifter      \x7\x3\xC0                    ARM32,ARMv4

[BLcc]
imm24                    \x8D\xF0\xD0                   THUMB,THUMB32,ARMv4T
immshifter               \x8D\xF0\xD0                   THUMB,THUMB32,ARMv4T
mem32                    \x8D\xF0\xD0                   THUMB,THUMB32,ARMv4T

imm24                    \x1\x0B                        ARM32,ARMv4
mem32                    \x1\x0B                        ARM32,ARMv4

[BLX]
reg32                    \x62\x47\x80                   THUMB,ARMv4T

immshifter               \x8D\xF0\xC0                   THUMB32,ARMv6T2
imm24                    \x8D\xF0\xC0                   THUMB32,ARMv6T2
mem32                    \x8D\xF0\xC0                   THUMB32,ARMv6T2

imm24                    \x28\xFA                       ARM32,ARMv5T
mem32                    \x28\xFA                       ARM32,ARMv5T
reg32                    \3\x01\x2F\xFF\x30             ARM32,ARMv5T

[BKPTcc]
immshifter               \x60\xBE\x0                   THUMB,ARMv5T
imm                      \x31\x1\x20\x70               ARM32,ARMv5T
immshifter               \x31\x1\x20\x70               ARM32,ARMv5T

[BXcc]
reg32                    \x62\x47\x0                   THUMB,ARMv4T

reg32                    \3\x01\x2F\xFF\x10            ARM32,ARMv4T

[CDP]
reg8,reg8                \300\1\x10\101                ARM32,ARMv4

[CMNcc]
reglo,reglo             \x60\x42\xC0                     THUMB,ARMv4T

reg32,immshifter        \x80\xF1\x10\x0F\x00             THUMB32,ARMv6T2
reg32,reg32             \x80\xEB\x10\x0F\x00             THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop   \x80\xEB\x10\x0F\x00             THUMB32,WIDE,ARMv6T2

reg32,reg32             \xC\x1\x60                       ARM32,ARMv4
reg32,reg32,shifterop   \xE\x1\x60                       ARM32,ARMv4
reg32,immshifter        \xF\x1\x60                       ARM32,ARMv4

[CMPcc]
reglo,reglo             \x60\x42\x80                     THUMB,ARMv4T
reg32,reg32             \x61\x45\x0                      THUMB,ARMv4T

reglo,immshifter        \x60\x28\x0                      THUMB,ARMv4T

reg32,immshifter         \x80\xF1\xB0\x0F\x00           THUMB32,WIDE,ARMv6T2
reg32,reg32              \x80\xEB\xB0\x0F\x00           THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop    \x80\xEB\xB0\x0F\x00           THUMB32,WIDE,ARMv6T2

reg32,reg32              \xC\x1\x40                     ARM32,ARMv4
reg32,reg32,shifterop    \xE\x1\x40                     ARM32,ARMv4
reg32,immshifter         \xF\x3\x40                     ARM32,ARMv4

[CMFcc]

[CMFEcc]

[STFcc]

[LDFcc]

[LFMcc]
reg32,imm8,fpureg        \xF0\x02\x01                   FPA

[CLZcc]
reg32,reg32              \x80\xFA\xB0\xF0\x80           THUMB32,ARMv6T2
reg32,reg32              \x32\x01\x6F\xF\x10            ARM32,ARMv4

[CPS]
[CPSID]
[CPSIE]

[EORcc]
reglo,reglo                 \x60\x40\x40                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF0\x80\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEA\x80\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x80\x0\x0            THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \4\x0\x20                     ARM32,ARMv4
reg32,reg32,reg32,shifterop \6\x0\x20                     ARM32,ARMv4
reg32,reg32,immshifter      \7\x2\x20                     ARM32,ARMv4

[LDC]
reg32,reg32         \321\300\1\x11\101            ARM32,ARMv4

[LDMcc]
memam4,reglist              \x69\xC8            THUMB,ARMv4T
reglo,reglist               \x69\xC8            THUMB,ARMv4T

memam4,reglist              \x8C\xE8\x10\x0\x0  THUMB32,WIDE,ARMv6T2
reg32,reglist               \x8C\xE8\x10\x0\x0  THUMB32,WIDE,ARMv6T2

memam4,reglist		          \x26\x81			   ARM32,ARMv4
reg32,reglist		          \x26\x81			   ARM32,ARMv4

[LDRBTcc]
reg32,memam2              \x88\xF8\x10\xE\x0\0           THUMB32,ARMv6T2
reg32,memam2              \x17\x04\x70                   ARM32,ARMv4
reg32,immshifter          \x17\x04\x70                   ARM32,ARMv4

[LDRBcc]
reglo,memam3              \x65\x5C\x0\0                  THUMB,ARMv4T
reglo,memam4              \x66\x78\x0\0                  THUMB,ARMv4T
reg32,memam2              \x88\xF8\x10\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2              \x17\x04\x50                   ARM32,ARMv4

[LDRcc]
reglo,memam3              \x65\x58\x0\2                  THUMB,ARMv4T
reglo,memam4              \x66\x68\x0\2                  THUMB,ARMv4T
reglo,memam5              \x67\x98\x0\2                  THUMB,ARMv4T
reglo,memam6              \x67\x48\x0\2                  THUMB,ARMv4T
reg32,memam2              \x88\xF8\x50\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2              \x17\x04\x10                   ARM32,ARMv4

[LDRHcc]
reglo,memam3              \x65\x5A\x0\1                  THUMB,ARMv4T
reglo,memam4              \x66\x88\x0\1                  THUMB,ARMv4T
reg32,memam2              \x88\xF8\x30\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2              \x22\x10\xB0                   ARM32,ARMv4

[LDRSBcc]
reglo,memam3              \x65\x56\x0\0                  THUMB,ARMv4T
reg32,memam2              \x88\xF9\x10\x0\x0\0           THUMB32,ARMv6T2
reg32,memam2              \x22\x10\xD0                   ARM32,ARMv4
reg32,reg32               \x23\x50\xD0                   ARM32,ARMv4
reg32,reg32,imm32         \x24\x50\xD0                   ARM32,ARMv4
reg32,reg32,reg32         \x25\x10\xD0                   ARM32,ARMv4

[LDRSHcc]
reglo,memam3              \x65\x5E\x0\1                  THUMB,ARMv4T
reg32,memam2              \x88\xF9\x30\x0\x0\0           THUMB32,ARMv6T2
reg32,memam2              \x22\x10\xF0                   ARM32,ARMv4

[LDRTcc]
reg32,memam2              \x88\xF8\x50\xE\x0\0           THUMB32,ARMv6T2
reg32,memam2              \x17\x04\x30                   ARM32,ARMv4

[MCRcc]
regf,immshifter,reg32,regf,regf              \x1C\xE\x0\x1     ARM32,ARMv4
regf,immshifter,reg32,regf,regf,immshifter   \x1C\xE\x0\x1     ARM32,ARMv4

[MCR2cc]
regf,immshifter,reg32,regf,regf              \x1C\xFE\x0\x1    ARM32,ARMv5T
regf,immshifter,reg32,regf,regf,immshifter   \x1C\xFE\x0\x1    ARM32,ARMv5T

[MRCcc]
regf,immshifter,reg32,regf,regf              \x1C\xE\x10\x1    ARM32,ARMv4
regf,immshifter,reg32,regf,regf,immshifter   \x1C\xE\x10\x1    ARM32,ARMv4

[MRC2cc]
regf,immshifter,reg32,regf,regf              \x1C\xFE\x10\x1   ARM32,ARMv5T
regf,immshifter,reg32,regf,regf,immshifter   \x1C\xFE\x10\x1   ARM32,ARMv5T

[MCRRcc]
regf,immshifter,reg32,reg32,regf             \x1D\xC\x40\x0    ARM32,ARMv5TE

[MCRR2cc]
regf,immshifter,reg32,reg32,regf             \x1D\xFC\x40\x0   ARM32,ARMv6

[MRRCcc]
regf,immshifter,reg32,reg32,regf             \x1D\xC\x50\x0    ARM32,ARMv5TE

[MRRC2cc]
regf,immshifter,reg32,reg32,regf             \x1D\xFC\x50\x0   ARM32,ARMv6

[MLAcc]
reg32,reg32,reg32,reg32  \x80\xFB\x0\x0\x0              THUMB32,ARMv6T2
reg32,reg32,reg32,reg32  \x15\x00\x20\x9                ARM32,ARMv4

[MOVcc]
reglo,reglo             \x60\x0\x0                       THUMB,ARMv4T
reg32,reg32             \x61\x46\x00                     THUMB,ARMv4T

reglo,immshifter        \x60\x20\x0                      THUMB,ARMv4T

reg32,immshifter        \x80\xF0\x4F\x0\x0               THUMB32,WIDE,ARMv6T2

reg32,reg32             \x80\xEA\x4F\x0\x0               THUMB32,WIDE,ARMv6T2

reg32,shifterop         \x8\x1\xA0                       ARM32,ARMv4
reg32,reg32,shifterop   \xA\x1\xA0                       ARM32,ARMv4
reg32,immshifter        \xB\x1\xA0                       ARM32,ARMv4

[MRScc]
reg32,regf          \x10\x01\x0F                        ARM32,ARMv4

[MSRcc]
regf,reg32          \x12\x01\x28\xF0                    ARM32,ARMv4
regf,immshifter     \x13\x03\x28\xF0                    ARM32,ARMv4
regs,immshifter     \x13\x03\x28\xF0                    ARM32,ARMv4

[MULcc]
reglo,reglo,reglo      \x64\x43\x40              THUMB,ARMv4T
reg32,reg32,reg32      \x80\xFB\x00\xF0\x00      THUMB32,ARMv6T2
reg32,reg32,reg32      \x14\x00\x00\x90          ARM32,ARMv4

[MVFcc]
fpureg,fpureg              \xF2                      FPA
fpureg,immfpu              \xF2                      FPA

[MVNcc]
reglo,reglo             \x60\x43\xc0                    THUMB,ARMv4T

reg32,immshifter        \x80\xF0\x6F\x0\x0               THUMB32,ARMv6T2
reg32,reg32             \x80\xEA\x6F\x0\x0               THUMB32,WIDE,ARMv6T2

reg32,reg32            \x8\x1\xE0                       ARM32,ARMv4
reg32,reg32,shifterop  \xA\x1\xE0                       ARM32,ARMv4
reg32,immshifter       \xB\x1\xE0                       ARM32,ARMv4

[VMOVcc]
vreg,vreg         \x40\xE\xB0\xA\x40            ARM32,VFPv2

reg32,vreg        \x40\xE\x10\xA\x10            ARM32,VFPv2
vreg,reg32        \x40\xE\x00\xA\x10            ARM32,VFPv2

reg32,reg32,vreg,vreg \x40\xC\x50\xA\x10        ARM32,VFPv2
vreg,vreg,reg32,reg32 \x40\xC\x40\xA\x10        ARM32,VFPv2

reg32,reg32,vreg      \x40\xC\x50\xB\x10        ARM32,VFPv2
vreg,reg32,reg32      \x40\xC\x40\xB\x10        ARM32,VFPv2

[NOP]
void                    \x61\xBF\x0                  THUMB,ARMv6T2
void                    \x2F\x03\x20\xF0\x0          ARM32,ARMv6K
; Before ARMv6K use mov r0,r0
void                    \x2F\xE1\xA0\x0\x0           ARM32,ARMv4

[ORNcc]
reg32,reg32,immshifter      \x80\xF0\x60\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEA\x60\x0\x0            THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x60\x0\x0            THUMB32,WIDE,ARMv6T2

[ORRcc]
reglo,reglo                  \x60\x43\x00            THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF0\x40\x0\x0       THUMB32,ARMv6T2
reg32,reg32,reg32           \x80\xEA\x40\x0\x0       THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x40\x0\x0       THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32            \4\x1\x80               ARM32,ARMv4
reg32,reg32,reg32,reg32      \5\x1\x80               ARM32,ARMv4
reg32,reg32,reg32,shifterop  \6\x1\x80               ARM32,ARMv4
reg32,reg32,immshifter       \7\x3\x80               ARM32,ARMv4

[RSBcc]
reglo,reglo,immzero         \x60\x42\x40                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF1\xC0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32           \x80\xEB\xC0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEB\xC0\x0\x0             THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32            \6\x0\x60                     ARM32,ARMv4
reg32,reg32,reg32,shifterop  \6\x0\x60                     ARM32,ARMv4
reg32,reg32,immshifter       \7\x0\x60                     ARM32,ARMv4

[RSCcc]
reg32,reg32,reg32            \4\x0\xE0                     ARM32,ARMv4
reg32,reg32,reg32,reg32      \5\x0\xE0                     ARM32,ARMv4
reg32,reg32,reg32,shifterop  \6\x0\xE0                     ARM32,ARMv4
reg32,reg32,immshifter       \7\x2\xE0                     ARM32,ARMv4

[SBCcc]
reglo,reglo                 \x60\x41\x80                  THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF1\x60\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32           \x80\xEB\x60\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEB\x60\x0\x0             THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32           \4\x0\xC0                     ARM32,ARMv4
reg32,reg32,reg32,reg32     \5\x0\xC0                     ARM32,ARMv4
reg32,reg32,reg32,imm       \6\x0\xC0                     ARM32,ARMv4
reg32,reg32,reg32,shifterop \6\x0\xC0                     ARM32,ARMv4
reg32,reg32,immshifter      \7\x2\xC0                     ARM32,ARMv4

[SFMcc]
reg32,imm8,fpureg           \xF0\x02\x00                  FPA

[SINcc]

[SMLALcc]
reg32,reg32,reg32,reg32     \x85\xFB\xC0\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32,reg32     \x16\x00\xE0\x9               ARM32,ARMv4

[SMULLcc]
reg32,reg32,reg32,reg32     \x85\xFB\x80\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32,reg32     \x16\x00\xC0\x9               ARM32,ARMv4

[STMcc]
memam4,reglist              \x69\xC0            THUMB,ARMv4T
reglo,reglist               \x69\xC0            THUMB,ARMv4T

memam4,reglist              \x8C\xE8\x00\x0\x0  THUMB32,WIDE,ARMv6T2
reg32,reglist               \x8C\xE8\x00\x0\x0  THUMB32,WIDE,ARMv6T2

memam4,reglist		          \x26\x80			   ARM32,ARMv4
reg32,reglist		          \x26\x80			   ARM32,ARMv4

[STRcc]
reglo,memam3                \x65\x50\x0\2                  THUMB,ARMv4T
reglo,memam4                \x66\x60\x0\2                  THUMB,ARMv4T
reglo,memam5                \x67\x90\x0\2                  THUMB,ARMv4T
reg32,memam2                \x88\xF8\x40\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2                \x17\x04\x00                   ARM32,ARMv4

[STRBcc]
reglo,memam3                \x65\x54\x0\0                  THUMB,ARMv4T
reglo,memam4                \x66\x70\x0\0                  THUMB,ARMv4T
reg32,memam2                \x88\xF8\x00\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2                \x17\x04\x40                   ARM32,ARMv4

[STRBTcc]
reg32,memam2                \x88\xF8\x00\xE\x0\0           THUMB32,ARMv6T2
reg32,memam2                \x17\x04\x60                   ARM32,ARMv4
reg32,immshifter            \x17\x04\x60                   ARM32,ARMv4

[STRHcc]
reglo,memam3                \x65\x52\x0\1                  THUMB,ARMv4T
reglo,memam4                \x66\x80\x0\1                  THUMB,ARMv4T
reg32,memam2                \x88\xF8\x20\x0\x0\0           THUMB32,WIDE,ARMv6T2
reg32,memam2                \x22\x00\xB0                   ARM32,ARMv4

[STRTcc]
reg32,memam2                \x88\xF8\x40\xE\x0\0           THUMB32,ARMv6T2
reg32,memam2                \x17\x04\x20                   ARM32,ARMv4

[SUBcc]
regsp,regsp,immshifter      \x64\xB0\x80                   THUMB,ARMv4T
reglo,reglo,reglo           \x60\x1A\x0                    THUMB,ARMv4T

reglo,reglo,immshifter      \x60\x1E\x0                    THUMB,ARMv4T
reglo,imm8                  \x60\x38\x0                    THUMB,ARMv4T

reg32,reg32,immshifter      \x80\xF1\xA0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32           \x80\xEB\xA0\x0\x0             THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEB\xA0\x0\x0             THUMB32,WIDE,ARMv6T2

reg32,reg32,shifterop       \x4\x0\x40                     ARM32,ARMv4
reg32,reg32,immshifter      \x4\x0\x40                     ARM32,ARMv4
reg32,reg32,reg32           \x4\x0\x40                     ARM32,ARMv4
reg32,reg32,reg32,shifterop \x6\x0\x40                     ARM32,ARMv4

[SWIcc]
imm                         \x2\x0F                        ARM32,ARMv4
immshifter                  \x2\x0F                        ARM32,ARMv4

[SWPcc]
reg32,reg32,memam2          \x27\x10\x09                   ARM32,ARMv4

[SWPBcc]
reg32,reg32,memam2          \x27\x14\x09                   ARM32,ARMv4

[TEQcc]
reg32,immshifter      \x80\xF0\x90\x0F\x00           THUMB32,ARMv6T2
reg32,reg32           \x80\xEA\x90\x0F\x00           THUMB32,ARMv6T2
reg32,reg32,shifterop \x80\xEA\x90\x0F\x00           THUMB32,ARMv6T2

reg32,reg32           \xC\x1\x20                     ARM32,ARMv4
reg32,reg32,reg32     \xD\x1\x20                     ARM32,ARMv4
reg32,reg32,shifterop \xE\x1\x20                     ARM32,ARMv4
reg32,immshifter      \xF\x3\x20                     ARM32,ARMv4

[TSTcc]
reglo,reglo           \x60\x42\x00                   THUMB,ARMv4T

reg32,immshifter      \x80\xF0\x10\x0F\x00           THUMB32,ARMv6T2
reg32,reg32           \x80\xEA\x10\x0F\x00           THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop \x80\xEA\x10\x0F\x00           THUMB32,WIDE,ARMv6T2

reg32,reg32           \xC\x1\x00                     ARM32,ARMv4
reg32,reg32,reg32     \xD\x1\x00                     ARM32,ARMv4
reg32,reg32,shifterop \xE\x1\x00                     ARM32,ARMv4
reg32,immshifter      \xF\x3\x00                     ARM32,ARMv4

[UMLALcc]
reg32,reg32,reg32,reg32     \x85\xFB\xE0\x0\x00     THUMB32,ARMv6T2
reg32,reg32,reg32,reg32     \x16\x00\xA0\x9         ARM32,ARMv4

[UMULLcc]
reg32,reg32,reg32,reg32     \x85\xFB\xA0\x0\x0      THUMB32,ARMv6T2
reg32,reg32,reg32,reg32     \x16\x00\x80\x9         ARM32,ARMv4

[WFScc]

; EDSP instructions
[LDRDcc]
reg32,reg32,memam2         \x89\xE8\x50\x0\x0                  THUMB32,ARMv6T2
reg32,reg32,memam2         \x19\x0\x0\x0\xD0                   ARM32,ARMv4

[PLD]
memam2                     \x87\xF8\x10\xF0\x0                 THUMB32,ARMv6T2
memam2                     \x25\xF5\x50\xF0\x0                 ARM32,ARMv5TE

[PLDW]
memam2                     \x87\xF8\x30\xF0\x0                 THUMB32,ARMv7
memam2                     \x25\xF5\x10\xF0\x0                 ARM32,ARMv7

[QADDcc]
reg32,reg32,reg32          \x82\xFA\x80\xF0\x80                THUMB32,ARMv6T2
reg32,reg32,reg32          \x1A\x01\x00\x05                    ARM32,ARMv5TE

[QDADDcc]
reg32,reg32,reg32          \x82\xFA\x80\xF0\x90                THUMB32,ARMv6T2
reg32,reg32,reg32          \x1A\x01\x40\x05                    ARM32,ARMv5TE

[QDSUBcc]
reg32,reg32,reg32          \x82\xFA\x80\xF0\xB0                THUMB32,ARMv6T2
reg32,reg32,reg32          \x1A\x01\x60\x05                    ARM32,ARMv5TE

[QSUBcc]
reg32,reg32,reg32          \x82\xFA\x80\xF0\xA0                THUMB32,ARMv6T2
reg32,reg32,reg32          \x1A\x01\x20\x05                    ARM32,ARMv5TE

[SMLABBcc]
reg32,reg32,reg32,reg32     \x15\x01\x00\x8                     ARM32,ARMv5TE

[SMLABTcc]
reg32,reg32,reg32,reg32     \x15\x01\x00\xC                     ARM32,ARMv5TE

[SMLATBcc]
reg32,reg32,reg32,reg32     \x15\x01\x00\xA                     ARM32,ARMv5TE

[SMLATTcc]
reg32,reg32,reg32,reg32     \x15\x01\x00\xE                     ARM32,ARMv5TE

[SMLALBBcc]
reg32,reg32,reg32,reg32     \x16\x01\x40\x8                     ARM32,ARMv5TE

[SMLALBTcc]
reg32,reg32,reg32,reg32     \x16\x01\x40\xC                     ARM32,ARMv5TE

[SMLALTBcc]
reg32,reg32,reg32,reg32     \x16\x01\x40\xA                     ARM32,ARMv5TE

[SMLALTTcc]
reg32,reg32,reg32,reg32     \x16\x01\x40\xE                     ARM32,ARMv5TE

[SMLAWBcc]

[SMLAWTcc]

[VLDMcc]
memam4,reglist		      \x44\xC\x10\xA		         ARM32,VFPv2
reg32,reglist		      \x44\xC\x10\xA		         ARM32,VFPv2

[VSTMcc]
memam4,reglist		      \x44\xC\x00\xA		         ARM32,VFPv2
reg32,reglist		      \x44\xC\x00\xA		         ARM32,VFPv2

[VPOP]
reglist		            \x44\xC\xBD\xA		         ARM32,VFPv2

[VPUSH]
reglist		            \x44\xD\x2D\xA		         ARM32,VFPv2

[VLDRcc]
vreg,memam2             \x45\xD\x10\xA             ARM32,VFPv2

[VSTRcc]
vreg,memam2             \x45\xD\x0\xA              ARM32,VFPv2

[SMULBBcc]
reg32,reg32,reg32           \x15\x01\x60\x8\x0                  ARM32,ARMv5TE

[SMULBTcc]
reg32,reg32,reg32           \x15\x01\x60\xC\x0                  ARM32,ARMv5TE

[SMULTBcc]
reg32,reg32,reg32           \x15\x01\x60\xA\x0                  ARM32,ARMv5TE

[SMULTTcc]
reg32,reg32,reg32           \x15\x01\x60\xE\x0                  ARM32,ARMv5TE

[SMULWBcc]
reg32,reg32,reg32           \x14\x1\x20\xA0                     ARM32,ARMv5TE

[SMULWTcc]
reg32,reg32,reg32           \x14\x1\x20\xE0                     ARM32,ARMv5TE

[STRDcc]
reg32,reg32,memam2         \x89\xE8\x40\x0\x0                  THUMB32,ARMv6T2
reg32,reg32,memam2         \x19\x0\x0\x0\xF0                   ARM32,ARMv4

[LDRHTcc]
reg32,memam2               \x88\xF8\x30\xE\x0\0                THUMB32,ARMv6T2
reg32,memam2               \x19\x0\x30\x0\xB0                  ARM32,ARMv4

[STRHTcc]
reg32,memam2               \x88\xF8\x20\xE\x0\0                THUMB32,ARMv6T2

reg32,memam2               \x88\xF8\x20\xE\x0\0                THUMB32,ARMv6T2
reg32,memam2               \x1E\x0\x20\x0\xB0                  ARM32,ARMv4

[LDRSBTcc]
reg32,memam2               \x88\xF9\x10\xE\x0\0                THUMB32,ARMv6T2
reg32,memam2               \x1E\x0\x30\x0\xD0                  ARM32,ARMv4

[LDRSHTcc]
reg32,memam2              \x88\xF9\x30\xE\x0\0         THUMB32,ARMv6T2
reg32,memam2              \x1E\x0\x30\x0\xF0           ARM32,ARMv4

[FSTDcc]

[FSTMcc]

[FSTScc]

; ARMv6

[BFCcc]
reg32,immshifter,immshifter       \x84\xF3\x6F\x0\x0            THUMB32,ARMv6T2
reg32,immshifter,imm32            \x84\xF3\x6F\x0\x0            THUMB32,ARMv6T2

reg32,immshifter,immshifter       \x2D\x7\xC0\x0\x1F            ARM32,ARMv4
reg32,immshifter,imm32            \x2D\x7\xC0\x0\x1F            ARM32,ARMv4

[BFIcc]
reg32,reg32,immshifter,immshifter \x84\xF3\x60\x0\x0            THUMB32,ARMv6T2
reg32,reg32,immshifter,imm32      \x84\xF3\x60\x0\x0            THUMB32,ARMv6T2

reg32,reg32,immshifter,immshifter \x2D\x7\xC0\x0\x10            ARM32,ARMv4
reg32,reg32,immshifter,imm32      \x2D\x7\xC0\x0\x10            ARM32,ARMv4

[CLREX]
void                      \x80\xF3\xBF\x8F\x2F            THUMB32,ARMv7
void                      \x2F\xF5\x7F\xF0\x1F            ARM32,ARMv6K

[LDREXcc]
reg32,memam6              \x8A\xE8\x50\x0F\x00            THUMB32,ARMv6T2
reg32,memam6              \x18\x01\x90\x0F\x9F            ARM32,ARMv4

[LDREXBcc]
reg32,memam6              \x8A\xE8\xD0\x0F\x4F            THUMB32,ARMv7
reg32,memam6              \x18\x01\xD0\x0F\x9F            ARM32,ARMv4

[LDREXDcc]
reg32,reg32,memam6        \x8A\xE8\xD0\x00\x7F            THUMB32,ARMv7
reg32,reg32,memam6        \x18\x01\xB0\x0F\x9F            ARM32,ARMv4

[LDREXHcc]
reg32,memam6              \x8A\xE8\xD0\x0F\x5F            THUMB32,ARMv7
reg32,memam6              \x18\x01\xF0\x0F\x9F            ARM32,ARMv4

[STREXcc]
reg32,reg32,memam6        \x8B\xE8\x40\x00\x00            THUMB32,ARMv6T2
reg32,reg32,memam6        \x18\x01\x80\x0F\x90            ARM32,ARMv4

[STREXBcc]
reg32,reg32,memam6        \x8B\xE8\xC0\x0F\x40            THUMB32,ARMv7
reg32,reg32,memam6        \x18\x01\xC0\x0F\x90            ARM32,ARMv4

[STREXDcc]
reg32,reg32,reg32,memam6  \x8B\xE8\xC0\x00\x70            THUMB32,ARMv7
reg32,reg32,reg32,memam6  \x18\x01\xA0\x0F\x90            ARM32,ARMv4

[STREXHcc]
reg32,reg32,memam6        \x8B\xE8\xC0\x0F\x50            THUMB32,ARMv7
reg32,reg32,memam6        \x18\x01\xE0\x0F\x90            ARM32,ARMv4

[MLScc]
reg32,reg32,reg32,reg32   \x80\xFB\x0\x0\x10              THUMB32,ARMv6T2
reg32,reg32,reg32,reg32   \x15\x00\x60\x9                 ARM32,ARMv6T2

[PKHBTcc]
reg32,reg32,reg32           \x80\xEA\xC0\x0\x0            THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\xC0\x0\x0            THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x6\x80\x1                     ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x6\x80\x1                     ARM32,ARMv6

[PKHTBcc]
reg32,reg32,reg32           \x80\xEA\xC0\x0\x10           THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\xC0\x0\x10           THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x6\x80\x1                     ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x6\x80\x5                     ARM32,ARMv6

[PLI]
memam2                     \x87\xF9\x10\xF0\x0                 THUMB32,ARMv7
memam2                     \x25\xF4\x50\xF0\x0                 ARM32,ARMv7

[QADD16cc]
reg32,reg32,reg32          \x80\xFA\x90\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xF1                    ARM32,ARMv6
[QADD8cc]
reg32,reg32,reg32          \x80\xFA\x80\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xF9                    ARM32,ARMv6
[QASXcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xF3                    ARM32,ARMv6
[QSAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xF5                    ARM32,ARMv6
[QSUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xF7                    ARM32,ARMv6
[QSUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x10                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x20\xFF                    ARM32,ARMv6

[RBITcc]
reg32,reg32                \x80\xFA\x90\xF0\xA0                THUMB32,ARMv6T2
reg32,reg32                \x32\x6\xFF\xF\x30                  ARM32,ARMv6T2

[REVcc]
reglo,reglo                \x61\xBA\x00                        THUMB,ARMv6
reg32,reg32                \x80\xFA\x90\xF0\x80                THUMB32,WIDE,ARMv6T2
reg32,reg32                \x32\x6\xBF\xF\x30                  ARM32,ARMv6

[REV16cc]
reglo,reglo                \x61\xBA\x40                        THUMB,ARMv6
reg32,reg32                \x80\xFA\x90\xF0\x90                THUMB32,WIDE,ARMv6T2
reg32,reg32                \x32\x6\xBF\xF\xB0                  ARM32,ARMv6

[REVSHcc]
reglo,reglo                \x61\xBA\xC0                        THUMB,ARMv6
reg32,reg32                \x80\xFA\x90\xF0\xB0                THUMB32,WIDE,ARMv6T2
reg32,reg32                \x32\x6\xFF\xF\xB0                  ARM32,ARMv6

[SADD16cc]
reg32,reg32,reg32          \x80\xFA\90\xF0\x0                  THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xF1                    ARM32,ARMv6

[SADD8cc]
reg32,reg32,reg32          \x80\xFA\80\xF0\x0                  THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xF9                    ARM32,ARMv6

[SASXcc]
reg32,reg32,reg32          \x80\xFA\A0\xF0\x0                  THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xF3                    ARM32,ARMv6

[SBFXcc]
reg32,reg32,immshifter,immshifter \x84\xF3\x40\x0\x0           THUMB32,ARMv6T2
reg32,reg32,immshifter,immshifter \x2D\x7\xA0\x0\x50           ARM32,ARMv6T2

[SELcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x80                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x80\xFB                    ARM32,ARMv6

[SETEND]
immshifter                 \x2B\xF1\x01\x0\x0                  ARM32,ARMv6

[SEVcc]
void                       \x64\xBF\x40                        THUMB,ARMv7
void                       \x2F\x3\x20\xF0\x4                  ARM32,ARMv6K

[ASRcc]
reglo,reglo,immshifter     \x60\x1\x0                          THUMB,ARMv4T
reglo,reglo                \x60\x41\x0                         THUMB,ARMv4T

reg32,reg32,immshifter     \x82\xEA\x4F\x0\x20                 THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32          \x80\xFA\x40\xF0\x0                 THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32          \x30\x1\xA0\x0\x50                  ARM32,ARMv4
reg32,reg32,immshifter     \x30\x1\xA0\x0\x40                  ARM32,ARMv4

[LSRcc]
reglo,reglo,immshifter     \x60\x8\x0                          THUMB,ARMv4T
reglo,reglo                \x60\x40\xC0                        THUMB,ARMv4T

reg32,reg32,immshifter     \x82\xEA\x4F\x0\x10                 THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32          \x80\xFA\x20\xF0\x0                 THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32          \x30\x1\xA0\x0\x30                  ARM32,ARMv4
reg32,reg32,immshifter     \x30\x1\xA0\x0\x20                  ARM32,ARMv4

[LSLcc]
reglo,reglo,immshifter     \x60\x0\x0                          THUMB,ARMv4T
reglo,reglo                \x60\x40\x80                        THUMB,ARMv4T

reg32,reg32,immshifter     \x82\xEA\x4F\x0\x00                 THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32          \x80\xFA\x60\xF0\x0                 THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32          \x30\x1\xA0\x0\x10                  ARM32,ARMv4
reg32,reg32,immshifter     \x30\x1\xA0\x0\x00                  ARM32,ARMv4

[RORcc]
reglo,reglo                \x60\x41\xC0                        THUMB,ARMv4T

reg32,reg32,immshifter     \x82\xEA\x4F\x0\x30                 THUMB32,WIDE,ARMv6T2
reg32,reg32,reg32          \x80\xFA\x60\xF0\x0                 THUMB32,WIDE,ARMv6T2

reg32,reg32,reg32          \x30\x1\xA0\x0\x70                  ARM32,ARMv4
reg32,reg32,immshifter     \x30\x1\xA0\x0\x60                  ARM32,ARMv4

[RRXcc]
reg32,reg32                \x80\xEA\x4F\x00\x30                THUMB32,ARMv6T2
reg32,reg32                \x30\x1\xA0\x0\x60                  ARM32,ARMv4

[UMAALcc]
reg32,reg32,reg32,reg32     \x85\xFB\xE0\x0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32,reg32     \x16\x0\x40\x9                     ARM32,ARMv6

[SHADD16cc]
reg32,reg32,reg32          \x80\xFA\x90\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xF1                    ARM32,ARMv6

[SHADD8cc]
reg32,reg32,reg32          \x80\xFA\x80\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xF9                    ARM32,ARMv6

[SHASXcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xF3                    ARM32,ARMv6

[SHSAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xF5                    ARM32,ARMv6

[SHSUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xF7                    ARM32,ARMv6

[SHSUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x20                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x30\xFF                    ARM32,ARMv6

[SMLADcc]
reg32,reg32,reg32,reg32    \x80\xFB\x20\x0\x00                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x15\x7\x00\x1                      ARM32,ARMv6

[SMLALDcc]
reg32,reg32,reg32,reg32    \x85\xFB\xC0\x0\xC0                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x16\x7\x40\x1                      ARM32,ARMv4

[SMLSDcc]
reg32,reg32,reg32,reg32    \x80\xFB\x40\x0\x00                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x15\x7\x00\x5                      ARM32,ARMv6

[SMLSLDcc]
reg32,reg32,reg32,reg32    \x85\xFB\xD0\x0\xC0                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x16\x7\x40\x5                      ARM32,ARMv6

[SMMLAcc]
reg32,reg32,reg32,reg32    \x80\xFB\x50\x0\x00                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x15\x7\x50\x1                      ARM32,ARMv6

[SMMLScc]
reg32,reg32,reg32,reg32    \x80\xFB\x60\x0\x00                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x15\x7\x50\xD                      ARM32,ARMv6

[SMMULcc]
reg32,reg32,reg32          \x80\xFB\x50\xF0\x0                 THUMB32,ARMv6T2
reg32,reg32,reg32          \x15\x7\x50\x1\xF                   ARM32,ARMv6

[SMUADcc]
reg32,reg32,reg32          \x80\xFB\x20\xF0\x0                 THUMB32,ARMv6T2
reg32,reg32,reg32          \x15\x7\x00\x1\xF                   ARM32,ARMv6

[SMUSDcc]
reg32,reg32,reg32          \x80\xFB\x40\xF0\x0                 THUMB32,ARMv6T2
reg32,reg32,reg32          \x15\x7\x00\x5\xF                   ARM32,ARMv6

[SRScc]

[SSATcc]
reg32,immshifter,reg32            \x83\xF3\x00\x0\x0          THUMB32,ARMv6T2
reg32,immshifter,reg32,shifterop  \x83\xF3\x00\x0\x0          THUMB32,ARMv6T2

reg32,immshifter,reg32            \x2A\x6\xA0\x0\x10          ARM32,ARMv6
reg32,immshifter,reg32,shifterop  \x2A\x6\xA0\x0\x10          ARM32,ARMv6

[SSAT16cc]
reg32,immshifter,reg32            \x83\xF3\x20\x0\x0          THUMB32,ARMv6T2
reg32,immshifter,reg32            \x2A\x6\xA0\xF\x30          ARM32,ARMv6

[SSAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x0                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xF5                   ARM32,ARMv6

[SSUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x0                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xF7                   ARM32,ARMv6

[SSUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x0                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x10\xFF                   ARM32,ARMv6

[SXTABcc]
reg32,reg32,reg32           \x86\xFA\x40\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x40\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x06\xA0\x07                  ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x06\xA0\x07                  ARM32,ARMv6

[SXTAB16cc]
reg32,reg32,reg32           \x86\xFA\x20\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x20\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x06\x80\x07                  ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x06\x80\x07                  ARM32,ARMv6

[SXTAHcc]
reg32,reg32,reg32           \x86\xFA\x00\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x00\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x06\xB0\x07                  ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x06\xB0\x07                  ARM32,ARMv6

[UBFXcc]
reg32,reg32,immshifter,immshifter \x84\xF3\xC0\x0\x0          THUMB32,ARMv6T2
reg32,reg32,immshifter,immshifter \x2D\x7\xE0\x0\x50          ARM32,ARMv4

[UXTABcc]
reg32,reg32,reg32           \x86\xFA\x50\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x50\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x6\xE0\x7                    ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x6\xE0\x7                    ARM32,ARMv6

[UXTAB16cc]
reg32,reg32,reg32           \x86\xFA\x30\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x30\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x86\xFA\x40\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x40\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x6\xC0\x7                     ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x6\xC0\x7                     ARM32,ARMv6

[UXTAHcc]
reg32,reg32,reg32           \x86\xFA\x10\xF0\x80              THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x86\xFA\x10\xF0\x80              THUMB32,ARMv6T2

reg32,reg32,reg32           \x16\x6\xF0\x7                     ARM32,ARMv6
reg32,reg32,reg32,shifterop \x16\x6\xF0\x7                     ARM32,ARMv6

[SXTBcc]
reglo,reglo                 \x61\xB2\x40                       THUMB,ARMv6

reg32,reg32                 \x86\xFA\x4F\xF0\x80               THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x4F\xF0\x80               THUMB32,WIDE,ARMv6T2

reg32,reg32                 \x1B\x6\xAF\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\xAF\x7                     ARM32,ARMv6

[SXTB16cc]
reg32,reg32                 \x86\xFA\x2F\xF0\x80               THUMB32,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x2F\xF0\x80               THUMB32,ARMv6T2

reg32,reg32                 \x1B\x6\x8F\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\x8F\x7                     ARM32,ARMv6

[SXTHcc]
reglo,reglo                 \x61\xB2\x00                       THUMB,ARMv6

reg32,reg32                 \x86\xFA\x0F\xF0\x80               THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x0F\xF0\x80               THUMB32,WIDE,ARMv6T2

reg32,reg32                 \x1B\x6\xBF\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\xBF\x7                     ARM32,ARMv6

[UXTBcc]
reglo,reglo                 \x61\xB2\xC0                       THUMB,ARMv6

reg32,reg32                 \x86\xFA\x5F\xF0\x80               THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x5F\xF0\x80               THUMB32,WIDE,ARMv6T2

reg32,reg32                 \x1B\x6\xEF\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\xEF\x7                     ARM32,ARMv6

[UXTB16cc]
reg32,reg32                 \x86\xFA\x3F\xF0\x80               THUMB32,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x3F\xF0\x80               THUMB32,ARMv6T2

reg32,reg32                 \x1B\x6\xCF\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\xCF\x7                     ARM32,ARMv6

[UXTHcc]
reglo,reglo                 \x61\xB2\x80                       THUMB,ARMv6

reg32,reg32                 \x86\xFA\x1F\xF0\x80               THUMB32,WIDE,ARMv6T2
reg32,reg32,shifterop       \x86\xFA\x1F\xF0\x80               THUMB32,WIDE,ARMv6T2

reg32,reg32                 \x1B\x6\xFF\x7                     ARM32,ARMv6
reg32,reg32,shifterop       \x1B\x6\xFF\x7                     ARM32,ARMv6

[UADD16cc]
reg32,reg32,reg32          \x80\xFA\x90\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xF1                    ARM32,ARMv6

[UADD8cc]
reg32,reg32,reg32          \x80\xFA\x80\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xF9                    ARM32,ARMv6

[UASXcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xF3                    ARM32,ARMv6

[UHADD16cc]
reg32,reg32,reg32          \x80\xFA\x90\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xF1                    ARM32,ARMv6

[UHADD8cc]
reg32,reg32,reg32          \x80\xFA\x80\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xF9                    ARM32,ARMv6

[UHASXcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xF3                    ARM32,ARMv6

[UHSAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xF5                    ARM32,ARMv6

[UHSUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xF7                    ARM32,ARMv6

[UHSUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x60                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x70\xFF                    ARM32,ARMv6

[UQADD16cc]
reg32,reg32,reg32          \x80\xFA\x90\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xF1                    ARM32,ARMv6

[UQADD8]
reg32,reg32,reg32          \x80\xFA\x80\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xF9                    ARM32,ARMv6

[UQASXcc]
reg32,reg32,reg32          \x80\xFA\xA0\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xF3                    ARM32,ARMv6

[UQSAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xF5                    ARM32,ARMv6

[UQSUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xF7                    ARM32,ARMv6

[UQSUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x50                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x60\xFF                    ARM32,ARMv6

[USAD8cc]
reg32,reg32,reg32          \x80\xFB\x70\xF0\x00                THUMB32,ARMv6T2
reg32,reg32,reg32          \x15\x07\x80\x01\xF                 ARM32,ARMv6

[USADA8cc]
reg32,reg32,reg32,reg32    \x80\xFB\x70\x0\x00                 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32    \x15\x07\x80\x01                    ARM32,ARMv6

[USATcc]
reg32,immshifter,reg32            \x83\xF3\x80\x0\x0          THUMB32,ARMv6T2
reg32,immshifter,reg32,shifterop  \x83\xF3\x80\x0\x0          THUMB32,ARMv6T2

reg32,immshifter,reg32            \x2A\x6\xE0\x0\x10          ARM32,ARMv6
reg32,immshifter,reg32,shifterop  \x2A\x6\xE0\x0\x10          ARM32,ARMv6

[USAT16cc]
reg32,immshifter,reg32            \x83\xF3\xA0\x0\x0          THUMB32,ARMv6T2
reg32,immshifter,reg32            \x2A\x6\xE0\xF\x30          ARM32,ARMv6

[USAXcc]
reg32,reg32,reg32          \x80\xFA\xE0\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xF5                    ARM32,ARMv6

[USUB16cc]
reg32,reg32,reg32          \x80\xFA\xD0\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xF7                    ARM32,ARMv6

[USUB8cc]
reg32,reg32,reg32          \x80\xFA\xC0\xF0\x40                THUMB32,ARMv6T2
reg32,reg32,reg32          \x16\x06\x50\xFF                    ARM32,ARMv6

[WFEcc]
void                          \x64\xBF\x20                     THUMB,ARMv7
void                          \x2F\x3\x20\xF0\x2               ARM32,ARMv6K

[WFIcc]
void                          \x64\xBF\x30                     THUMB,ARMv7
void                          \x2F\x3\x20\xF0\x3               ARM32,ARMv6K

[YIELDcc]
void                          \x64\xBF\x10                     THUMB,ARMv7
void                          \x2F\x3\x20\xF0\x1               ARM32,ARMv6K

;
; vfp instructions
;
[FABSDcc]

[FABSScc]

[FADDDcc]

[FADDScc]

[FCMPDcc]

[FCMPEDcc]

[FCMPEScc]

[FCMPEZDcc]

[FCMPEZScc]

[FCMPScc]

[FCMPZDcc]

[FCMPZScc]

[FCPYDcc]

[FCPYScc]

[FCVTDScc]

[FCVTSDcc]

[FDIVDcc]

[FDIVScc]

[FLDDcc]

[FLDMcc]

[FLDScc]

[FMACDcc]

[FMACScc]

[FMDHRcc]

[FMDLRcc]

[FMRDHcc]

[FMRDLcc]

[FMRScc]

[FMRXcc]

[FMSCDcc]

[FMSCScc]

[FMSRcc]

[FMSTATcc]

[FMULDcc]

[FMULScc]

[FMXRcc]

[FNEGDcc]

[FNEGScc]

[FNMACDcc]

[FNMACScc]

[FNMSCDcc]

[FNMSCScc]

[FNMULDcc]

[FNMULScc]

[FSITODcc]

[FSITOScc]

[FSQRTDcc]

[FSQRTScc]

[FSUBDcc]

[FSUBScc]

[FTOSIDcc]

[FTOSIScc]

[FTOUIDcc]

[FTOUIScc]

[FUITODcc]

[FUITOScc]

[FMDRRcc]

[FMRRDcc]

; Thumb-2

[POP]
reglist                       \x69\xBC                   THUMB,ARMv4T
reglist		                  \x26\x8B		               ARM32,ARMv4

[PUSH]
reglist                       \x69\xB4                   THUMB,ARMv4T
reglist		                  \x26\x80		               ARM32,ARMv4

[SDIVcc]
reg32,reg32,reg32             \x80\xFB\x90\xF0\xF0       THUMB32,ARMv7R,ARMv7M

[UDIVcc]
reg32,reg32,reg32             \x80\xFB\xB0\xF0\xF0       THUMB32,ARMv7R,ARMv7M

[MOVTcc]
reg32,imm                     \x81\xF2\xC0\x0\x0         THUMB32,ARMv6T2
reg32,immshifter              \x81\xF2\xC0\x0\x0         THUMB32,ARMv6T2

reg32,imm                     \x2C\x3\x40                ARM32,ARMv6T2
reg32,immshifter              \x2C\x3\x40                ARM32,ARMv6T2

[IT]
condition                     \x6A\xBF\x08\x00           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITE]
condition                     \x6A\xBF\x04\x88           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITT]
condition                     \x6A\xBF\x04\x08           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITEE]
condition                     \x6A\xBF\x02\xCC           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTE]
condition                     \x6A\xBF\x02\x4C           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITET]
condition                     \x6A\xBF\x02\x8C           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTT]
condition                     \x6A\xBF\x02\x0C           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITEEE]
condition                     \x6A\xBF\x01\xEE           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTEE]
condition                     \x6A\xBF\x01\x6E           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITETE]
condition                     \x6A\xBF\x01\xAE           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTTE]
condition                     \x6A\xBF\x01\x2E           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITEET]
condition                     \x6A\xBF\x01\xCE           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTET]
condition                     \x6A\xBF\x01\x4E           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITETT]
condition                     \x6A\xBF\x01\x8E           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[ITTTT]
condition                     \x6A\xBF\x01\x0E           THUMB,ARMv6T2
condition                     \xFE                       ARM32,ARMv4

[TBB]
[TBH]

[MOVW]
reg32,imm32             \x2C\x3\x0                 ARM32,ARMv6T2
reg32,immshifter        \x2C\x3\x0                 ARM32,ARMv6T2

reg32,imm32             \x81\xF2\x40\x0\x0         THUMB32,ARMv6T2
reg32,immshifter        \x81\xF2\x40\x0\x0         THUMB32,ARMv6T2

[CBZ]
reglo,immshifter        \x68\xB1                   THUMB,ARMv6T2
reglo,memam2            \x68\xB1                   THUMB,ARMv6T2

[CBNZ]
reglo,immshifter        \x68\xB9                   THUMB,ARMv6T2
reglo,memam2            \x68\xB9                   THUMB,ARMv6T2

; VFP
[VABScc]
vreg,vreg               \x42\xE\xB0\xA\xC0         ARM32,VFPv2

[VADDcc]
vreg,vreg,vreg          \x42\xE\x30\xA\x0          ARM32,VFPv2

[VCMPcc]
vreg,vreg               \x42\xE\xB4\xA\x40         ARM32,VFPv2
vreg,immshifter         \x42\xE\xB5\xA\x40         ARM32,VFPv2

[VCMPEcc]
vreg,vreg               \x42\xE\xB4\xA\xC0         ARM32,VFPv2
vreg,immshifter         \x42\xE\xB5\xA\xC0         ARM32,VFPv2

[VCVTcc]
vreg,vreg               \x43\xE\xB8\xA\xC0         ARM32,VFPv2
vreg,vreg,immshifter    \x43\xE\xBA\xA\x40         ARM32,VFPv3

[VCVTRcc]
vreg,vreg               \x43\xE\xB8\xA\x40         ARM32,VFPv2

[VDIVcc]
vreg,vreg,vreg          \x42\xE\x80\xA\x0          ARM32,VFPv2

[VMRScc]
reg32,regf              \x41\xE\xF0\xA\x10         ARM32,VFPv2
regf,regf               \x41\xE\xF0\xA\x10         ARM32,VFPv2

[VMSRcc]
regf,reg32              \x41\xE\xE0\xA\x10         ARM32,VFPv2

[VMLAcc]
vreg,vreg,vreg          \x42\xE\x0\xA\x00          ARM32,VFPv2

[VMLScc]
vreg,vreg,vreg          \x42\xE\x0\xA\x40          ARM32,VFPv2

[VMULcc]
vreg,vreg,vreg          \x42\xE\x20\xA\x0          ARM32,VFPv2

[VNMLAcc]
vreg,vreg,vreg          \x42\xE\x10\xA\x40         ARM32,VFPv2

[VNMLScc]
vreg,vreg,vreg          \x42\xE\x10\xA\x00         ARM32,VFPv2

[VNMULcc]
vreg,vreg,vreg          \x42\xE\x20\xA\x40         ARM32,VFPv2

[VFMA]
[VFMS]
[VFNMA]
[VFNMS]

[VNEGcc]
vreg,vreg               \x42\xE\xB1\xA\x40         ARM32,VFPv2

[VSQRT]
vreg,vreg               \x42\xE\xB1\xA\xC0         ARM32,VFPv2

[VSUB]
vreg,vreg,vreg          \x42\xE\x30\xA\x40         ARM32,VFPv2

[DMB]
immshifter        \x80\xF3\xBF\x8F\x50             THUMB32,ARMv7
immshifter        \x2E\xF5\x7F\xF0\x50             ARM32,ARMv7

[ISB]
immshifter        \x80\xF3\xBF\x8F\x60             THUMB32,ARMv7
immshifter        \x2E\xF5\x7F\xF0\x60             ARM32,ARMv7

[DSB]
immshifter        \x80\xF3\xBF\x8F\x40             THUMB32,ARMv7
immshifter        \x2E\xF5\x7F\xF0\x40             ARM32,ARMv7

[SMC]
immshifter        \x2E\x01\x60\x00\x70             ARM32,ARMv7

; Thumb armv6-m (gcc)
[NEG]

[SVC]
immshifter         \x61\xDF\x0                     THUMB,ARMv4T

imm32              \x2\x0F                         ARM32,ARMv4
immshifter         \x2\x0F                         ARM32,ARMv4

[BXJcc]
reg32              \x80\xF3\xC0\x8F\x0             THUMB32,ARMv6T2
reg32              \x3\x01\x2F\xFF\x20             ARM32,ARMv5TEJ

; Undefined mnemonic
[UDF]
immshifter           \x61\xDE\x0                   THUMB,ARMv4T
void                 void                          ARM32,ARMv4T

; FPA


[TANcc]

[SQTcc]

[SUFcc]

[RSFcc]

[RNDcc]

[POLcc]

[RDFcc]

[RFScc]

[RFCcc]

[RMFcc]

[RPWcc]

[MNFcc]

[MUFcc]

[ABScc]

[ACScc]

[ASNcc]

[ATNcc]

[CNFcc]

[COScc]

[DVFcc]

[EXPcc]

[FDVcc]

[FLTcc]

[FIXcc]

[FMLcc]

[FRDcc]

[LGNcc]

[LOGcc]