cgcpu.pas 72 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister); override;
  45. procedure a_op_const_reg_reg(list : TAsmList;op : TOpCg;size : tcgsize; a : tcgint;src,dst : tregister); override;
  46. { move instructions }
  47. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  48. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  49. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  50. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  51. { fpu move instructions }
  52. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  53. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  54. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  55. { comparison operations }
  56. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  57. l : tasmlabel);override;
  58. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  59. procedure a_jmp_name(list : TAsmList;const s : string); override;
  60. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  61. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  62. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  63. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  64. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  65. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  66. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  67. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  68. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  69. procedure g_save_registers(list : TAsmList);override;
  70. procedure g_restore_registers(list : TAsmList);override;
  71. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  72. procedure fixref(list : TAsmList;var ref : treference);
  73. function normalize_ref(list : TAsmList;ref : treference;
  74. tmpreg : tregister) : treference;
  75. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  76. procedure a_adjust_sp(list: TAsmList; value: longint);
  77. function GetLoad(const ref : treference) : tasmop;
  78. function GetStore(const ref: treference): tasmop;
  79. protected
  80. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  81. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  82. end;
  83. tcg64favr = class(tcg64f32)
  84. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  85. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  86. end;
  87. procedure create_codegen;
  88. const
  89. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  90. A_NONE,A_MULS,A_MUL,A_NEG,A_COM,A_OR,
  91. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  92. implementation
  93. uses
  94. globals,verbose,systems,cutils,
  95. fmodule,
  96. symconst,symsym,symtable,
  97. tgobj,rgobj,
  98. procinfo,cpupi,
  99. paramgr;
  100. procedure tcgavr.init_register_allocators;
  101. begin
  102. inherited init_register_allocators;
  103. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  104. [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  105. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,
  106. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17],first_int_imreg,[]);
  107. end;
  108. procedure tcgavr.done_register_allocators;
  109. begin
  110. rg[R_INTREGISTER].free;
  111. // rg[R_ADDRESSREGISTER].free;
  112. inherited done_register_allocators;
  113. end;
  114. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  115. var
  116. tmp1,tmp2,tmp3 : TRegister;
  117. begin
  118. case size of
  119. OS_8,OS_S8:
  120. Result:=inherited getintregister(list, size);
  121. OS_16,OS_S16:
  122. begin
  123. Result:=inherited getintregister(list, OS_8);
  124. { ensure that the high register can be retrieved by
  125. GetNextReg
  126. }
  127. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  128. internalerror(2011021331);
  129. end;
  130. OS_32,OS_S32:
  131. begin
  132. Result:=inherited getintregister(list, OS_8);
  133. tmp1:=inherited getintregister(list, OS_8);
  134. { ensure that the high register can be retrieved by
  135. GetNextReg
  136. }
  137. if tmp1<>GetNextReg(Result) then
  138. internalerror(2011021332);
  139. tmp2:=inherited getintregister(list, OS_8);
  140. { ensure that the upper register can be retrieved by
  141. GetNextReg
  142. }
  143. if tmp2<>GetNextReg(tmp1) then
  144. internalerror(2011021333);
  145. tmp3:=inherited getintregister(list, OS_8);
  146. { ensure that the upper register can be retrieved by
  147. GetNextReg
  148. }
  149. if tmp3<>GetNextReg(tmp2) then
  150. internalerror(2011021334);
  151. end;
  152. else
  153. internalerror(2011021330);
  154. end;
  155. end;
  156. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  157. begin
  158. Result:=getintregister(list,OS_ADDR);
  159. end;
  160. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  161. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  162. var
  163. ref : treference;
  164. begin
  165. paramanager.allocparaloc(list,paraloc);
  166. case paraloc^.loc of
  167. LOC_REGISTER,LOC_CREGISTER:
  168. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  169. LOC_REFERENCE,LOC_CREFERENCE:
  170. begin
  171. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  172. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  173. end;
  174. else
  175. internalerror(2002071004);
  176. end;
  177. end;
  178. var
  179. i, i2 : longint;
  180. hp : PCGParaLocation;
  181. begin
  182. { if use_push(cgpara) then
  183. begin
  184. if tcgsize2size[cgpara.Size] > 2 then
  185. begin
  186. if tcgsize2size[cgpara.Size] <> 4 then
  187. internalerror(2013031101);
  188. if cgpara.location^.Next = nil then
  189. begin
  190. if tcgsize2size[cgpara.location^.size] <> 4 then
  191. internalerror(2013031101);
  192. end
  193. else
  194. begin
  195. if tcgsize2size[cgpara.location^.size] <> 2 then
  196. internalerror(2013031101);
  197. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  198. internalerror(2013031101);
  199. if cgpara.location^.Next^.Next <> nil then
  200. internalerror(2013031101);
  201. end;
  202. if tcgsize2size[cgpara.size]>cgpara.alignment then
  203. pushsize:=cgpara.size
  204. else
  205. pushsize:=int_cgsize(cgpara.alignment);
  206. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  207. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  208. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  209. end
  210. else
  211. begin
  212. cgpara.check_simple_location;
  213. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  214. pushsize:=cgpara.location^.size
  215. else
  216. pushsize:=int_cgsize(cgpara.alignment);
  217. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  218. end;
  219. end
  220. else }
  221. begin
  222. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  223. internalerror(2014011101);
  224. hp:=cgpara.location;
  225. i:=0;
  226. while i<tcgsize2size[cgpara.Size] do
  227. begin
  228. if not(assigned(hp)) then
  229. internalerror(2014011102);
  230. inc(i, tcgsize2size[hp^.Size]);
  231. if hp^.Loc=LOC_REGISTER then
  232. begin
  233. load_para_loc(r,hp);
  234. hp:=hp^.Next;
  235. r:=GetNextReg(r);
  236. end
  237. else
  238. begin
  239. load_para_loc(r,hp);
  240. for i2:=1 to tcgsize2size[hp^.Size] do
  241. r:=GetNextReg(r);
  242. hp:=hp^.Next;
  243. end;
  244. end;
  245. if assigned(hp) then
  246. internalerror(2014011103);
  247. end;
  248. end;
  249. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  250. var
  251. i : longint;
  252. hp : PCGParaLocation;
  253. begin
  254. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  255. internalerror(2014011101);
  256. hp:=paraloc.location;
  257. for i:=1 to tcgsize2size[paraloc.Size] do
  258. begin
  259. if not(assigned(hp)) then
  260. internalerror(2014011105);
  261. case hp^.loc of
  262. LOC_REGISTER,LOC_CREGISTER:
  263. begin
  264. if (tcgsize2size[hp^.size]<>1) or
  265. (hp^.shiftval<>0) then
  266. internalerror(2015041101);
  267. a_load_const_reg(list,hp^.size,(a shr (8*(i-1))) and $ff,hp^.register);
  268. hp:=hp^.Next;
  269. end;
  270. LOC_REFERENCE,LOC_CREFERENCE:
  271. list.concat(taicpu.op_const(A_PUSH,(a shr (8*(i-1))) and $ff));
  272. else
  273. internalerror(2002071004);
  274. end;
  275. end;
  276. end;
  277. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  278. var
  279. tmpref, ref: treference;
  280. location: pcgparalocation;
  281. sizeleft: tcgint;
  282. begin
  283. location := paraloc.location;
  284. tmpref := r;
  285. sizeleft := paraloc.intsize;
  286. while assigned(location) do
  287. begin
  288. paramanager.allocparaloc(list,location);
  289. case location^.loc of
  290. LOC_REGISTER,LOC_CREGISTER:
  291. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  292. LOC_REFERENCE:
  293. begin
  294. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  295. { doubles in softemu mode have a strange order of registers and references }
  296. if location^.size=OS_32 then
  297. g_concatcopy(list,tmpref,ref,4)
  298. else
  299. begin
  300. g_concatcopy(list,tmpref,ref,sizeleft);
  301. if assigned(location^.next) then
  302. internalerror(2005010710);
  303. end;
  304. end;
  305. LOC_VOID:
  306. begin
  307. // nothing to do
  308. end;
  309. else
  310. internalerror(2002081103);
  311. end;
  312. inc(tmpref.offset,tcgsize2size[location^.size]);
  313. dec(sizeleft,tcgsize2size[location^.size]);
  314. location := location^.next;
  315. end;
  316. end;
  317. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  318. var
  319. tmpreg: tregister;
  320. begin
  321. tmpreg:=getaddressregister(list);
  322. a_loadaddr_ref_reg(list,r,tmpreg);
  323. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  324. end;
  325. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  326. begin
  327. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  328. list.concat(taicpu.op_sym(A_CALL,current_asmdata.RefAsmSymbol(s)))
  329. else
  330. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  331. include(current_procinfo.flags,pi_do_call);
  332. end;
  333. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  334. begin
  335. a_reg_alloc(list,NR_ZLO);
  336. a_reg_alloc(list,NR_ZHI);
  337. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  338. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  339. list.concat(taicpu.op_none(A_ICALL));
  340. a_reg_dealloc(list,NR_ZLO);
  341. a_reg_dealloc(list,NR_ZHI);
  342. include(current_procinfo.flags,pi_do_call);
  343. end;
  344. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  345. begin
  346. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  347. internalerror(2012102403);
  348. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  349. end;
  350. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  351. begin
  352. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  353. internalerror(2012102401);
  354. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  355. end;
  356. procedure tcgavr.a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
  357. begin
  358. if (op in [OP_MUL,OP_IMUL]) and (size in [OS_16,OS_S16]) then
  359. begin
  360. getcpuregister(list,NR_R0);
  361. getcpuregister(list,NR_R1);
  362. list.concat(taicpu.op_reg_reg(A_MUL,src1,src2));
  363. emit_mov(list,dst,NR_R0);
  364. emit_mov(list,GetNextReg(dst),NR_R1);
  365. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(src1),src2));
  366. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  367. list.concat(taicpu.op_reg_reg(A_MUL,src1,GetNextReg(src2)));
  368. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  369. ungetcpuregister(list,NR_R0);
  370. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  371. ungetcpuregister(list,NR_R1);
  372. end
  373. else
  374. inherited a_op_reg_reg_reg(list,op,size,src1,src2,dst);
  375. end;
  376. procedure tcgavr.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
  377. begin
  378. if (op in [OP_MUL,OP_IMUL]) and (size in [OS_16,OS_S16]) and (a in [1,2,4,8]) then
  379. begin
  380. emit_mov(list,dst,src);
  381. emit_mov(list,GetNextReg(dst),GetNextReg(src));
  382. a:=a shr 1;
  383. while a>0 do
  384. begin
  385. list.concat(taicpu.op_reg(A_LSL,dst));
  386. list.concat(taicpu.op_reg(A_ROL,GetNextReg(dst)));
  387. a:=a shr 1;
  388. end;
  389. end
  390. else
  391. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  392. end;
  393. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  394. var
  395. countreg,
  396. tmpreg: tregister;
  397. i : integer;
  398. instr : taicpu;
  399. paraloc1,paraloc2,paraloc3 : TCGPara;
  400. l1,l2 : tasmlabel;
  401. pd : tprocdef;
  402. procedure NextSrcDst;
  403. begin
  404. if i=5 then
  405. begin
  406. dst:=dsthi;
  407. src:=srchi;
  408. end
  409. else
  410. begin
  411. dst:=GetNextReg(dst);
  412. src:=GetNextReg(src);
  413. end;
  414. end;
  415. { iterates TmpReg through all registers of dst }
  416. procedure NextTmp;
  417. begin
  418. if i=5 then
  419. tmpreg:=dsthi
  420. else
  421. tmpreg:=GetNextReg(tmpreg);
  422. end;
  423. begin
  424. case op of
  425. OP_ADD:
  426. begin
  427. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  428. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  429. begin
  430. for i:=2 to tcgsize2size[size] do
  431. begin
  432. NextSrcDst;
  433. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  434. end;
  435. end;
  436. end;
  437. OP_SUB:
  438. begin
  439. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  440. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  441. begin
  442. for i:=2 to tcgsize2size[size] do
  443. begin
  444. NextSrcDst;
  445. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  446. end;
  447. end;
  448. end;
  449. OP_NEG:
  450. begin
  451. if src<>dst then
  452. begin
  453. if size in [OS_S64,OS_64] then
  454. begin
  455. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  456. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  457. end
  458. else
  459. a_load_reg_reg(list,size,size,src,dst);
  460. end;
  461. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  462. begin
  463. tmpreg:=GetNextReg(dst);
  464. for i:=2 to tcgsize2size[size] do
  465. begin
  466. list.concat(taicpu.op_reg(A_COM,tmpreg));
  467. NextTmp;
  468. end;
  469. list.concat(taicpu.op_reg(A_NEG,dst));
  470. tmpreg:=GetNextReg(dst);
  471. for i:=2 to tcgsize2size[size] do
  472. begin
  473. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  474. NextTmp;
  475. end;
  476. end;
  477. end;
  478. OP_NOT:
  479. begin
  480. for i:=1 to tcgsize2size[size] do
  481. begin
  482. if src<>dst then
  483. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  484. list.concat(taicpu.op_reg(A_COM,dst));
  485. NextSrcDst;
  486. end;
  487. end;
  488. OP_MUL,OP_IMUL:
  489. begin
  490. if size in [OS_8,OS_S8] then
  491. begin
  492. cg.a_reg_alloc(list,NR_R0);
  493. cg.a_reg_alloc(list,NR_R1);
  494. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  495. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  496. cg.a_reg_dealloc(list,NR_R1);
  497. list.concat(taicpu.op_reg_reg(A_MOV,dst,NR_R0));
  498. cg.a_reg_dealloc(list,NR_R0);
  499. end
  500. else if size=OS_16 then
  501. begin
  502. tmpreg:=getintregister(list,OS_16);
  503. emit_mov(list,tmpreg,dst);
  504. emit_mov(list,GetNextReg(tmpreg),GetNextReg(dst));
  505. list.concat(taicpu.op_reg_reg(A_MUL,tmpreg,src));
  506. emit_mov(list,dst,NR_R0);
  507. emit_mov(list,GetNextReg(dst),NR_R1);
  508. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(tmpreg),src));
  509. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  510. list.concat(taicpu.op_reg_reg(A_MUL,tmpreg,GetNextReg(src)));
  511. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  512. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  513. { keep code for muls with overflow checking
  514. pd:=search_system_proc('fpc_mul_word');
  515. paraloc1.init;
  516. paraloc2.init;
  517. paraloc3.init;
  518. paramanager.getintparaloc(list,pd,1,paraloc1);
  519. paramanager.getintparaloc(list,pd,2,paraloc2);
  520. paramanager.getintparaloc(list,pd,3,paraloc3);
  521. a_load_const_cgpara(list,OS_8,0,paraloc3);
  522. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  523. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  524. paramanager.freecgpara(list,paraloc3);
  525. paramanager.freecgpara(list,paraloc2);
  526. paramanager.freecgpara(list,paraloc1);
  527. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  528. a_call_name(list,'FPC_MUL_WORD',false);
  529. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  530. cg.a_reg_alloc(list,NR_R24);
  531. cg.a_reg_alloc(list,NR_R25);
  532. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R24,dst);
  533. cg.a_reg_dealloc(list,NR_R24);
  534. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R25,GetNextReg(dst));
  535. cg.a_reg_dealloc(list,NR_R25);
  536. paraloc3.done;
  537. paraloc2.done;
  538. paraloc1.done;
  539. }
  540. end
  541. else
  542. internalerror(2011022002);
  543. end;
  544. OP_DIV,OP_IDIV:
  545. { special stuff, needs separate handling inside code }
  546. { generator }
  547. internalerror(2011022001);
  548. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  549. begin
  550. current_asmdata.getjumplabel(l1);
  551. current_asmdata.getjumplabel(l2);
  552. countreg:=getintregister(list,OS_8);
  553. a_load_reg_reg(list,size,OS_8,src,countreg);
  554. list.concat(taicpu.op_reg(A_TST,countreg));
  555. a_jmp_flags(list,F_EQ,l2);
  556. cg.a_label(list,l1);
  557. case op of
  558. OP_SHR:
  559. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  560. OP_SHL:
  561. list.concat(taicpu.op_reg(A_LSL,dst));
  562. OP_SAR:
  563. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  564. OP_ROR:
  565. begin
  566. { load carry? }
  567. if not(size in [OS_8,OS_S8]) then
  568. begin
  569. list.concat(taicpu.op_none(A_CLC));
  570. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  571. list.concat(taicpu.op_none(A_SEC));
  572. end;
  573. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  574. end;
  575. OP_ROL:
  576. begin
  577. { load carry? }
  578. if not(size in [OS_8,OS_S8]) then
  579. begin
  580. list.concat(taicpu.op_none(A_CLC));
  581. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  582. list.concat(taicpu.op_none(A_SEC));
  583. end;
  584. list.concat(taicpu.op_reg(A_ROL,dst))
  585. end;
  586. else
  587. internalerror(2011030901);
  588. end;
  589. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  590. begin
  591. for i:=2 to tcgsize2size[size] do
  592. begin
  593. case op of
  594. OP_ROR,
  595. OP_SHR:
  596. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  597. OP_ROL,
  598. OP_SHL:
  599. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  600. OP_SAR:
  601. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  602. else
  603. internalerror(2011030902);
  604. end;
  605. end;
  606. end;
  607. list.concat(taicpu.op_reg(A_DEC,countreg));
  608. a_jmp_flags(list,F_NE,l1);
  609. // keep registers alive
  610. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  611. cg.a_label(list,l2);
  612. end;
  613. OP_AND,OP_OR,OP_XOR:
  614. begin
  615. for i:=1 to tcgsize2size[size] do
  616. begin
  617. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  618. NextSrcDst;
  619. end;
  620. end;
  621. else
  622. internalerror(2011022004);
  623. end;
  624. end;
  625. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  626. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  627. var
  628. mask : qword;
  629. shift : byte;
  630. i : byte;
  631. tmpreg : tregister;
  632. tmpreg64 : tregister64;
  633. procedure NextReg;
  634. begin
  635. if i=5 then
  636. reg:=reghi
  637. else
  638. reg:=GetNextReg(reg);
  639. end;
  640. var
  641. curvalue : byte;
  642. begin
  643. mask:=$ff;
  644. shift:=0;
  645. case op of
  646. OP_OR:
  647. begin
  648. for i:=1 to tcgsize2size[size] do
  649. begin
  650. list.concat(taicpu.op_reg_const(A_ORI,reg,(qword(a) and mask) shr shift));
  651. NextReg;
  652. mask:=mask shl 8;
  653. inc(shift,8);
  654. end;
  655. end;
  656. OP_AND:
  657. begin
  658. for i:=1 to tcgsize2size[size] do
  659. begin
  660. list.concat(taicpu.op_reg_const(A_ANDI,reg,(qword(a) and mask) shr shift));
  661. NextReg;
  662. mask:=mask shl 8;
  663. inc(shift,8);
  664. end;
  665. end;
  666. OP_SUB:
  667. begin
  668. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  669. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  670. begin
  671. for i:=2 to tcgsize2size[size] do
  672. begin
  673. NextReg;
  674. mask:=mask shl 8;
  675. inc(shift,8);
  676. curvalue:=(qword(a) and mask) shr shift;
  677. { decrease pressure on upper half of registers by using SBC ...,R1 instead
  678. of SBCI ...,0 }
  679. if curvalue=0 then
  680. list.concat(taicpu.op_reg_reg(A_SBC,reg,NR_R1))
  681. else
  682. list.concat(taicpu.op_reg_const(A_SBCI,reg,curvalue));
  683. end;
  684. end;
  685. end;
  686. OP_ADD:
  687. begin
  688. curvalue:=a and mask;
  689. if curvalue=0 then
  690. list.concat(taicpu.op_reg_reg(A_ADD,reg,NR_R1))
  691. else
  692. begin
  693. tmpreg:=getintregister(list,OS_8);
  694. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  695. list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
  696. end;
  697. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  698. begin
  699. for i:=2 to tcgsize2size[size] do
  700. begin
  701. NextReg;
  702. mask:=mask shl 8;
  703. inc(shift,8);
  704. curvalue:=(qword(a) and mask) shr shift;
  705. { decrease pressure on upper half of registers by using ADC ...,R1 instead
  706. of ADD ...,0 }
  707. if curvalue=0 then
  708. list.concat(taicpu.op_reg_reg(A_ADC,reg,NR_R1))
  709. else
  710. begin
  711. tmpreg:=getintregister(list,OS_8);
  712. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  713. list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
  714. end;
  715. end;
  716. end;
  717. end;
  718. else
  719. begin
  720. if size in [OS_64,OS_S64] then
  721. begin
  722. tmpreg64.reglo:=getintregister(list,OS_32);
  723. tmpreg64.reghi:=getintregister(list,OS_32);
  724. cg64.a_load64_const_reg(list,a,tmpreg64);
  725. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  726. end
  727. else
  728. begin
  729. {$if 0}
  730. { code not working yet }
  731. if (op=OP_SAR) and (a=31) and (size in [OS_32,OS_S32]) then
  732. begin
  733. tmpreg:=reg;
  734. for i:=1 to 4 do
  735. begin
  736. list.concat(taicpu.op_reg_reg(A_MOV,tmpreg,NR_R1));
  737. tmpreg:=GetNextReg(tmpreg);
  738. end;
  739. end
  740. else
  741. {$endif}
  742. begin
  743. tmpreg:=getintregister(list,size);
  744. a_load_const_reg(list,size,a,tmpreg);
  745. a_op_reg_reg(list,op,size,tmpreg,reg);
  746. end;
  747. end;
  748. end;
  749. end;
  750. end;
  751. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  752. var
  753. mask : qword;
  754. shift : byte;
  755. i : byte;
  756. begin
  757. mask:=$ff;
  758. shift:=0;
  759. for i:=1 to tcgsize2size[size] do
  760. begin
  761. if ((qword(a) and mask) shr shift)=0 then
  762. emit_mov(list,reg,NR_R1)
  763. else
  764. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  765. mask:=mask shl 8;
  766. inc(shift,8);
  767. reg:=GetNextReg(reg);
  768. end;
  769. end;
  770. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  771. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  772. begin
  773. { allocate the register only, if a cpu register is passed }
  774. if getsupreg(reg)<first_int_imreg then
  775. getcpuregister(list,reg);
  776. end;
  777. var
  778. tmpref : treference;
  779. l : tasmlabel;
  780. begin
  781. Result:=ref;
  782. if ref.addressmode<>AM_UNCHANGED then
  783. internalerror(2011021701);
  784. { Be sure to have a base register }
  785. if (ref.base=NR_NO) then
  786. begin
  787. { only symbol+offset? }
  788. if ref.index=NR_NO then
  789. exit;
  790. ref.base:=ref.index;
  791. ref.index:=NR_NO;
  792. end;
  793. if assigned(ref.symbol) or (ref.offset<>0) then
  794. begin
  795. reference_reset(tmpref,0);
  796. tmpref.symbol:=ref.symbol;
  797. tmpref.offset:=ref.offset;
  798. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  799. tmpref.refaddr:=addr_lo8_gs
  800. else
  801. tmpref.refaddr:=addr_lo8;
  802. maybegetcpuregister(list,tmpreg);
  803. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  804. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  805. tmpref.refaddr:=addr_hi8_gs
  806. else
  807. tmpref.refaddr:=addr_hi8;
  808. maybegetcpuregister(list,GetNextReg(tmpreg));
  809. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  810. if (ref.base<>NR_NO) then
  811. begin
  812. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  813. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  814. end;
  815. if (ref.index<>NR_NO) then
  816. begin
  817. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  818. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  819. end;
  820. ref.symbol:=nil;
  821. ref.offset:=0;
  822. ref.base:=tmpreg;
  823. ref.index:=NR_NO;
  824. end
  825. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  826. begin
  827. maybegetcpuregister(list,tmpreg);
  828. emit_mov(list,tmpreg,ref.base);
  829. maybegetcpuregister(list,GetNextReg(tmpreg));
  830. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  831. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  832. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  833. ref.base:=tmpreg;
  834. ref.index:=NR_NO;
  835. end
  836. else if (ref.base<>NR_NO) then
  837. begin
  838. maybegetcpuregister(list,tmpreg);
  839. emit_mov(list,tmpreg,ref.base);
  840. maybegetcpuregister(list,GetNextReg(tmpreg));
  841. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  842. ref.base:=tmpreg;
  843. ref.index:=NR_NO;
  844. end
  845. else if (ref.index<>NR_NO) then
  846. begin
  847. maybegetcpuregister(list,tmpreg);
  848. emit_mov(list,tmpreg,ref.index);
  849. maybegetcpuregister(list,GetNextReg(tmpreg));
  850. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  851. ref.base:=tmpreg;
  852. ref.index:=NR_NO;
  853. end;
  854. Result:=ref;
  855. end;
  856. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  857. var
  858. href : treference;
  859. conv_done: boolean;
  860. tmpreg : tregister;
  861. i : integer;
  862. QuickRef : Boolean;
  863. begin
  864. QuickRef:=false;
  865. if not((Ref.addressmode=AM_UNCHANGED) and
  866. (Ref.symbol=nil) and
  867. ((Ref.base=NR_R28) or
  868. (Ref.base=NR_R29)) and
  869. (Ref.Index=NR_No) and
  870. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  871. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  872. href:=normalize_ref(list,Ref,NR_R30)
  873. else
  874. begin
  875. QuickRef:=true;
  876. href:=Ref;
  877. end;
  878. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  879. internalerror(2011021307);
  880. conv_done:=false;
  881. if tosize<>fromsize then
  882. begin
  883. conv_done:=true;
  884. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  885. fromsize:=tosize;
  886. case fromsize of
  887. OS_8:
  888. begin
  889. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  890. href.addressmode:=AM_POSTINCREMENT;
  891. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  892. for i:=2 to tcgsize2size[tosize] do
  893. begin
  894. if QuickRef then
  895. inc(href.offset);
  896. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  897. href.addressmode:=AM_POSTINCREMENT
  898. else
  899. href.addressmode:=AM_UNCHANGED;
  900. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  901. end;
  902. end;
  903. OS_S8:
  904. begin
  905. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  906. href.addressmode:=AM_POSTINCREMENT;
  907. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  908. if tcgsize2size[tosize]>1 then
  909. begin
  910. tmpreg:=getintregister(list,OS_8);
  911. emit_mov(list,tmpreg,NR_R1);
  912. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  913. list.concat(taicpu.op_reg(A_COM,tmpreg));
  914. for i:=2 to tcgsize2size[tosize] do
  915. begin
  916. if QuickRef then
  917. inc(href.offset);
  918. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  919. href.addressmode:=AM_POSTINCREMENT
  920. else
  921. href.addressmode:=AM_UNCHANGED;
  922. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  923. end;
  924. end;
  925. end;
  926. OS_16:
  927. begin
  928. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  929. href.addressmode:=AM_POSTINCREMENT;
  930. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  931. if QuickRef then
  932. inc(href.offset)
  933. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  934. href.addressmode:=AM_POSTINCREMENT
  935. else
  936. href.addressmode:=AM_UNCHANGED;
  937. reg:=GetNextReg(reg);
  938. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  939. for i:=3 to tcgsize2size[tosize] do
  940. begin
  941. if QuickRef then
  942. inc(href.offset);
  943. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  944. href.addressmode:=AM_POSTINCREMENT
  945. else
  946. href.addressmode:=AM_UNCHANGED;
  947. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  948. end;
  949. end;
  950. OS_S16:
  951. begin
  952. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  953. href.addressmode:=AM_POSTINCREMENT;
  954. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  955. if QuickRef then
  956. inc(href.offset)
  957. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  958. href.addressmode:=AM_POSTINCREMENT
  959. else
  960. href.addressmode:=AM_UNCHANGED;
  961. reg:=GetNextReg(reg);
  962. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  963. if tcgsize2size[tosize]>2 then
  964. begin
  965. tmpreg:=getintregister(list,OS_8);
  966. emit_mov(list,tmpreg,NR_R1);
  967. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  968. list.concat(taicpu.op_reg(A_COM,tmpreg));
  969. for i:=3 to tcgsize2size[tosize] do
  970. begin
  971. if QuickRef then
  972. inc(href.offset);
  973. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  974. href.addressmode:=AM_POSTINCREMENT
  975. else
  976. href.addressmode:=AM_UNCHANGED;
  977. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  978. end;
  979. end;
  980. end;
  981. else
  982. conv_done:=false;
  983. end;
  984. end;
  985. if not conv_done then
  986. begin
  987. for i:=1 to tcgsize2size[fromsize] do
  988. begin
  989. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  990. href.addressmode:=AM_POSTINCREMENT
  991. else
  992. href.addressmode:=AM_UNCHANGED;
  993. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  994. if QuickRef then
  995. inc(href.offset);
  996. reg:=GetNextReg(reg);
  997. end;
  998. end;
  999. if not(QuickRef) then
  1000. begin
  1001. ungetcpuregister(list,href.base);
  1002. ungetcpuregister(list,GetNextReg(href.base));
  1003. end;
  1004. end;
  1005. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  1006. const Ref : treference;reg : tregister);
  1007. var
  1008. href : treference;
  1009. conv_done: boolean;
  1010. tmpreg : tregister;
  1011. i : integer;
  1012. QuickRef : boolean;
  1013. begin
  1014. QuickRef:=false;
  1015. if not((Ref.addressmode=AM_UNCHANGED) and
  1016. (Ref.symbol=nil) and
  1017. ((Ref.base=NR_R28) or
  1018. (Ref.base=NR_R29)) and
  1019. (Ref.Index=NR_No) and
  1020. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  1021. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  1022. href:=normalize_ref(list,Ref,NR_R30)
  1023. else
  1024. begin
  1025. QuickRef:=true;
  1026. href:=Ref;
  1027. end;
  1028. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1029. internalerror(2011021307);
  1030. conv_done:=false;
  1031. if tosize<>fromsize then
  1032. begin
  1033. conv_done:=true;
  1034. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1035. fromsize:=tosize;
  1036. case fromsize of
  1037. OS_8:
  1038. begin
  1039. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1040. for i:=2 to tcgsize2size[tosize] do
  1041. begin
  1042. reg:=GetNextReg(reg);
  1043. emit_mov(list,reg,NR_R1);
  1044. end;
  1045. end;
  1046. OS_S8:
  1047. begin
  1048. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1049. tmpreg:=reg;
  1050. if tcgsize2size[tosize]>1 then
  1051. begin
  1052. reg:=GetNextReg(reg);
  1053. emit_mov(list,reg,NR_R1);
  1054. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1055. list.concat(taicpu.op_reg(A_COM,reg));
  1056. tmpreg:=reg;
  1057. for i:=3 to tcgsize2size[tosize] do
  1058. begin
  1059. reg:=GetNextReg(reg);
  1060. emit_mov(list,reg,tmpreg);
  1061. end;
  1062. end;
  1063. end;
  1064. OS_16:
  1065. begin
  1066. if not(QuickRef) then
  1067. href.addressmode:=AM_POSTINCREMENT;
  1068. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1069. if QuickRef then
  1070. inc(href.offset);
  1071. href.addressmode:=AM_UNCHANGED;
  1072. reg:=GetNextReg(reg);
  1073. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1074. for i:=3 to tcgsize2size[tosize] do
  1075. begin
  1076. reg:=GetNextReg(reg);
  1077. emit_mov(list,reg,NR_R1);
  1078. end;
  1079. end;
  1080. OS_S16:
  1081. begin
  1082. if not(QuickRef) then
  1083. href.addressmode:=AM_POSTINCREMENT;
  1084. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1085. if QuickRef then
  1086. inc(href.offset);
  1087. href.addressmode:=AM_UNCHANGED;
  1088. reg:=GetNextReg(reg);
  1089. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1090. tmpreg:=reg;
  1091. reg:=GetNextReg(reg);
  1092. emit_mov(list,reg,NR_R1);
  1093. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1094. list.concat(taicpu.op_reg(A_COM,reg));
  1095. tmpreg:=reg;
  1096. for i:=4 to tcgsize2size[tosize] do
  1097. begin
  1098. reg:=GetNextReg(reg);
  1099. emit_mov(list,reg,tmpreg);
  1100. end;
  1101. end;
  1102. else
  1103. conv_done:=false;
  1104. end;
  1105. end;
  1106. if not conv_done then
  1107. begin
  1108. for i:=1 to tcgsize2size[fromsize] do
  1109. begin
  1110. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1111. href.addressmode:=AM_POSTINCREMENT
  1112. else
  1113. href.addressmode:=AM_UNCHANGED;
  1114. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1115. if QuickRef then
  1116. inc(href.offset);
  1117. reg:=GetNextReg(reg);
  1118. end;
  1119. end;
  1120. if not(QuickRef) then
  1121. begin
  1122. ungetcpuregister(list,href.base);
  1123. ungetcpuregister(list,GetNextReg(href.base));
  1124. end;
  1125. end;
  1126. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1127. var
  1128. conv_done: boolean;
  1129. tmpreg : tregister;
  1130. i : integer;
  1131. begin
  1132. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1133. internalerror(2011021310);
  1134. conv_done:=false;
  1135. if tosize<>fromsize then
  1136. begin
  1137. conv_done:=true;
  1138. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1139. fromsize:=tosize;
  1140. case fromsize of
  1141. OS_8:
  1142. begin
  1143. emit_mov(list,reg2,reg1);
  1144. for i:=2 to tcgsize2size[tosize] do
  1145. begin
  1146. reg2:=GetNextReg(reg2);
  1147. emit_mov(list,reg2,NR_R1);
  1148. end;
  1149. end;
  1150. OS_S8:
  1151. begin
  1152. emit_mov(list,reg2,reg1);
  1153. if tcgsize2size[tosize]>1 then
  1154. begin
  1155. reg2:=GetNextReg(reg2);
  1156. emit_mov(list,reg2,NR_R1);
  1157. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1158. list.concat(taicpu.op_reg(A_COM,reg2));
  1159. tmpreg:=reg2;
  1160. for i:=3 to tcgsize2size[tosize] do
  1161. begin
  1162. reg2:=GetNextReg(reg2);
  1163. emit_mov(list,reg2,tmpreg);
  1164. end;
  1165. end;
  1166. end;
  1167. OS_16:
  1168. begin
  1169. emit_mov(list,reg2,reg1);
  1170. reg1:=GetNextReg(reg1);
  1171. reg2:=GetNextReg(reg2);
  1172. emit_mov(list,reg2,reg1);
  1173. for i:=3 to tcgsize2size[tosize] do
  1174. begin
  1175. reg2:=GetNextReg(reg2);
  1176. emit_mov(list,reg2,NR_R1);
  1177. end;
  1178. end;
  1179. OS_S16:
  1180. begin
  1181. emit_mov(list,reg2,reg1);
  1182. reg1:=GetNextReg(reg1);
  1183. reg2:=GetNextReg(reg2);
  1184. emit_mov(list,reg2,reg1);
  1185. if tcgsize2size[tosize]>2 then
  1186. begin
  1187. reg2:=GetNextReg(reg2);
  1188. emit_mov(list,reg2,NR_R1);
  1189. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1190. list.concat(taicpu.op_reg(A_COM,reg2));
  1191. tmpreg:=reg2;
  1192. for i:=4 to tcgsize2size[tosize] do
  1193. begin
  1194. reg2:=GetNextReg(reg2);
  1195. emit_mov(list,reg2,tmpreg);
  1196. end;
  1197. end;
  1198. end;
  1199. else
  1200. conv_done:=false;
  1201. end;
  1202. end;
  1203. if not conv_done and (reg1<>reg2) then
  1204. begin
  1205. for i:=1 to tcgsize2size[fromsize] do
  1206. begin
  1207. emit_mov(list,reg2,reg1);
  1208. reg1:=GetNextReg(reg1);
  1209. reg2:=GetNextReg(reg2);
  1210. end;
  1211. end;
  1212. end;
  1213. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1214. begin
  1215. internalerror(2012010702);
  1216. end;
  1217. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1218. begin
  1219. internalerror(2012010703);
  1220. end;
  1221. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1222. begin
  1223. internalerror(2012010704);
  1224. end;
  1225. { comparison operations }
  1226. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1227. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1228. var
  1229. swapped : boolean;
  1230. tmpreg : tregister;
  1231. i : byte;
  1232. begin
  1233. if a=0 then
  1234. begin
  1235. swapped:=false;
  1236. { swap parameters? }
  1237. case cmp_op of
  1238. OC_GT:
  1239. begin
  1240. swapped:=true;
  1241. cmp_op:=OC_LT;
  1242. end;
  1243. OC_LTE:
  1244. begin
  1245. swapped:=true;
  1246. cmp_op:=OC_GTE;
  1247. end;
  1248. OC_BE:
  1249. begin
  1250. swapped:=true;
  1251. cmp_op:=OC_AE;
  1252. end;
  1253. OC_A:
  1254. begin
  1255. swapped:=true;
  1256. cmp_op:=OC_B;
  1257. end;
  1258. end;
  1259. if swapped then
  1260. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1261. else
  1262. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1263. for i:=2 to tcgsize2size[size] do
  1264. begin
  1265. reg:=GetNextReg(reg);
  1266. if swapped then
  1267. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1268. else
  1269. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1270. end;
  1271. a_jmp_cond(list,cmp_op,l);
  1272. end
  1273. else
  1274. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1275. end;
  1276. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1277. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1278. var
  1279. swapped : boolean;
  1280. tmpreg : tregister;
  1281. i : byte;
  1282. begin
  1283. swapped:=false;
  1284. { swap parameters? }
  1285. case cmp_op of
  1286. OC_GT:
  1287. begin
  1288. swapped:=true;
  1289. cmp_op:=OC_LT;
  1290. end;
  1291. OC_LTE:
  1292. begin
  1293. swapped:=true;
  1294. cmp_op:=OC_GTE;
  1295. end;
  1296. OC_BE:
  1297. begin
  1298. swapped:=true;
  1299. cmp_op:=OC_AE;
  1300. end;
  1301. OC_A:
  1302. begin
  1303. swapped:=true;
  1304. cmp_op:=OC_B;
  1305. end;
  1306. end;
  1307. if swapped then
  1308. begin
  1309. tmpreg:=reg1;
  1310. reg1:=reg2;
  1311. reg2:=tmpreg;
  1312. end;
  1313. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1314. for i:=2 to tcgsize2size[size] do
  1315. begin
  1316. reg1:=GetNextReg(reg1);
  1317. reg2:=GetNextReg(reg2);
  1318. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1319. end;
  1320. a_jmp_cond(list,cmp_op,l);
  1321. end;
  1322. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1323. var
  1324. ai : taicpu;
  1325. begin
  1326. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1327. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s))
  1328. else
  1329. ai:=taicpu.op_sym(A_RJMP,current_asmdata.RefAsmSymbol(s));
  1330. ai.is_jmp:=true;
  1331. list.concat(ai);
  1332. end;
  1333. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1334. var
  1335. ai : taicpu;
  1336. begin
  1337. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1338. ai:=taicpu.op_sym(A_JMP,l)
  1339. else
  1340. ai:=taicpu.op_sym(A_RJMP,l);
  1341. ai.is_jmp:=true;
  1342. list.concat(ai);
  1343. end;
  1344. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1345. var
  1346. ai : taicpu;
  1347. begin
  1348. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1349. ai.is_jmp:=true;
  1350. list.concat(ai);
  1351. end;
  1352. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1353. var
  1354. l : TAsmLabel;
  1355. tmpflags : TResFlags;
  1356. begin
  1357. current_asmdata.getjumplabel(l);
  1358. {
  1359. if flags_to_cond(f) then
  1360. begin
  1361. tmpflags:=f;
  1362. inverse_flags(tmpflags);
  1363. emit_mov(reg,NR_R1);
  1364. a_jmp_flags(list,tmpflags,l);
  1365. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1366. end
  1367. else
  1368. }
  1369. begin
  1370. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1371. a_jmp_flags(list,f,l);
  1372. emit_mov(list,reg,NR_R1);
  1373. end;
  1374. cg.a_label(list,l);
  1375. end;
  1376. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1377. var
  1378. i : integer;
  1379. begin
  1380. case value of
  1381. 0:
  1382. ;
  1383. {-14..-1:
  1384. begin
  1385. if ((-value) mod 2)<>0 then
  1386. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1387. for i:=1 to (-value) div 2 do
  1388. list.concat(taicpu.op_const(A_RCALL,0));
  1389. end;
  1390. 1..7:
  1391. begin
  1392. for i:=1 to value do
  1393. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1394. end;}
  1395. else
  1396. begin
  1397. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1398. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1399. // get SREG
  1400. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1401. // block interrupts
  1402. list.concat(taicpu.op_none(A_CLI));
  1403. // write high SP
  1404. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1405. // release interrupts
  1406. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1407. // write low SP
  1408. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1409. end;
  1410. end;
  1411. end;
  1412. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1413. begin
  1414. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1415. result:=A_LDS
  1416. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1417. result:=A_LDD
  1418. else
  1419. result:=A_LD;
  1420. end;
  1421. function tcgavr.GetStore(const ref: treference) : tasmop;
  1422. begin
  1423. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1424. result:=A_STS
  1425. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1426. result:=A_STD
  1427. else
  1428. result:=A_ST;
  1429. end;
  1430. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1431. var
  1432. regs : tcpuregisterset;
  1433. reg : tsuperregister;
  1434. begin
  1435. if not(nostackframe) then
  1436. begin
  1437. { save int registers,
  1438. but only if the procedure returns }
  1439. if not(po_noreturn in current_procinfo.procdef.procoptions) then
  1440. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall)
  1441. else
  1442. regs:=[];
  1443. { if the framepointer is potentially used, save it always because we need a proper stack frame,
  1444. even if the procedure never returns, the procedure could be e.g. a nested one accessing
  1445. an outer stackframe }
  1446. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1447. regs:=regs+[RS_R28,RS_R29];
  1448. for reg:=RS_R31 downto RS_R0 do
  1449. if reg in regs then
  1450. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1451. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1452. begin
  1453. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1454. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1455. end
  1456. else
  1457. { the framepointer cannot be omitted on avr because sp
  1458. is not a register but part of the i/o map
  1459. }
  1460. internalerror(2011021901);
  1461. a_adjust_sp(list,-localsize);
  1462. end;
  1463. end;
  1464. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1465. var
  1466. regs : tcpuregisterset;
  1467. reg : TSuperRegister;
  1468. LocalSize : longint;
  1469. begin
  1470. { every byte counts for avr, so if a subroutine is marked as non-returning, we do
  1471. not generate any exit code, so we really trust the noreturn directive
  1472. }
  1473. if po_noreturn in current_procinfo.procdef.procoptions then
  1474. exit;
  1475. if not(nostackframe) then
  1476. begin
  1477. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1478. begin
  1479. LocalSize:=current_procinfo.calc_stackframe_size;
  1480. a_adjust_sp(list,LocalSize);
  1481. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1482. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1483. regs:=regs+[RS_R28,RS_R29];
  1484. for reg:=RS_R0 to RS_R31 do
  1485. if reg in regs then
  1486. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1487. end
  1488. else
  1489. { the framepointer cannot be omitted on avr because sp
  1490. is not a register but part of the i/o map
  1491. }
  1492. internalerror(2011021902);
  1493. end;
  1494. list.concat(taicpu.op_none(A_RET));
  1495. end;
  1496. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1497. var
  1498. tmpref : treference;
  1499. begin
  1500. if ref.addressmode<>AM_UNCHANGED then
  1501. internalerror(2011021701);
  1502. if assigned(ref.symbol) or (ref.offset<>0) then
  1503. begin
  1504. reference_reset(tmpref,0);
  1505. tmpref.symbol:=ref.symbol;
  1506. tmpref.offset:=ref.offset;
  1507. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1508. tmpref.refaddr:=addr_lo8_gs
  1509. else
  1510. tmpref.refaddr:=addr_lo8;
  1511. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1512. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1513. tmpref.refaddr:=addr_hi8_gs
  1514. else
  1515. tmpref.refaddr:=addr_hi8;
  1516. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1517. if (ref.base<>NR_NO) then
  1518. begin
  1519. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1520. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1521. end;
  1522. if (ref.index<>NR_NO) then
  1523. begin
  1524. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1525. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1526. end;
  1527. end
  1528. else if (ref.base<>NR_NO)then
  1529. begin
  1530. emit_mov(list,r,ref.base);
  1531. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1532. if (ref.index<>NR_NO) then
  1533. begin
  1534. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1535. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1536. end;
  1537. end
  1538. else if (ref.index<>NR_NO) then
  1539. begin
  1540. emit_mov(list,r,ref.index);
  1541. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1542. end;
  1543. end;
  1544. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1545. begin
  1546. internalerror(2011021320);
  1547. end;
  1548. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1549. var
  1550. paraloc1,paraloc2,paraloc3 : TCGPara;
  1551. pd : tprocdef;
  1552. begin
  1553. pd:=search_system_proc('MOVE');
  1554. paraloc1.init;
  1555. paraloc2.init;
  1556. paraloc3.init;
  1557. paramanager.getintparaloc(list,pd,1,paraloc1);
  1558. paramanager.getintparaloc(list,pd,2,paraloc2);
  1559. paramanager.getintparaloc(list,pd,3,paraloc3);
  1560. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1561. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1562. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1563. paramanager.freecgpara(list,paraloc3);
  1564. paramanager.freecgpara(list,paraloc2);
  1565. paramanager.freecgpara(list,paraloc1);
  1566. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1567. a_call_name_static(list,'FPC_MOVE');
  1568. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1569. paraloc3.done;
  1570. paraloc2.done;
  1571. paraloc1.done;
  1572. end;
  1573. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1574. var
  1575. countreg,tmpreg : tregister;
  1576. srcref,dstref : treference;
  1577. copysize,countregsize : tcgsize;
  1578. l : TAsmLabel;
  1579. i : longint;
  1580. SrcQuickRef, DestQuickRef : Boolean;
  1581. begin
  1582. if len>16 then
  1583. begin
  1584. current_asmdata.getjumplabel(l);
  1585. reference_reset(srcref,0);
  1586. reference_reset(dstref,0);
  1587. srcref.base:=NR_R30;
  1588. srcref.addressmode:=AM_POSTINCREMENT;
  1589. dstref.base:=NR_R26;
  1590. dstref.addressmode:=AM_POSTINCREMENT;
  1591. copysize:=OS_8;
  1592. if len<256 then
  1593. countregsize:=OS_8
  1594. else if len<65536 then
  1595. countregsize:=OS_16
  1596. else
  1597. internalerror(2011022007);
  1598. countreg:=getintregister(list,countregsize);
  1599. a_load_const_reg(list,countregsize,len,countreg);
  1600. a_loadaddr_ref_reg(list,source,NR_R30);
  1601. tmpreg:=getaddressregister(list);
  1602. a_loadaddr_ref_reg(list,dest,tmpreg);
  1603. { X is used for spilling code so we can load it
  1604. only by a push/pop sequence, this can be
  1605. optimized later on by the peephole optimizer
  1606. }
  1607. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1608. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1609. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1610. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1611. cg.a_label(list,l);
  1612. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1613. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1614. list.concat(taicpu.op_reg(A_DEC,countreg));
  1615. a_jmp_flags(list,F_NE,l);
  1616. // keep registers alive
  1617. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1618. end
  1619. else
  1620. begin
  1621. SrcQuickRef:=false;
  1622. DestQuickRef:=false;
  1623. if not((source.addressmode=AM_UNCHANGED) and
  1624. (source.symbol=nil) and
  1625. ((source.base=NR_R28) or
  1626. (source.base=NR_R29)) and
  1627. (source.Index=NR_NO) and
  1628. (source.Offset in [0..64-len])) and
  1629. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1630. srcref:=normalize_ref(list,source,NR_R30)
  1631. else
  1632. begin
  1633. SrcQuickRef:=true;
  1634. srcref:=source;
  1635. end;
  1636. if not((dest.addressmode=AM_UNCHANGED) and
  1637. (dest.symbol=nil) and
  1638. ((dest.base=NR_R28) or
  1639. (dest.base=NR_R29)) and
  1640. (dest.Index=NR_No) and
  1641. (dest.Offset in [0..64-len])) and
  1642. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1643. begin
  1644. if not(SrcQuickRef) then
  1645. begin
  1646. tmpreg:=getaddressregister(list);
  1647. dstref:=normalize_ref(list,dest,tmpreg);
  1648. { X is used for spilling code so we can load it
  1649. only by a push/pop sequence, this can be
  1650. optimized later on by the peephole optimizer
  1651. }
  1652. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1653. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1654. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1655. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1656. dstref.base:=NR_R26;
  1657. end
  1658. else
  1659. dstref:=normalize_ref(list,dest,NR_R30);
  1660. end
  1661. else
  1662. begin
  1663. DestQuickRef:=true;
  1664. dstref:=dest;
  1665. end;
  1666. for i:=1 to len do
  1667. begin
  1668. if not(SrcQuickRef) and (i<len) then
  1669. srcref.addressmode:=AM_POSTINCREMENT
  1670. else
  1671. srcref.addressmode:=AM_UNCHANGED;
  1672. if not(DestQuickRef) and (i<len) then
  1673. dstref.addressmode:=AM_POSTINCREMENT
  1674. else
  1675. dstref.addressmode:=AM_UNCHANGED;
  1676. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1677. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1678. if SrcQuickRef then
  1679. inc(srcref.offset);
  1680. if DestQuickRef then
  1681. inc(dstref.offset);
  1682. end;
  1683. if not(SrcQuickRef) then
  1684. begin
  1685. ungetcpuregister(list,srcref.base);
  1686. ungetcpuregister(list,GetNextReg(srcref.base));
  1687. end;
  1688. end;
  1689. end;
  1690. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1691. var
  1692. hl : tasmlabel;
  1693. ai : taicpu;
  1694. cond : TAsmCond;
  1695. begin
  1696. if not(cs_check_overflow in current_settings.localswitches) then
  1697. exit;
  1698. current_asmdata.getjumplabel(hl);
  1699. if not ((def.typ=pointerdef) or
  1700. ((def.typ=orddef) and
  1701. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1702. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1703. cond:=C_VC
  1704. else
  1705. cond:=C_CC;
  1706. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1707. ai.SetCondition(cond);
  1708. ai.is_jmp:=true;
  1709. list.concat(ai);
  1710. a_call_name(list,'FPC_OVERFLOW',false);
  1711. a_label(list,hl);
  1712. end;
  1713. procedure tcgavr.g_save_registers(list: TAsmList);
  1714. begin
  1715. { this is done by the entry code }
  1716. end;
  1717. procedure tcgavr.g_restore_registers(list: TAsmList);
  1718. begin
  1719. { this is done by the exit code }
  1720. end;
  1721. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1722. var
  1723. ai1,ai2 : taicpu;
  1724. hl : TAsmLabel;
  1725. begin
  1726. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1727. ai1.is_jmp:=true;
  1728. hl:=nil;
  1729. case cond of
  1730. OC_EQ:
  1731. ai1.SetCondition(C_EQ);
  1732. OC_GT:
  1733. begin
  1734. { emulate GT }
  1735. current_asmdata.getjumplabel(hl);
  1736. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1737. ai2.SetCondition(C_EQ);
  1738. ai2.is_jmp:=true;
  1739. list.concat(ai2);
  1740. ai1.SetCondition(C_GE);
  1741. end;
  1742. OC_LT:
  1743. ai1.SetCondition(C_LT);
  1744. OC_GTE:
  1745. ai1.SetCondition(C_GE);
  1746. OC_LTE:
  1747. begin
  1748. { emulate LTE }
  1749. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1750. ai2.SetCondition(C_EQ);
  1751. ai2.is_jmp:=true;
  1752. list.concat(ai2);
  1753. ai1.SetCondition(C_LT);
  1754. end;
  1755. OC_NE:
  1756. ai1.SetCondition(C_NE);
  1757. OC_BE:
  1758. begin
  1759. { emulate BE }
  1760. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1761. ai2.SetCondition(C_EQ);
  1762. ai2.is_jmp:=true;
  1763. list.concat(ai2);
  1764. ai1.SetCondition(C_LO);
  1765. end;
  1766. OC_B:
  1767. ai1.SetCondition(C_LO);
  1768. OC_AE:
  1769. ai1.SetCondition(C_SH);
  1770. OC_A:
  1771. begin
  1772. { emulate A (unsigned GT) }
  1773. current_asmdata.getjumplabel(hl);
  1774. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1775. ai2.SetCondition(C_EQ);
  1776. ai2.is_jmp:=true;
  1777. list.concat(ai2);
  1778. ai1.SetCondition(C_SH);
  1779. end;
  1780. else
  1781. internalerror(2011082501);
  1782. end;
  1783. list.concat(ai1);
  1784. if assigned(hl) then
  1785. a_label(list,hl);
  1786. end;
  1787. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1788. var
  1789. instr: taicpu;
  1790. begin
  1791. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1792. list.Concat(instr);
  1793. { Notify the register allocator that we have written a move instruction so
  1794. it can try to eliminate it. }
  1795. add_move_instruction(instr);
  1796. end;
  1797. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1798. begin
  1799. if not(size in [OS_S64,OS_64]) then
  1800. internalerror(2012102402);
  1801. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1802. end;
  1803. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1804. begin
  1805. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1806. end;
  1807. procedure create_codegen;
  1808. begin
  1809. cg:=tcgavr.create;
  1810. cg64:=tcg64favr.create;
  1811. end;
  1812. end.