cpuinfo.pas 27 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv5te,
  31. cpu_armv5tej,
  32. cpu_armv6,
  33. cpu_armv6k,
  34. cpu_armv6t2,
  35. cpu_armv6z,
  36. cpu_armv7,
  37. cpu_armv7a,
  38. cpu_armv7r,
  39. cpu_armv7m,
  40. cpu_armv7em
  41. );
  42. Const
  43. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  44. cpu_thumb = [];
  45. cpu_thumb2 = [cpu_armv7m];
  46. Type
  47. tfputype =
  48. (fpu_none,
  49. fpu_soft,
  50. fpu_libgcc,
  51. fpu_fpa,
  52. fpu_fpa10,
  53. fpu_fpa11,
  54. fpu_vfpv2,
  55. fpu_vfpv3,
  56. fpu_vfpv3_d16
  57. );
  58. tcontrollertype =
  59. (ct_none,
  60. { Phillips }
  61. ct_lpc2114,
  62. ct_lpc2124,
  63. ct_lpc2194,
  64. ct_lpc1754,
  65. ct_lpc1756,
  66. ct_lpc1758,
  67. ct_lpc1764,
  68. ct_lpc1766,
  69. ct_lpc1768,
  70. { ATMEL }
  71. ct_at91sam7s256,
  72. ct_at91sam7se256,
  73. ct_at91sam7x256,
  74. ct_at91sam7xc256,
  75. { STMicroelectronics }
  76. ct_stm32f103rb,
  77. ct_stm32f103re,
  78. ct_stm32f103c4t,
  79. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  80. ct_lm3s1110,
  81. ct_lm3s1133,
  82. ct_lm3s1138,
  83. ct_lm3s1150,
  84. ct_lm3s1162,
  85. ct_lm3s1165,
  86. ct_lm3s1166,
  87. ct_lm3s2110,
  88. ct_lm3s2139,
  89. ct_lm3s6100,
  90. ct_lm3s6110,
  91. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  92. ct_lm3s1601,
  93. ct_lm3s1608,
  94. ct_lm3s1620,
  95. ct_lm3s1635,
  96. ct_lm3s1636,
  97. ct_lm3s1637,
  98. ct_lm3s1651,
  99. ct_lm3s2601,
  100. ct_lm3s2608,
  101. ct_lm3s2620,
  102. ct_lm3s2637,
  103. ct_lm3s2651,
  104. ct_lm3s6610,
  105. ct_lm3s6611,
  106. ct_lm3s6618,
  107. ct_lm3s6633,
  108. ct_lm3s6637,
  109. ct_lm3s8630,
  110. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  111. ct_lm3s1911,
  112. ct_lm3s1918,
  113. ct_lm3s1937,
  114. ct_lm3s1958,
  115. ct_lm3s1960,
  116. ct_lm3s1968,
  117. ct_lm3s1969,
  118. ct_lm3s2911,
  119. ct_lm3s2918,
  120. ct_lm3s2919,
  121. ct_lm3s2939,
  122. ct_lm3s2948,
  123. ct_lm3s2950,
  124. ct_lm3s2965,
  125. ct_lm3s6911,
  126. ct_lm3s6918,
  127. ct_lm3s6938,
  128. ct_lm3s6950,
  129. ct_lm3s6952,
  130. ct_lm3s6965,
  131. ct_lm3s8930,
  132. ct_lm3s8933,
  133. ct_lm3s8938,
  134. ct_lm3s8962,
  135. ct_lm3s8970,
  136. ct_lm3s8971,
  137. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  138. ct_lm3s5951,
  139. ct_lm3s5956,
  140. ct_lm3s1b21,
  141. ct_lm3s2b93,
  142. ct_lm3s5b91,
  143. ct_lm3s9b81,
  144. ct_lm3s9b90,
  145. ct_lm3s9b92,
  146. ct_lm3s9b95,
  147. ct_lm3s9b96,
  148. { SAMSUNG }
  149. ct_sc32442b,
  150. // generic Thumb2 target
  151. ct_thumb2bare
  152. );
  153. Const
  154. {# Size of native extended floating point type }
  155. extended_size = 12;
  156. {# Size of a multimedia register }
  157. mmreg_size = 16;
  158. { target cpu string (used by compiler options) }
  159. target_cpu_string = 'arm';
  160. { calling conventions supported by the code generator }
  161. supported_calling_conventions : tproccalloptions = [
  162. pocall_internproc,
  163. pocall_safecall,
  164. pocall_stdcall,
  165. { same as stdcall only different name mangling }
  166. pocall_cdecl,
  167. { same as stdcall only different name mangling }
  168. pocall_cppdecl,
  169. { same as stdcall but floating point numbers are handled like equal sized integers }
  170. pocall_softfloat,
  171. { same as stdcall (requires that all const records are passed by
  172. reference, but that's already done for stdcall) }
  173. pocall_mwpascal,
  174. { used for interrupt handling }
  175. pocall_interrupt
  176. ];
  177. cputypestr : array[tcputype] of string[8] = ('',
  178. 'ARMV3',
  179. 'ARMV4',
  180. 'ARMV4T',
  181. 'ARMV5',
  182. 'ARMV5T',
  183. 'ARMV5TE',
  184. 'ARMV5TEJ',
  185. 'ARMV6',
  186. 'ARMV6K',
  187. 'ARMV6T2',
  188. 'ARMV6Z',
  189. 'ARMV7',
  190. 'ARMV7A',
  191. 'ARMV7R',
  192. 'ARMV7M',
  193. 'ARMV7EM'
  194. );
  195. fputypestr : array[tfputype] of string[9] = ('',
  196. 'SOFT',
  197. 'LIBGCC',
  198. 'FPA',
  199. 'FPA10',
  200. 'FPA11',
  201. 'VFPV2',
  202. 'VFPV3',
  203. 'VFPV3_D16'
  204. );
  205. { We know that there are fields after sramsize
  206. but we don't care about this warning }
  207. {$WARN 3177 OFF}
  208. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  209. ((
  210. controllertypestr:'';
  211. controllerunitstr:'';
  212. flashbase:0;
  213. flashsize:0;
  214. srambase:0;
  215. sramsize:0
  216. ),
  217. (
  218. controllertypestr:'LPC2114';
  219. controllerunitstr:'LPC21x4';
  220. flashbase:$00000000;
  221. flashsize:$00040000;
  222. srambase:$40000000;
  223. sramsize:$00004000
  224. ),
  225. (
  226. controllertypestr:'LPC2124';
  227. controllerunitstr:'LPC21x4';
  228. flashbase:$00000000;
  229. flashsize:$00040000;
  230. srambase:$40000000;
  231. sramsize:$00004000
  232. ),
  233. (
  234. controllertypestr:'LPC2194';
  235. controllerunitstr:'LPC21x4';
  236. flashbase:$00000000;
  237. flashsize:$00040000;
  238. srambase:$40000000;
  239. sramsize:$00004000
  240. ),
  241. (
  242. controllertypestr:'LPC1754';
  243. controllerunitstr:'LPC1754';
  244. flashbase:$00000000;
  245. flashsize:$00020000;
  246. srambase:$10000000;
  247. sramsize:$00004000
  248. ),
  249. (
  250. controllertypestr:'LPC1756';
  251. controllerunitstr:'LPC1756';
  252. flashbase:$00000000;
  253. flashsize:$00040000;
  254. srambase:$10000000;
  255. sramsize:$00004000
  256. ),
  257. (
  258. controllertypestr:'LPC1758';
  259. controllerunitstr:'LPC1758';
  260. flashbase:$00000000;
  261. flashsize:$00080000;
  262. srambase:$10000000;
  263. sramsize:$00008000
  264. ),
  265. (
  266. controllertypestr:'LPC1764';
  267. controllerunitstr:'LPC1764';
  268. flashbase:$00000000;
  269. flashsize:$00020000;
  270. srambase:$10000000;
  271. sramsize:$00004000
  272. ),
  273. (
  274. controllertypestr:'LPC1766';
  275. controllerunitstr:'LPC1766';
  276. flashbase:$00000000;
  277. flashsize:$00040000;
  278. srambase:$10000000;
  279. sramsize:$00008000
  280. ),
  281. (
  282. controllertypestr:'LPC1768';
  283. controllerunitstr:'LPC1768';
  284. flashbase:$00000000;
  285. flashsize:$00080000;
  286. srambase:$10000000;
  287. sramsize:$00008000
  288. ),
  289. (
  290. controllertypestr:'AT91SAM7S256';
  291. controllerunitstr:'AT91SAM7x256';
  292. flashbase:$00000000;
  293. flashsize:$00040000;
  294. srambase:$00200000;
  295. sramsize:$00010000
  296. ),
  297. (
  298. controllertypestr:'AT91SAM7SE256';
  299. controllerunitstr:'AT91SAM7x256';
  300. flashbase:$00000000;
  301. flashsize:$00040000;
  302. srambase:$00200000;
  303. sramsize:$00010000
  304. ),
  305. (
  306. controllertypestr:'AT91SAM7X256';
  307. controllerunitstr:'AT91SAM7x256';
  308. flashbase:$00000000;
  309. flashsize:$00040000;
  310. srambase:$00200000;
  311. sramsize:$00010000
  312. ),
  313. (
  314. controllertypestr:'AT91SAM7XC256';
  315. controllerunitstr:'AT91SAM7x256';
  316. flashbase:$00000000;
  317. flashsize:$00040000;
  318. srambase:$00200000;
  319. sramsize:$00010000
  320. ),
  321. // ct_stm32f103rb,
  322. (
  323. controllertypestr:'STM32F103RB';
  324. controllerunitstr:'STM32F10X_MD';
  325. flashbase:$08000000;
  326. flashsize:$00020000;
  327. srambase:$20000000;
  328. sramsize:$00005000
  329. ),
  330. // ct_stm32f103re,
  331. (
  332. controllertypestr:'STM32F103RE';
  333. controllerunitstr:'STM32F10X_HD';
  334. flashbase:$08000000;
  335. flashsize:$00080000;
  336. srambase:$20000000;
  337. sramsize:$00010000
  338. ),
  339. // ct_stm32f103c4t,
  340. (
  341. controllertypestr:'STM32F103C4T';
  342. controllerunitstr:'STM32F10X_LD';
  343. flashbase:$08000000;
  344. flashsize:$00004000;
  345. srambase:$20000000;
  346. sramsize:$00001800
  347. ),
  348. { TI - 64 K Flash, 16 K SRAM Devices }
  349. // ct_lm3s1110,
  350. (
  351. controllertypestr:'LM3S1110';
  352. controllerunitstr:'LM3FURY';
  353. flashbase:$00000000;
  354. flashsize:$00010000;
  355. srambase:$20000000;
  356. sramsize:$00004000
  357. ),
  358. // ct_lm3s1133,
  359. (
  360. controllertypestr:'LM3S1133';
  361. controllerunitstr:'LM3FURY';
  362. flashbase:$00000000;
  363. flashsize:$00010000;
  364. srambase:$20000000;
  365. sramsize:$00004000
  366. ),
  367. // ct_lm3s1138,
  368. (
  369. controllertypestr:'LM3S1138';
  370. controllerunitstr:'LM3FURY';
  371. flashbase:$00000000;
  372. flashsize:$00010000;
  373. srambase:$20000000;
  374. sramsize:$00004000
  375. ),
  376. // ct_lm3s1150,
  377. (
  378. controllertypestr:'LM3S1150';
  379. controllerunitstr:'LM3FURY';
  380. flashbase:$00000000;
  381. flashsize:$00010000;
  382. srambase:$20000000;
  383. sramsize:$00004000
  384. ),
  385. // ct_lm3s1162,
  386. (
  387. controllertypestr:'LM3S1162';
  388. controllerunitstr:'LM3FURY';
  389. flashbase:$00000000;
  390. flashsize:$00010000;
  391. srambase:$20000000;
  392. sramsize:$00004000
  393. ),
  394. // ct_lm3s1165,
  395. (
  396. controllertypestr:'LM3S1165';
  397. controllerunitstr:'LM3FURY';
  398. flashbase:$00000000;
  399. flashsize:$00010000;
  400. srambase:$20000000;
  401. sramsize:$00004000
  402. ),
  403. // ct_lm3s1166,
  404. (
  405. controllertypestr:'LM3S1166';
  406. controllerunitstr:'LM3FURY';
  407. flashbase:$00000000;
  408. flashsize:$00010000;
  409. srambase:$20000000;
  410. sramsize:$00004000
  411. ),
  412. // ct_lm3s2110,
  413. (
  414. controllertypestr:'LM3S2110';
  415. controllerunitstr:'LM3FURY';
  416. flashbase:$00000000;
  417. flashsize:$00010000;
  418. srambase:$20000000;
  419. sramsize:$00004000
  420. ),
  421. // ct_lm3s2139,
  422. (
  423. controllertypestr:'LM3S2139';
  424. controllerunitstr:'LM3FURY';
  425. flashbase:$00000000;
  426. flashsize:$00010000;
  427. srambase:$20000000;
  428. sramsize:$00004000
  429. ),
  430. // ct_lm3s6100,
  431. (
  432. controllertypestr:'LM3S6100';
  433. controllerunitstr:'LM3FURY';
  434. flashbase:$00000000;
  435. flashsize:$00010000;
  436. srambase:$20000000;
  437. sramsize:$00004000
  438. ),
  439. // ct_lm3s6110,
  440. (
  441. controllertypestr:'LM3S6110';
  442. controllerunitstr:'LM3FURY';
  443. flashbase:$00000000;
  444. flashsize:$00010000;
  445. srambase:$20000000;
  446. sramsize:$00004000
  447. ),
  448. { TI - 128K Flash, 32K SRAM devices }
  449. // ct_lm3s1601,
  450. (
  451. controllertypestr:'LM3S1601';
  452. controllerunitstr:'LM3FURY';
  453. flashbase:$00000000;
  454. flashsize:$00020000;
  455. srambase:$20000000;
  456. sramsize:$00008000
  457. ),
  458. // ct_lm3s1608,
  459. (
  460. controllertypestr:'LM3S1608';
  461. controllerunitstr:'LM3FURY';
  462. flashbase:$00000000;
  463. flashsize:$00020000;
  464. srambase:$20000000;
  465. sramsize:$00008000
  466. ),
  467. // ct_lm3s1620,
  468. (
  469. controllertypestr:'LM3S1620';
  470. controllerunitstr:'LM3FURY';
  471. flashbase:$00000000;
  472. flashsize:$00020000;
  473. srambase:$20000000;
  474. sramsize:$00008000
  475. ),
  476. // ct_lm3s1635,
  477. (
  478. controllertypestr:'LM3S1635';
  479. controllerunitstr:'LM3FURY';
  480. flashbase:$00000000;
  481. flashsize:$00020000;
  482. srambase:$20000000;
  483. sramsize:$00008000
  484. ),
  485. // ct_lm3s1636,
  486. (
  487. controllertypestr:'LM3S1636';
  488. controllerunitstr:'LM3FURY';
  489. flashbase:$00000000;
  490. flashsize:$00020000;
  491. srambase:$20000000;
  492. sramsize:$00008000
  493. ),
  494. // ct_lm3s1637,
  495. (
  496. controllertypestr:'LM3S1637';
  497. controllerunitstr:'LM3FURY';
  498. flashbase:$00000000;
  499. flashsize:$00020000;
  500. srambase:$20000000;
  501. sramsize:$00008000
  502. ),
  503. // ct_lm3s1651,
  504. (
  505. controllertypestr:'LM3S1651';
  506. controllerunitstr:'LM3FURY';
  507. flashbase:$00000000;
  508. flashsize:$00020000;
  509. srambase:$20000000;
  510. sramsize:$00008000
  511. ),
  512. // ct_lm3s2601,
  513. (
  514. controllertypestr:'LM3S2601';
  515. controllerunitstr:'LM3FURY';
  516. flashbase:$00000000;
  517. flashsize:$00020000;
  518. srambase:$20000000;
  519. sramsize:$00008000
  520. ),
  521. // ct_lm3s2608,
  522. (
  523. controllertypestr:'LM3S2608';
  524. controllerunitstr:'LM3FURY';
  525. flashbase:$00000000;
  526. flashsize:$00020000;
  527. srambase:$20000000;
  528. sramsize:$00008000
  529. ),
  530. // ct_lm3s2620,
  531. (
  532. controllertypestr:'LM3S2620';
  533. controllerunitstr:'LM3FURY';
  534. flashbase:$00000000;
  535. flashsize:$00020000;
  536. srambase:$20000000;
  537. sramsize:$00008000
  538. ),
  539. // ct_lm3s2637,
  540. (
  541. controllertypestr:'LM3S2637';
  542. controllerunitstr:'LM3FURY';
  543. flashbase:$00000000;
  544. flashsize:$00020000;
  545. srambase:$20000000;
  546. sramsize:$00008000
  547. ),
  548. // ct_lm3s2651,
  549. (
  550. controllertypestr:'LM3S2651';
  551. controllerunitstr:'LM3FURY';
  552. flashbase:$00000000;
  553. flashsize:$00020000;
  554. srambase:$20000000;
  555. sramsize:$00008000
  556. ),
  557. // ct_lm3s6610,
  558. (
  559. controllertypestr:'LM3S6610';
  560. controllerunitstr:'LM3FURY';
  561. flashbase:$00000000;
  562. flashsize:$00020000;
  563. srambase:$20000000;
  564. sramsize:$00008000
  565. ),
  566. // ct_lm3s6611,
  567. (
  568. controllertypestr:'LM3S6611';
  569. controllerunitstr:'LM3FURY';
  570. flashbase:$00000000;
  571. flashsize:$00020000;
  572. srambase:$20000000;
  573. sramsize:$00008000
  574. ),
  575. // ct_lm3s6618,
  576. (
  577. controllertypestr:'LM3S6618';
  578. controllerunitstr:'LM3FURY';
  579. flashbase:$00000000;
  580. flashsize:$00020000;
  581. srambase:$20000000;
  582. sramsize:$00008000
  583. ),
  584. // ct_lm3s6633,
  585. (
  586. controllertypestr:'LM3S6633';
  587. controllerunitstr:'LM3FURY';
  588. flashbase:$00000000;
  589. flashsize:$00020000;
  590. srambase:$20000000;
  591. sramsize:$00008000
  592. ),
  593. // ct_lm3s6637,
  594. (
  595. controllertypestr:'LM3S6637';
  596. controllerunitstr:'LM3FURY';
  597. flashbase:$00000000;
  598. flashsize:$00020000;
  599. srambase:$20000000;
  600. sramsize:$00008000
  601. ),
  602. // ct_lm3s8630,
  603. (
  604. controllertypestr:'LM3S8630';
  605. controllerunitstr:'LM3FURY';
  606. flashbase:$00000000;
  607. flashsize:$00020000;
  608. srambase:$20000000;
  609. sramsize:$00008000
  610. ),
  611. { TI - 256K Flash, 64K SRAM devices }
  612. // ct_lm3s1911,
  613. (
  614. controllertypestr:'LM3S1911';
  615. controllerunitstr:'LM3FURY';
  616. flashbase:$00000000;
  617. flashsize:$00040000;
  618. srambase:$20000000;
  619. sramsize:$00010000
  620. ),
  621. // ct_lm3s1918,
  622. (
  623. controllertypestr:'LM3S1918';
  624. controllerunitstr:'LM3FURY';
  625. flashbase:$00000000;
  626. flashsize:$00040000;
  627. srambase:$20000000;
  628. sramsize:$00010000
  629. ),
  630. // ct_lm3s1937,
  631. (
  632. controllertypestr:'LM3S1937';
  633. controllerunitstr:'LM3FURY';
  634. flashbase:$00000000;
  635. flashsize:$00040000;
  636. srambase:$20000000;
  637. sramsize:$00010000
  638. ),
  639. // ct_lm3s1958,
  640. (
  641. controllertypestr:'LM3S1958';
  642. controllerunitstr:'LM3FURY';
  643. flashbase:$00000000;
  644. flashsize:$00040000;
  645. srambase:$20000000;
  646. sramsize:$00010000
  647. ),
  648. // ct_lm3s1960,
  649. (
  650. controllertypestr:'LM3S1960';
  651. controllerunitstr:'LM3FURY';
  652. flashbase:$00000000;
  653. flashsize:$00040000;
  654. srambase:$20000000;
  655. sramsize:$00010000
  656. ),
  657. // ct_lm3s1968,
  658. (
  659. controllertypestr:'LM3S1968';
  660. controllerunitstr:'LM3FURY';
  661. flashbase:$00000000;
  662. flashsize:$00040000;
  663. srambase:$20000000;
  664. sramsize:$00010000
  665. ),
  666. // ct_lm3s1969,
  667. (
  668. controllertypestr:'LM3S1969';
  669. controllerunitstr:'LM3FURY';
  670. flashbase:$00000000;
  671. flashsize:$00040000;
  672. srambase:$20000000;
  673. sramsize:$00010000
  674. ),
  675. // ct_lm3s2911,
  676. (
  677. controllertypestr:'LM3S2911';
  678. controllerunitstr:'LM3FURY';
  679. flashbase:$00000000;
  680. flashsize:$00040000;
  681. srambase:$20000000;
  682. sramsize:$00010000
  683. ),
  684. // ct_lm3s2918,
  685. (
  686. controllertypestr:'LM3S2918';
  687. controllerunitstr:'LM3FURY';
  688. flashbase:$00000000;
  689. flashsize:$00040000;
  690. srambase:$20000000;
  691. sramsize:$00010000
  692. ),
  693. // ct_lm3s2919,
  694. (
  695. controllertypestr:'LM3S2919';
  696. controllerunitstr:'LM3FURY';
  697. flashbase:$00000000;
  698. flashsize:$00040000;
  699. srambase:$20000000;
  700. sramsize:$00010000
  701. ),
  702. // ct_lm3s2939,
  703. (
  704. controllertypestr:'LM3S2939';
  705. controllerunitstr:'LM3FURY';
  706. flashbase:$00000000;
  707. flashsize:$00040000;
  708. srambase:$20000000;
  709. sramsize:$00010000
  710. ),
  711. // ct_lm3s2948,
  712. (
  713. controllertypestr:'LM3S2948';
  714. controllerunitstr:'LM3FURY';
  715. flashbase:$00000000;
  716. flashsize:$00040000;
  717. srambase:$20000000;
  718. sramsize:$00010000
  719. ),
  720. // ct_lm3s2950,
  721. (
  722. controllertypestr:'LM3S2950';
  723. controllerunitstr:'LM3FURY';
  724. flashbase:$00000000;
  725. flashsize:$00040000;
  726. srambase:$20000000;
  727. sramsize:$00010000
  728. ),
  729. // ct_lm3s2965,
  730. (
  731. controllertypestr:'LM3S2965';
  732. controllerunitstr:'LM3FURY';
  733. flashbase:$00000000;
  734. flashsize:$00040000;
  735. srambase:$20000000;
  736. sramsize:$00010000
  737. ),
  738. // ct_lm3s6911,
  739. (
  740. controllertypestr:'LM3S6911';
  741. controllerunitstr:'LM3FURY';
  742. flashbase:$00000000;
  743. flashsize:$00040000;
  744. srambase:$20000000;
  745. sramsize:$00010000
  746. ),
  747. // ct_lm3s6918,
  748. (
  749. controllertypestr:'LM3S6918';
  750. controllerunitstr:'LM3FURY';
  751. flashbase:$00000000;
  752. flashsize:$00040000;
  753. srambase:$20000000;
  754. sramsize:$00010000
  755. ),
  756. // ct_lm3s6938,
  757. (
  758. controllertypestr:'LM3S6938';
  759. controllerunitstr:'LM3FURY';
  760. flashbase:$00000000;
  761. flashsize:$00040000;
  762. srambase:$20000000;
  763. sramsize:$00010000
  764. ),
  765. // ct_lm3s6950,
  766. (
  767. controllertypestr:'LM3S6950';
  768. controllerunitstr:'LM3FURY';
  769. flashbase:$00000000;
  770. flashsize:$00040000;
  771. srambase:$20000000;
  772. sramsize:$00010000
  773. ),
  774. // ct_lm3s6952,
  775. (
  776. controllertypestr:'LM3S6952';
  777. controllerunitstr:'LM3FURY';
  778. flashbase:$00000000;
  779. flashsize:$00040000;
  780. srambase:$20000000;
  781. sramsize:$00010000
  782. ),
  783. // ct_lm3s6965,
  784. (
  785. controllertypestr:'LM3S6965';
  786. controllerunitstr:'LM3FURY';
  787. flashbase:$00000000;
  788. flashsize:$00040000;
  789. srambase:$20000000;
  790. sramsize:$00010000
  791. ),
  792. // ct_lm3s8930,
  793. (
  794. controllertypestr:'LM3S8930';
  795. controllerunitstr:'LM3FURY';
  796. flashbase:$00000000;
  797. flashsize:$00040000;
  798. srambase:$20000000;
  799. sramsize:$00010000
  800. ),
  801. // ct_lm3s8933,
  802. (
  803. controllertypestr:'LM3S8933';
  804. controllerunitstr:'LM3FURY';
  805. flashbase:$00000000;
  806. flashsize:$00040000;
  807. srambase:$20000000;
  808. sramsize:$00010000
  809. ),
  810. // ct_lm3s8938,
  811. (
  812. controllertypestr:'LM3S8938';
  813. controllerunitstr:'LM3FURY';
  814. flashbase:$00000000;
  815. flashsize:$00040000;
  816. srambase:$20000000;
  817. sramsize:$00010000
  818. ),
  819. // ct_lm3s8962,
  820. (
  821. controllertypestr:'LM3S8962';
  822. controllerunitstr:'LM3FURY';
  823. flashbase:$00000000;
  824. flashsize:$00040000;
  825. srambase:$20000000;
  826. sramsize:$00010000
  827. ),
  828. // ct_lm3s8970,
  829. (
  830. controllertypestr:'LM3S8970';
  831. controllerunitstr:'LM3FURY';
  832. flashbase:$00000000;
  833. flashsize:$00040000;
  834. srambase:$20000000;
  835. sramsize:$00010000
  836. ),
  837. // ct_lm3s8971,
  838. (
  839. controllertypestr:'LM3S8971';
  840. controllerunitstr:'LM3FURY';
  841. flashbase:$00000000;
  842. flashsize:$00040000;
  843. srambase:$20000000;
  844. sramsize:$00010000
  845. ),
  846. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  847. // ct_lm3s5951,
  848. (
  849. controllertypestr:'LM3S5951';
  850. controllerunitstr:'LM3TEMPEST';
  851. flashbase:$00000000;
  852. flashsize:$00040000;
  853. srambase:$20000000;
  854. sramsize:$00010000
  855. ),
  856. // ct_lm3s5956,
  857. (
  858. controllertypestr:'LM3S5956';
  859. controllerunitstr:'LM3TEMPEST';
  860. flashbase:$00000000;
  861. flashsize:$00040000;
  862. srambase:$20000000;
  863. sramsize:$00010000
  864. ),
  865. // ct_lm3s1b21,
  866. (
  867. controllertypestr:'LM3S1B21';
  868. controllerunitstr:'LM3TEMPEST';
  869. flashbase:$00000000;
  870. flashsize:$00040000;
  871. srambase:$20000000;
  872. sramsize:$00010000
  873. ),
  874. // ct_lm3s2b93,
  875. (
  876. controllertypestr:'LM3S2B93';
  877. controllerunitstr:'LM3TEMPEST';
  878. flashbase:$00000000;
  879. flashsize:$00040000;
  880. srambase:$20000000;
  881. sramsize:$00010000
  882. ),
  883. // ct_lm3s5b91,
  884. (
  885. controllertypestr:'LM3S5B91';
  886. controllerunitstr:'LM3TEMPEST';
  887. flashbase:$00000000;
  888. flashsize:$00040000;
  889. srambase:$20000000;
  890. sramsize:$00010000
  891. ),
  892. // ct_lm3s9b81,
  893. (
  894. controllertypestr:'LM3S9B81';
  895. controllerunitstr:'LM3TEMPEST';
  896. flashbase:$00000000;
  897. flashsize:$00040000;
  898. srambase:$20000000;
  899. sramsize:$00010000
  900. ),
  901. // ct_lm3s9b90,
  902. (
  903. controllertypestr:'LM3S9B90';
  904. controllerunitstr:'LM3TEMPEST';
  905. flashbase:$00000000;
  906. flashsize:$00040000;
  907. srambase:$20000000;
  908. sramsize:$00010000
  909. ),
  910. // ct_lm3s9b92,
  911. (
  912. controllertypestr:'LM3S9B92';
  913. controllerunitstr:'LM3TEMPEST';
  914. flashbase:$00000000;
  915. flashsize:$00040000;
  916. srambase:$20000000;
  917. sramsize:$00010000
  918. ),
  919. // ct_lm3s9b95,
  920. (
  921. controllertypestr:'LM3S9B95';
  922. controllerunitstr:'LM3TEMPEST';
  923. flashbase:$00000000;
  924. flashsize:$00040000;
  925. srambase:$20000000;
  926. sramsize:$00010000
  927. ),
  928. // ct_lm3s9b96,
  929. (
  930. controllertypestr:'LM3S9B96';
  931. controllerunitstr:'LM3TEMPEST';
  932. flashbase:$00000000;
  933. flashsize:$00040000;
  934. srambase:$20000000;
  935. sramsize:$00010000
  936. ),
  937. //ct_SC32442b,
  938. (
  939. controllertypestr:'SC32442B';
  940. controllerunitstr:'sc32442b';
  941. flashbase:$00000000;
  942. flashsize:$00000000;
  943. srambase:$00000000;
  944. sramsize:$08000000
  945. ),
  946. // bare bones Thumb2
  947. (
  948. controllertypestr:'THUMB2_BARE';
  949. controllerunitstr:'THUMB2_BARE';
  950. flashbase:$00000000;
  951. flashsize:$00100000;
  952. srambase:$20000000;
  953. sramsize:$00100000
  954. )
  955. );
  956. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16];
  957. { Supported optimizations, only used for information }
  958. supported_optimizerswitches = genericlevel1optimizerswitches+
  959. genericlevel2optimizerswitches+
  960. genericlevel3optimizerswitches-
  961. { no need to write info about those }
  962. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  963. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  964. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  965. level1optimizerswitches = genericlevel1optimizerswitches;
  966. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  967. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  968. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [cs_opt_scheduler{,cs_opt_loopunroll}];
  969. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  970. type
  971. tcpuflags =
  972. (CPUARM_HAS_BX, { CPU supports the BX instruction }
  973. CPUARM_HAS_BLX, { CPU supports the BLX rX instruction }
  974. CPUARM_HAS_BLX_LABEL, { CPU supports the BLX <label> instruction }
  975. CPUARM_HAS_CLZ, { CPU supports the CLZ instruction }
  976. CPUARM_HAS_EDSP, { CPU supports the PLD,STRD,LDRD,MCRR and MRRC instructions }
  977. CPUARM_HAS_REV, { CPU supports the REV instruction }
  978. CPUARM_HAS_LDREX,
  979. CPUARM_HAS_IDIV
  980. );
  981. const
  982. cpu_capabilities : array[tcputype] of set of tcpuflags =
  983. ( { cpu_none } [],
  984. { cpu_armv3 } [],
  985. { cpu_armv4 } [],
  986. { cpu_armv4t } [CPUARM_HAS_BX],
  987. { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  988. { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  989. { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  990. { cpu_armv5tej } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  991. { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  992. { cpu_armv6k } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  993. { cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  994. { cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  995. { the identifier armv7 is should not be used, it is considered being equal to armv7a }
  996. { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  997. { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  998. { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  999. { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
  1000. { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
  1001. );
  1002. Implementation
  1003. end.