aoptcpu.pas 30 KB

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  1. {
  2. Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
  3. Development Team
  4. This unit implements the ARM optimizer object
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. Interface
  21. uses cpubase, aasmtai, aopt, aoptcpub;
  22. Type
  23. TCpuAsmOptimizer = class(TAsmOptimizer)
  24. { uses the same constructor as TAopObj }
  25. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  26. procedure PeepHoleOptPass2;override;
  27. End;
  28. TCpuPreRegallocScheduler = class(TAsmOptimizer)
  29. function PeepHoleOptPass1Cpu(var p: tai): boolean;override;
  30. end;
  31. TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
  32. { uses the same constructor as TAopObj }
  33. procedure PeepHoleOptPass2;override;
  34. End;
  35. Implementation
  36. uses
  37. cutils,
  38. verbose,
  39. cgbase,cgutils,
  40. aasmbase,aasmdata,aasmcpu;
  41. function CanBeCond(p : tai) : boolean;
  42. begin
  43. result:=
  44. (p.typ=ait_instruction) and
  45. (taicpu(p).condition=C_None) and
  46. ((taicpu(p).opcode<>A_BLX) or
  47. (taicpu(p).oper[0]^.typ=top_reg));
  48. end;
  49. function RefsEqual(const r1, r2: treference): boolean;
  50. begin
  51. refsequal :=
  52. (r1.offset = r2.offset) and
  53. (r1.base = r2.base) and
  54. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  55. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  56. (r1.relsymbol = r2.relsymbol) and
  57. (r1.signindex = r2.signindex) and
  58. (r1.shiftimm = r2.shiftimm) and
  59. (r1.addressmode = r2.addressmode) and
  60. (r1.shiftmode = r2.shiftmode);
  61. end;
  62. function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
  63. begin
  64. result :=
  65. (instr.typ = ait_instruction) and
  66. (taicpu(instr).opcode = op) and
  67. ((cond = []) or (taicpu(instr).condition in cond)) and
  68. ((postfix = []) or (taicpu(instr).oppostfix in postfix));
  69. end;
  70. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
  71. begin
  72. result := (oper1.typ = oper2.typ) and
  73. (
  74. ((oper1.typ = top_const) and (oper1.val = oper2.val)) or
  75. ((oper1.typ = top_reg) and (oper1.reg = oper2.reg)) or
  76. ((oper1.typ = top_conditioncode) and (oper1.cc = oper2.cc))
  77. );
  78. end;
  79. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  80. begin
  81. result := (oper.typ = top_reg) and (oper.reg = reg);
  82. end;
  83. procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList) ;
  84. begin
  85. if (taicpu(movp).condition = C_EQ) and
  86. (taicpu(cmpp).oper[0]^.reg = taicpu(movp).oper[0]^.reg) and
  87. (taicpu(cmpp).oper[1]^.val = taicpu(movp).oper[1]^.val) then
  88. begin
  89. asml.insertafter(tai_comment.Create(strpnew('Peephole CmpMovMov - Removed redundant moveq')), movp);
  90. asml.remove(movp);
  91. movp.free;
  92. end;
  93. end;
  94. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  95. var
  96. hp1,hp2: tai;
  97. i: longint;
  98. begin
  99. result := false;
  100. case p.typ of
  101. ait_instruction:
  102. begin
  103. (* optimization proved not to be safe, see tw4768.pp
  104. {
  105. change
  106. <op> reg,x,y
  107. cmp reg,#0
  108. into
  109. <op>s reg,x,y
  110. }
  111. { this optimization can applied only to the currently enabled operations because
  112. the other operations do not update all flags and FPC does not track flag usage }
  113. if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
  114. (taicpu(p).oppostfix = PF_None) and
  115. (taicpu(p).condition = C_None) and
  116. GetNextInstruction(p, hp1) and
  117. MatchInstruction(hp1, A_CMP, [C_None], [PF_None]) and
  118. (taicpu(hp1).oper[1]^.typ = top_const) and
  119. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  120. (taicpu(hp1).oper[1]^.val = 0) { and
  121. GetNextInstruction(hp1, hp2) and
  122. (tai(hp2).typ = ait_instruction) and
  123. // be careful here, following instructions could use other flags
  124. // however after a jump fpc never depends on the value of flags
  125. (taicpu(hp2).opcode = A_B) and
  126. (taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL])} then
  127. begin
  128. taicpu(p).oppostfix:=PF_S;
  129. asml.remove(hp1);
  130. hp1.free;
  131. end
  132. else
  133. *)
  134. case taicpu(p).opcode of
  135. A_STR:
  136. begin
  137. { change
  138. str reg1,ref
  139. ldr reg2,ref
  140. into
  141. str reg1,ref
  142. mov reg2,reg1
  143. }
  144. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  145. GetNextInstruction(p,hp1) and
  146. MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
  147. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  148. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  149. begin
  150. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  151. begin
  152. asml.remove(hp1);
  153. hp1.free;
  154. end
  155. else
  156. begin
  157. asml.insertbefore(tai_comment.Create(strpnew('Peephole StrLdr2StrMov done')), hp1);
  158. taicpu(hp1).opcode:=A_MOV;
  159. taicpu(hp1).oppostfix:=PF_None;
  160. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  161. end;
  162. result := true;
  163. end;
  164. end;
  165. A_LDR:
  166. begin
  167. { change
  168. ldr reg1,ref
  169. ldr reg2,ref
  170. into
  171. ldr reg1,ref
  172. mov reg2,reg1
  173. }
  174. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  175. GetNextInstruction(p,hp1) and
  176. MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
  177. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  178. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
  179. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
  180. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  181. begin
  182. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  183. begin
  184. asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2Ldr done')), hp1);
  185. asml.remove(hp1);
  186. hp1.free;
  187. end
  188. else
  189. begin
  190. asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2LdrMov done')), hp1);
  191. taicpu(hp1).opcode:=A_MOV;
  192. taicpu(hp1).oppostfix:=PF_None;
  193. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  194. end;
  195. result := true;
  196. end;
  197. end;
  198. A_MOV:
  199. begin
  200. { fold
  201. mov reg1,reg0, shift imm1
  202. mov reg1,reg1, shift imm2
  203. to
  204. mov reg1,reg0, shift imm1+imm2
  205. }
  206. if (taicpu(p).ops=3) and
  207. (taicpu(p).oper[2]^.typ = top_shifterop) and
  208. (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
  209. getnextinstruction(p,hp1) and
  210. MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and
  211. (taicpu(hp1).ops=3) and
  212. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
  213. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
  214. (taicpu(hp1).oper[2]^.typ = top_shifterop) and
  215. (taicpu(hp1).oper[2]^.shifterop^.rs = NR_NO) and
  216. (taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(hp1).oper[2]^.shifterop^.shiftmode) then
  217. begin
  218. inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(hp1).oper[2]^.shifterop^.shiftimm);
  219. { avoid overflows }
  220. if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
  221. case taicpu(p).oper[2]^.shifterop^.shiftmode of
  222. SM_ROR:
  223. taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
  224. SM_ASR:
  225. taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
  226. SM_LSR,
  227. SM_LSL:
  228. begin
  229. hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
  230. InsertLLItem(p.previous, p.next, hp1);
  231. p.free;
  232. p:=hp1;
  233. end;
  234. else
  235. internalerror(2008072803);
  236. end;
  237. asml.insertbefore(tai_comment.Create(strpnew('Peephole ShiftShift2Shift done')), p);
  238. asml.remove(hp1);
  239. hp1.free;
  240. result := true;
  241. end;
  242. {
  243. This changes the very common
  244. mov r0, #0
  245. str r0, [...]
  246. mov r0, #0
  247. str r0, [...]
  248. and removes all superfluous mov instructions
  249. }
  250. if (taicpu(p).ops = 2) and
  251. (taicpu(p).oper[1]^.typ = top_const) and
  252. GetNextInstruction(p,hp1) then
  253. begin
  254. while MatchInstruction(hp1, A_STR, [], []) and
  255. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) and
  256. GetNextInstruction(hp1, hp2) and
  257. MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [taicpu(p).oppostfix]) and
  258. (taicpu(hp2).ops = 2) and
  259. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^) and
  260. MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) do
  261. begin
  262. asml.insertbefore(tai_comment.Create(strpnew('Peephole MovStrMov done')), hp2);
  263. GetNextInstruction(hp2,hp1);
  264. asml.remove(hp2);
  265. hp2.free;
  266. if not assigned(hp1) then break;
  267. end;
  268. end;
  269. {
  270. change
  271. mov r1, r0
  272. add r1, r1, #1
  273. to
  274. add r1, r0, #1
  275. }
  276. if (taicpu(p).ops = 2) and
  277. (taicpu(p).oper[1]^.typ = top_reg) and
  278. (taicpu(p).oppostfix = PF_NONE) and
  279. GetNextInstruction(p, hp1) and
  280. (tai(hp1).typ = ait_instruction) and
  281. (taicpu(hp1).opcode in [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
  282. A_AND, A_BIC, A_EOR, A_ORR]) and
  283. (taicpu(hp1).condition in [C_NONE, taicpu(hp1).condition]) and
  284. MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
  285. (taicpu(hp1).oper[1]^.typ = top_reg) and
  286. (taicpu(hp1).oper[2]^.typ in [top_reg, top_const]) then
  287. begin
  288. { When we get here we still don't know if the registers match}
  289. for I:=1 to 2 do
  290. {
  291. If the first loop was successful p will be replaced with hp1.
  292. The checks will still be ok, because all required information
  293. will also be in hp1 then.
  294. }
  295. if MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg) then
  296. begin
  297. asml.insertbefore(tai_comment.Create(strpnew('Peephole RedundantMovProcess done ')), hp1);
  298. taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
  299. if p<>hp1 then
  300. begin
  301. asml.remove(p);
  302. p.free;
  303. p:=hp1;
  304. end;
  305. end;
  306. end;
  307. end;
  308. A_AND:
  309. begin
  310. {
  311. change
  312. and reg2,reg1,const1
  313. and reg2,reg2,const2
  314. to
  315. and reg2,reg1,(const1 and const2)
  316. }
  317. if (taicpu(p).oper[1]^.typ = top_reg) and
  318. (taicpu(p).oper[2]^.typ = top_const) and
  319. GetNextInstruction(p, hp1) and
  320. MatchInstruction(hp1, A_AND, [taicpu(p).condition], [PF_None]) and
  321. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
  322. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
  323. (taicpu(hp1).oper[2]^.typ = top_const) then
  324. begin
  325. asml.insertbefore(tai_comment.Create(strpnew('Peephole AndAnd2And done')), p);
  326. taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
  327. taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
  328. asml.remove(hp1);
  329. hp1.free;
  330. end;
  331. end;
  332. A_CMP:
  333. begin
  334. {
  335. change
  336. cmp reg,const1
  337. moveq reg,const1
  338. movne reg,const2
  339. to
  340. cmp reg,const1
  341. movne reg,const2
  342. }
  343. if (taicpu(p).oper[1]^.typ = top_const) and
  344. GetNextInstruction(p, hp1) and
  345. MatchInstruction(hp1, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
  346. (taicpu(hp1).oper[1]^.typ = top_const) and
  347. GetNextInstruction(hp1, hp2) and
  348. MatchInstruction(hp2, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
  349. (taicpu(hp1).oper[1]^.typ = top_const) then
  350. begin
  351. RemoveRedundantMove(p, hp1, asml);
  352. RemoveRedundantMove(p, hp2, asml);
  353. end;
  354. end;
  355. end;
  356. end;
  357. end;
  358. end;
  359. { instructions modifying the CPSR can be only the last instruction }
  360. function MustBeLast(p : tai) : boolean;
  361. begin
  362. Result:=(p.typ=ait_instruction) and
  363. ((taicpu(p).opcode in [A_BL,A_BLX,A_CMP,A_CMN,A_SWI,A_TEQ,A_TST,A_CMF,A_CMFE {,A_MSR}]) or
  364. ((taicpu(p).ops>=1) and (taicpu(p).oper[0]^.typ=top_reg) and (taicpu(p).oper[0]^.reg=NR_PC)) or
  365. (taicpu(p).oppostfix=PF_S));
  366. end;
  367. procedure TCpuAsmOptimizer.PeepHoleOptPass2;
  368. var
  369. p,hp1,hp2: tai;
  370. l : longint;
  371. condition : tasmcond;
  372. hp3: tai;
  373. WasLast: boolean;
  374. { UsedRegs, TmpUsedRegs: TRegSet; }
  375. begin
  376. p := BlockStart;
  377. { UsedRegs := []; }
  378. while (p <> BlockEnd) Do
  379. begin
  380. { UpdateUsedRegs(UsedRegs, tai(p.next)); }
  381. case p.Typ Of
  382. Ait_Instruction:
  383. begin
  384. case taicpu(p).opcode Of
  385. A_B:
  386. if taicpu(p).condition<>C_None then
  387. begin
  388. { check for
  389. Bxx xxx
  390. <several instructions>
  391. xxx:
  392. }
  393. l:=0;
  394. WasLast:=False;
  395. GetNextInstruction(p, hp1);
  396. while assigned(hp1) and
  397. (l<=4) and
  398. CanBeCond(hp1) and
  399. { stop on labels }
  400. not(hp1.typ=ait_label) do
  401. begin
  402. inc(l);
  403. if MustBeLast(hp1) then
  404. begin
  405. WasLast:=True;
  406. GetNextInstruction(hp1,hp1);
  407. break;
  408. end
  409. else
  410. GetNextInstruction(hp1,hp1);
  411. end;
  412. if assigned(hp1) then
  413. begin
  414. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  415. begin
  416. if (l<=4) and (l>0) then
  417. begin
  418. condition:=inverse_cond(taicpu(p).condition);
  419. hp2:=p;
  420. GetNextInstruction(p,hp1);
  421. p:=hp1;
  422. repeat
  423. if hp1.typ=ait_instruction then
  424. taicpu(hp1).condition:=condition;
  425. if MustBeLast(hp1) then
  426. begin
  427. GetNextInstruction(hp1,hp1);
  428. break;
  429. end
  430. else
  431. GetNextInstruction(hp1,hp1);
  432. until not(assigned(hp1)) or
  433. not(CanBeCond(hp1)) or
  434. (hp1.typ=ait_label);
  435. { wait with removing else GetNextInstruction could
  436. ignore the label if it was the only usage in the
  437. jump moved away }
  438. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  439. asml.remove(hp2);
  440. hp2.free;
  441. continue;
  442. end;
  443. end
  444. else
  445. { do not perform further optimizations if there is inctructon
  446. in block #1 which can not be optimized.
  447. }
  448. if not WasLast then
  449. begin
  450. { check further for
  451. Bcc xxx
  452. <several instructions 1>
  453. B yyy
  454. xxx:
  455. <several instructions 2>
  456. yyy:
  457. }
  458. { hp2 points to jmp yyy }
  459. hp2:=hp1;
  460. { skip hp1 to xxx }
  461. GetNextInstruction(hp1, hp1);
  462. if assigned(hp2) and
  463. assigned(hp1) and
  464. (l<=3) and
  465. (hp2.typ=ait_instruction) and
  466. (taicpu(hp2).is_jmp) and
  467. (taicpu(hp2).condition=C_None) and
  468. { real label and jump, no further references to the
  469. label are allowed }
  470. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  471. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  472. begin
  473. l:=0;
  474. { skip hp1 to <several moves 2> }
  475. GetNextInstruction(hp1, hp1);
  476. while assigned(hp1) and
  477. CanBeCond(hp1) do
  478. begin
  479. inc(l);
  480. GetNextInstruction(hp1, hp1);
  481. end;
  482. { hp1 points to yyy: }
  483. if assigned(hp1) and
  484. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  485. begin
  486. condition:=inverse_cond(taicpu(p).condition);
  487. GetNextInstruction(p,hp1);
  488. hp3:=p;
  489. p:=hp1;
  490. repeat
  491. if hp1.typ=ait_instruction then
  492. taicpu(hp1).condition:=condition;
  493. GetNextInstruction(hp1,hp1);
  494. until not(assigned(hp1)) or
  495. not(CanBeCond(hp1));
  496. { hp2 is still at jmp yyy }
  497. GetNextInstruction(hp2,hp1);
  498. { hp2 is now at xxx: }
  499. condition:=inverse_cond(condition);
  500. GetNextInstruction(hp1,hp1);
  501. { hp1 is now at <several movs 2> }
  502. repeat
  503. taicpu(hp1).condition:=condition;
  504. GetNextInstruction(hp1,hp1);
  505. until not(assigned(hp1)) or
  506. not(CanBeCond(hp1)) or
  507. (hp1.typ=ait_label);
  508. {
  509. asml.remove(hp1.next)
  510. hp1.next.free;
  511. asml.remove(hp1);
  512. hp1.free;
  513. }
  514. { remove Bcc }
  515. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  516. asml.remove(hp3);
  517. hp3.free;
  518. { remove jmp }
  519. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  520. asml.remove(hp2);
  521. hp2.free;
  522. continue;
  523. end;
  524. end;
  525. end;
  526. end;
  527. end;
  528. end;
  529. end;
  530. end;
  531. p := tai(p.next)
  532. end;
  533. end;
  534. const
  535. { set of opcode which might or do write to memory }
  536. { TODO : extend armins.dat to contain r/w info }
  537. opcode_could_mem_write = [A_B,A_BL,A_BLX,A_BKPT,A_BX,A_STR,A_STRB,A_STRBT,
  538. A_STRH,A_STRT,A_STF,A_SFM,A_STM,A_FSTS,A_FSTD];
  539. function TCpuPreRegallocScheduler.PeepHoleOptPass1Cpu(var p: tai): boolean;
  540. { TODO : schedule also forward }
  541. { TODO : schedule distance > 1 }
  542. var
  543. hp1,hp2,hp3,hp4,hp5 : tai;
  544. list : TAsmList;
  545. begin
  546. result:=true;
  547. list:=TAsmList.Create;
  548. p := BlockStart;
  549. { UsedRegs := []; }
  550. while (p <> BlockEnd) Do
  551. begin
  552. if (p.typ=ait_instruction) and
  553. GetNextInstruction(p,hp1) and
  554. (hp1.typ=ait_instruction) and
  555. { for now we don't reschedule if the previous instruction changes potentially a memory location }
  556. ( (not(taicpu(p).opcode in opcode_could_mem_write) and
  557. not(RegModifiedByInstruction(NR_PC,p)) and
  558. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH])
  559. ) or
  560. ((taicpu(p).opcode in [A_STM,A_STRB,A_STRH,A_STR]) and
  561. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
  562. ((taicpu(hp1).oper[1]^.ref^.base=NR_PC) or
  563. (assigned(taicpu(hp1).oper[1]^.ref^.symboldata) and
  564. (taicpu(hp1).oper[1]^.ref^.offset=0)
  565. )
  566. ) or
  567. { try to prove that the memory accesses don't overlapp }
  568. ((taicpu(p).opcode in [A_STRB,A_STRH,A_STR]) and
  569. (taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
  570. (taicpu(p).oper[1]^.ref^.base=taicpu(hp1).oper[1]^.ref^.base) and
  571. (taicpu(p).oppostfix=PF_None) and
  572. (taicpu(hp1).oppostfix=PF_None) and
  573. (taicpu(p).oper[1]^.ref^.index=NR_NO) and
  574. (taicpu(hp1).oper[1]^.ref^.index=NR_NO) and
  575. { get operand sizes and check if the offset distance is large enough to ensure no overlapp }
  576. (abs(taicpu(p).oper[1]^.ref^.offset-taicpu(hp1).oper[1]^.ref^.offset)>=max(tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)],tcgsize2size[reg_cgsize(taicpu(hp1).oper[0]^.reg)]))
  577. )
  578. )
  579. ) and
  580. GetNextInstruction(hp1,hp2) and
  581. (hp2.typ=ait_instruction) and
  582. { loaded register used by next instruction? }
  583. (RegInInstruction(taicpu(hp1).oper[0]^.reg,hp2)) and
  584. { loaded register not used by previous instruction? }
  585. not(RegInInstruction(taicpu(hp1).oper[0]^.reg,p)) and
  586. { same condition? }
  587. (taicpu(p).condition=taicpu(hp1).condition) and
  588. { first instruction might not change the register used as base }
  589. ((taicpu(hp1).oper[1]^.ref^.base=NR_NO) or
  590. not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.base,p))
  591. ) and
  592. { first instruction might not change the register used as index }
  593. ((taicpu(hp1).oper[1]^.ref^.index=NR_NO) or
  594. not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.index,p))
  595. ) then
  596. begin
  597. hp3:=tai(p.Previous);
  598. hp5:=tai(p.next);
  599. asml.Remove(p);
  600. { if there is a reg. dealloc instruction associated with p, move it together with p }
  601. { before the instruction? }
  602. while assigned(hp3) and (hp3.typ<>ait_instruction) do
  603. begin
  604. if (hp3.typ=ait_regalloc) and (tai_regalloc(hp3).ratype in [ra_dealloc]) and
  605. RegInInstruction(tai_regalloc(hp3).reg,p) then
  606. begin
  607. hp4:=hp3;
  608. hp3:=tai(hp3.Previous);
  609. asml.Remove(hp4);
  610. list.Concat(hp4);
  611. end
  612. else
  613. hp3:=tai(hp3.Previous);
  614. end;
  615. list.Concat(p);
  616. { after the instruction? }
  617. while assigned(hp5) and (hp5.typ<>ait_instruction) do
  618. begin
  619. if (hp5.typ=ait_regalloc) and (tai_regalloc(hp5).ratype in [ra_dealloc]) and
  620. RegInInstruction(tai_regalloc(hp5).reg,p) then
  621. begin
  622. hp4:=hp5;
  623. hp5:=tai(hp5.next);
  624. asml.Remove(hp4);
  625. list.Concat(hp4);
  626. end
  627. else
  628. hp5:=tai(hp5.Next);
  629. end;
  630. asml.Remove(hp1);
  631. {$ifdef DEBUG_PREREGSCHEDULER}
  632. asml.InsertBefore(tai_comment.Create(strpnew('Rescheduled')),hp2);
  633. {$endif DEBUG_PREREGSCHEDULER}
  634. asml.InsertBefore(hp1,hp2);
  635. asml.InsertListBefore(hp2,list);
  636. end;
  637. p := tai(p.next)
  638. end;
  639. list.Free;
  640. end;
  641. procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
  642. begin
  643. { TODO: Add optimizer code }
  644. end;
  645. begin
  646. casmoptimizer:=TCpuAsmOptimizer;
  647. cpreregallocscheduler:=TCpuPreRegallocScheduler;
  648. End.