popt386.pas 102 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit popt386;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses Aasmbase,aasmtai,aasmcpu,verbose;
  21. procedure PrePeepHoleOpts(asml: taasmoutput; BlockStart, BlockEnd: tai);
  22. procedure PeepHoleOptPass1(asml: taasmoutput; BlockStart, BlockEnd: tai);
  23. procedure PeepHoleOptPass2(asml: taasmoutput; BlockStart, BlockEnd: tai);
  24. procedure PostPeepHoleOpts(asml: taasmoutput; BlockStart, BlockEnd: tai);
  25. implementation
  26. uses
  27. globtype,systems,
  28. globals,cgbase,procinfo,
  29. symsym,
  30. {$ifdef finaldestdebug}
  31. cobjects,
  32. {$endif finaldestdebug}
  33. cpuinfo,cpubase,cgutils,daopt386;
  34. function RegUsedAfterInstruction(reg: Tregister; p: tai; var UsedRegs: TRegSet): Boolean;
  35. var
  36. supreg: tsuperregister;
  37. begin
  38. supreg := getsupreg(reg);
  39. UpdateUsedRegs(UsedRegs, tai(p.Next));
  40. RegUsedAfterInstruction :=
  41. (supreg in UsedRegs) and
  42. (not(getNextInstruction(p,p)) or
  43. not(regLoadedWithNewValue(supreg,false,p)));
  44. end;
  45. function doFpuLoadStoreOpt(asmL: TAAsmoutput; var p: tai): boolean;
  46. { returns true if a "continue" should be done after this optimization }
  47. var hp1, hp2: tai;
  48. begin
  49. doFpuLoadStoreOpt := false;
  50. if (taicpu(p).oper[0]^.typ = top_ref) and
  51. getNextInstruction(p, hp1) and
  52. (hp1.typ = ait_instruction) and
  53. (((taicpu(hp1).opcode = A_FLD) and
  54. (taicpu(p).opcode = A_FSTP)) or
  55. ((taicpu(p).opcode = A_FISTP) and
  56. (taicpu(hp1).opcode = A_FILD))) and
  57. (taicpu(hp1).oper[0]^.typ = top_ref) and
  58. (taicpu(hp1).opsize = taicpu(p).opsize) and
  59. refsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  60. begin
  61. { replacing fstp f;fld f by fst f is only valid for extended because of rounding }
  62. if (taicpu(p).opsize=S_FX) and
  63. getNextInstruction(hp1, hp2) and
  64. (hp2.typ = ait_instruction) and
  65. ((taicpu(hp2).opcode = A_LEAVE) or
  66. (taicpu(hp2).opcode = A_RET)) and
  67. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  68. not(assigned(current_procinfo.procdef.funcretsym) and
  69. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  70. (taicpu(p).oper[0]^.ref^.index = NR_NO) then
  71. begin
  72. asml.remove(p);
  73. asml.remove(hp1);
  74. p.free;
  75. hp1.free;
  76. p := hp2;
  77. removeLastDeallocForFuncRes(asmL, p);
  78. doFPULoadStoreOpt := true;
  79. end
  80. { can't be done because the store operation rounds
  81. else
  82. { fst can't store an extended value! }
  83. if (taicpu(p).opsize <> S_FX) and
  84. (taicpu(p).opsize <> S_IQ) then
  85. begin
  86. if (taicpu(p).opcode = A_FSTP) then
  87. taicpu(p).opcode := A_FST
  88. else taicpu(p).opcode := A_FIST;
  89. asml.remove(hp1);
  90. hp1.free;
  91. end
  92. }
  93. end;
  94. end;
  95. procedure PrePeepHoleOpts(asml: taasmoutput; BlockStart, BlockEnd: tai);
  96. var
  97. p,hp1: tai;
  98. l: aint;
  99. tmpRef: treference;
  100. begin
  101. p := BlockStart;
  102. while (p <> BlockEnd) Do
  103. begin
  104. case p.Typ Of
  105. Ait_Instruction:
  106. begin
  107. case taicpu(p).opcode Of
  108. A_IMUL:
  109. {changes certain "imul const, %reg"'s to lea sequences}
  110. begin
  111. if (taicpu(p).oper[0]^.typ = Top_Const) and
  112. (taicpu(p).oper[1]^.typ = Top_Reg) and
  113. (taicpu(p).opsize = S_L) then
  114. if (taicpu(p).oper[0]^.val = 1) then
  115. if (taicpu(p).ops = 2) then
  116. {remove "imul $1, reg"}
  117. begin
  118. hp1 := tai(p.Next);
  119. asml.remove(p);
  120. p.free;
  121. p := hp1;
  122. continue;
  123. end
  124. else
  125. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  126. begin
  127. hp1 := taicpu.Op_Reg_Reg(A_MOV, S_L, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
  128. InsertLLItem(asml, p.previous, p.next, hp1);
  129. p.free;
  130. p := hp1;
  131. end
  132. else if
  133. ((taicpu(p).ops <= 2) or
  134. (taicpu(p).oper[2]^.typ = Top_Reg)) and
  135. (aktoptprocessor < ClassPentium2) and
  136. (taicpu(p).oper[0]^.val <= 12) and
  137. not(CS_LittleSize in aktglobalswitches) and
  138. (not(GetNextInstruction(p, hp1)) or
  139. {GetNextInstruction(p, hp1) and}
  140. not((tai(hp1).typ = ait_instruction) and
  141. ((taicpu(hp1).opcode=A_Jcc) and
  142. (taicpu(hp1).condition in [C_O,C_NO])))) then
  143. begin
  144. reference_reset(tmpref);
  145. case taicpu(p).oper[0]^.val Of
  146. 3: begin
  147. {imul 3, reg1, reg2 to
  148. lea (reg1,reg1,2), reg2
  149. imul 3, reg1 to
  150. lea (reg1,reg1,2), reg1}
  151. TmpRef.base := taicpu(p).oper[1]^.reg;
  152. TmpRef.index := taicpu(p).oper[1]^.reg;
  153. TmpRef.ScaleFactor := 2;
  154. if (taicpu(p).ops = 2) then
  155. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  156. else
  157. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  158. InsertLLItem(asml,p.previous, p.next, hp1);
  159. p.free;
  160. p := hp1;
  161. end;
  162. 5: begin
  163. {imul 5, reg1, reg2 to
  164. lea (reg1,reg1,4), reg2
  165. imul 5, reg1 to
  166. lea (reg1,reg1,4), reg1}
  167. TmpRef.base := taicpu(p).oper[1]^.reg;
  168. TmpRef.index := taicpu(p).oper[1]^.reg;
  169. TmpRef.ScaleFactor := 4;
  170. if (taicpu(p).ops = 2) then
  171. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  172. else
  173. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  174. InsertLLItem(asml,p.previous, p.next, hp1);
  175. p.free;
  176. p := hp1;
  177. end;
  178. 6: begin
  179. {imul 6, reg1, reg2 to
  180. lea (,reg1,2), reg2
  181. lea (reg2,reg1,4), reg2
  182. imul 6, reg1 to
  183. lea (reg1,reg1,2), reg1
  184. add reg1, reg1}
  185. if (aktoptprocessor <= Class386) then
  186. begin
  187. TmpRef.index := taicpu(p).oper[1]^.reg;
  188. if (taicpu(p).ops = 3) then
  189. begin
  190. TmpRef.base := taicpu(p).oper[2]^.reg;
  191. TmpRef.ScaleFactor := 4;
  192. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  193. end
  194. else
  195. begin
  196. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  197. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  198. end;
  199. InsertLLItem(asml,p, p.next, hp1);
  200. reference_reset(tmpref);
  201. TmpRef.index := taicpu(p).oper[1]^.reg;
  202. TmpRef.ScaleFactor := 2;
  203. if (taicpu(p).ops = 3) then
  204. begin
  205. TmpRef.base := NR_NO;
  206. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  207. taicpu(p).oper[2]^.reg);
  208. end
  209. else
  210. begin
  211. TmpRef.base := taicpu(p).oper[1]^.reg;
  212. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  213. end;
  214. InsertLLItem(asml,p.previous, p.next, hp1);
  215. p.free;
  216. p := tai(hp1.next);
  217. end
  218. end;
  219. 9: begin
  220. {imul 9, reg1, reg2 to
  221. lea (reg1,reg1,8), reg2
  222. imul 9, reg1 to
  223. lea (reg1,reg1,8), reg1}
  224. TmpRef.base := taicpu(p).oper[1]^.reg;
  225. TmpRef.index := taicpu(p).oper[1]^.reg;
  226. TmpRef.ScaleFactor := 8;
  227. if (taicpu(p).ops = 2) then
  228. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  229. else
  230. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  231. InsertLLItem(asml,p.previous, p.next, hp1);
  232. p.free;
  233. p := hp1;
  234. end;
  235. 10: begin
  236. {imul 10, reg1, reg2 to
  237. lea (reg1,reg1,4), reg2
  238. add reg2, reg2
  239. imul 10, reg1 to
  240. lea (reg1,reg1,4), reg1
  241. add reg1, reg1}
  242. if (aktoptprocessor <= Class386) then
  243. begin
  244. if (taicpu(p).ops = 3) then
  245. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  246. taicpu(p).oper[2]^.reg,taicpu(p).oper[2]^.reg)
  247. else
  248. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  249. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  250. InsertLLItem(asml,p, p.next, hp1);
  251. TmpRef.base := taicpu(p).oper[1]^.reg;
  252. TmpRef.index := taicpu(p).oper[1]^.reg;
  253. TmpRef.ScaleFactor := 4;
  254. if (taicpu(p).ops = 3) then
  255. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg)
  256. else
  257. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  258. InsertLLItem(asml,p.previous, p.next, hp1);
  259. p.free;
  260. p := tai(hp1.next);
  261. end
  262. end;
  263. 12: begin
  264. {imul 12, reg1, reg2 to
  265. lea (,reg1,4), reg2
  266. lea (,reg1,8) reg2
  267. imul 12, reg1 to
  268. lea (reg1,reg1,2), reg1
  269. lea (,reg1,4), reg1}
  270. if (aktoptprocessor <= Class386)
  271. then
  272. begin
  273. TmpRef.index := taicpu(p).oper[1]^.reg;
  274. if (taicpu(p).ops = 3) then
  275. begin
  276. TmpRef.base := taicpu(p).oper[2]^.reg;
  277. TmpRef.ScaleFactor := 8;
  278. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  279. end
  280. else
  281. begin
  282. TmpRef.base := NR_NO;
  283. TmpRef.ScaleFactor := 4;
  284. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  285. end;
  286. InsertLLItem(asml,p, p.next, hp1);
  287. reference_reset(tmpref);
  288. TmpRef.index := taicpu(p).oper[1]^.reg;
  289. if (taicpu(p).ops = 3) then
  290. begin
  291. TmpRef.base := NR_NO;
  292. TmpRef.ScaleFactor := 4;
  293. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  294. end
  295. else
  296. begin
  297. TmpRef.base := taicpu(p).oper[1]^.reg;
  298. TmpRef.ScaleFactor := 2;
  299. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  300. end;
  301. InsertLLItem(asml,p.previous, p.next, hp1);
  302. p.free;
  303. p := tai(hp1.next);
  304. end
  305. end
  306. end;
  307. end;
  308. end;
  309. A_SAR, A_SHR:
  310. {changes the code sequence
  311. shr/sar const1, x
  312. shl const2, x
  313. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  314. begin
  315. if GetNextInstruction(p, hp1) and
  316. (tai(hp1).typ = ait_instruction) and
  317. (taicpu(hp1).opcode = A_SHL) and
  318. (taicpu(p).oper[0]^.typ = top_const) and
  319. (taicpu(hp1).oper[0]^.typ = top_const) and
  320. (taicpu(hp1).opsize = taicpu(p).opsize) and
  321. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
  322. OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
  323. if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
  324. not(CS_LittleSize in aktglobalswitches) then
  325. { shr/sar const1, %reg
  326. shl const2, %reg
  327. with const1 > const2 }
  328. begin
  329. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  330. taicpu(hp1).opcode := A_AND;
  331. l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
  332. case taicpu(p).opsize Of
  333. S_L: taicpu(hp1).LoadConst(0,l Xor aint($ffffffff));
  334. S_B: taicpu(hp1).LoadConst(0,l Xor $ff);
  335. S_W: taicpu(hp1).LoadConst(0,l Xor $ffff);
  336. end;
  337. end
  338. else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
  339. not(CS_LittleSize in aktglobalswitches) then
  340. { shr/sar const1, %reg
  341. shl const2, %reg
  342. with const1 < const2 }
  343. begin
  344. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
  345. taicpu(p).opcode := A_AND;
  346. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  347. case taicpu(p).opsize Of
  348. S_L: taicpu(p).LoadConst(0,l Xor aint($ffffffff));
  349. S_B: taicpu(p).LoadConst(0,l Xor $ff);
  350. S_W: taicpu(p).LoadConst(0,l Xor $ffff);
  351. end;
  352. end
  353. else
  354. { shr/sar const1, %reg
  355. shl const2, %reg
  356. with const1 = const2 }
  357. if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
  358. begin
  359. taicpu(p).opcode := A_AND;
  360. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  361. case taicpu(p).opsize Of
  362. S_B: taicpu(p).LoadConst(0,l Xor $ff);
  363. S_W: taicpu(p).LoadConst(0,l Xor $ffff);
  364. S_L: taicpu(p).LoadConst(0,l Xor aint($ffffffff));
  365. end;
  366. asml.remove(hp1);
  367. hp1.free;
  368. end;
  369. end;
  370. A_XOR:
  371. if (taicpu(p).oper[0]^.typ = top_reg) and
  372. (taicpu(p).oper[1]^.typ = top_reg) and
  373. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  374. { temporarily change this to 'mov reg,0' to make it easier }
  375. { for the CSE. Will be changed back in pass 2 }
  376. begin
  377. taicpu(p).opcode := A_MOV;
  378. taicpu(p).loadconst(0,0);
  379. end;
  380. end;
  381. end;
  382. end;
  383. p := tai(p.next)
  384. end;
  385. end;
  386. procedure PeepHoleOptPass1(Asml: taasmoutput; BlockStart, BlockEnd: tai);
  387. {First pass of peepholeoptimizations}
  388. var
  389. l : longint;
  390. p,hp1,hp2 : tai;
  391. hp3,hp4: tai;
  392. TmpRef: TReference;
  393. UsedRegs, TmpUsedRegs: TRegSet;
  394. TmpBool1, TmpBool2: Boolean;
  395. function SkipLabels(hp: tai; var hp2: tai): boolean;
  396. {skips all labels and returns the next "real" instruction}
  397. begin
  398. while assigned(hp.next) and
  399. (tai(hp.next).typ in SkipInstr + [ait_label,ait_align]) Do
  400. hp := tai(hp.next);
  401. if assigned(hp.next) then
  402. begin
  403. SkipLabels := True;
  404. hp2 := tai(hp.next)
  405. end
  406. else
  407. begin
  408. hp2 := hp;
  409. SkipLabels := False
  410. end;
  411. end;
  412. function GetFinalDestination(asml: taasmoutput; hp: taicpu; level: longint): boolean;
  413. {traces sucessive jumps to their final destination and sets it, e.g.
  414. je l1 je l3
  415. <code> <code>
  416. l1: becomes l1:
  417. je l2 je l3
  418. <code> <code>
  419. l2: l2:
  420. jmp l3 jmp l3
  421. the level parameter denotes how deeep we have already followed the jump,
  422. to avoid endless loops with constructs such as "l5: ; jmp l5" }
  423. var p1, p2: tai;
  424. l: tasmlabel;
  425. function FindAnyLabel(hp: tai; var l: tasmlabel): Boolean;
  426. begin
  427. FindAnyLabel := false;
  428. while assigned(hp.next) and
  429. (tai(hp.next).typ in (SkipInstr+[ait_align])) Do
  430. hp := tai(hp.next);
  431. if assigned(hp.next) and
  432. (tai(hp.next).typ = ait_label) then
  433. begin
  434. FindAnyLabel := true;
  435. l := tai_label(hp.next).l;
  436. end
  437. end;
  438. begin
  439. GetfinalDestination := false;
  440. if level > 20 then
  441. exit;
  442. p1 := dfa.getlabelwithsym(tasmlabel(hp.oper[0]^.ref^.symbol));
  443. if assigned(p1) then
  444. begin
  445. SkipLabels(p1,p1);
  446. if (tai(p1).typ = ait_instruction) and
  447. (taicpu(p1).is_jmp) then
  448. if { the next instruction after the label where the jump hp arrives}
  449. { is unconditional or of the same type as hp, so continue }
  450. (taicpu(p1).condition in [C_None,hp.condition]) or
  451. { the next instruction after the label where the jump hp arrives}
  452. { is the opposite of hp (so this one is never taken), but after }
  453. { that one there is a branch that will be taken, so perform a }
  454. { little hack: set p1 equal to this instruction (that's what the}
  455. { last SkipLabels is for, only works with short bool evaluation)}
  456. ((taicpu(p1).condition = inverse_cond(hp.condition)) and
  457. SkipLabels(p1,p2) and
  458. (p2.typ = ait_instruction) and
  459. (taicpu(p2).is_jmp) and
  460. (taicpu(p2).condition in [C_None,hp.condition]) and
  461. SkipLabels(p1,p1)) then
  462. begin
  463. { quick check for loops of the form "l5: ; jmp l5 }
  464. if (tasmlabel(taicpu(p1).oper[0]^.ref^.symbol).labelnr =
  465. tasmlabel(hp.oper[0]^.ref^.symbol).labelnr) then
  466. exit;
  467. if not GetFinalDestination(asml, taicpu(p1),succ(level)) then
  468. exit;
  469. tasmlabel(hp.oper[0]^.ref^.symbol).decrefs;
  470. hp.oper[0]^.ref^.symbol:=taicpu(p1).oper[0]^.ref^.symbol;
  471. tasmlabel(hp.oper[0]^.ref^.symbol).increfs;
  472. end
  473. else
  474. if (taicpu(p1).condition = inverse_cond(hp.condition)) then
  475. if not FindAnyLabel(p1,l) then
  476. begin
  477. {$ifdef finaldestdebug}
  478. insertllitem(asml,p1,p1.next,tai_comment.Create(
  479. strpnew('previous label inserted'))));
  480. {$endif finaldestdebug}
  481. objectlibrary.getjumplabel(l);
  482. insertllitem(asml,p1,p1.next,tai_label.Create(l));
  483. tasmlabel(taicpu(hp).oper[0]^.ref^.symbol).decrefs;
  484. hp.oper[0]^.ref^.symbol := l;
  485. l.increfs;
  486. { this won't work, since the new label isn't in the labeltable }
  487. { so it will fail the rangecheck. Labeltable should become a }
  488. { hashtable to support this: }
  489. { GetFinalDestination(asml, hp); }
  490. end
  491. else
  492. begin
  493. {$ifdef finaldestdebug}
  494. insertllitem(asml,p1,p1.next,tai_comment.Create(
  495. strpnew('next label reused'))));
  496. {$endif finaldestdebug}
  497. l.increfs;
  498. hp.oper[0]^.ref^.symbol := l;
  499. if not GetFinalDestination(asml, hp,succ(level)) then
  500. exit;
  501. end;
  502. end;
  503. GetFinalDestination := true;
  504. end;
  505. function DoSubAddOpt(var p: tai): Boolean;
  506. begin
  507. DoSubAddOpt := False;
  508. if GetLastInstruction(p, hp1) and
  509. (hp1.typ = ait_instruction) and
  510. (taicpu(hp1).opsize = taicpu(p).opsize) then
  511. case taicpu(hp1).opcode Of
  512. A_DEC:
  513. if (taicpu(hp1).oper[0]^.typ = top_reg) and
  514. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  515. begin
  516. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val+1);
  517. asml.remove(hp1);
  518. hp1.free;
  519. end;
  520. A_SUB:
  521. if (taicpu(hp1).oper[0]^.typ = top_const) and
  522. (taicpu(hp1).oper[1]^.typ = top_reg) and
  523. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  524. begin
  525. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
  526. asml.remove(hp1);
  527. hp1.free;
  528. end;
  529. A_ADD:
  530. if (taicpu(hp1).oper[0]^.typ = top_const) and
  531. (taicpu(hp1).oper[1]^.typ = top_reg) and
  532. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  533. begin
  534. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  535. asml.remove(hp1);
  536. hp1.free;
  537. if (taicpu(p).oper[0]^.val = 0) then
  538. begin
  539. hp1 := tai(p.next);
  540. asml.remove(p);
  541. p.free;
  542. if not GetLastInstruction(hp1, p) then
  543. p := hp1;
  544. DoSubAddOpt := True;
  545. end
  546. end;
  547. end;
  548. end;
  549. begin
  550. p := BlockStart;
  551. UsedRegs := [];
  552. while (p <> BlockEnd) Do
  553. begin
  554. UpDateUsedRegs(UsedRegs, tai(p.next));
  555. case p.Typ Of
  556. ait_instruction:
  557. begin
  558. { Handle Jmp Optimizations }
  559. if taicpu(p).is_jmp then
  560. begin
  561. {the following if-block removes all code between a jmp and the next label,
  562. because it can never be executed}
  563. if (taicpu(p).opcode = A_JMP) then
  564. begin
  565. while GetNextInstruction(p, hp1) and
  566. (hp1.typ <> ait_label) do
  567. if not(hp1.typ in ([ait_label,ait_align]+skipinstr)) then
  568. begin
  569. asml.remove(hp1);
  570. hp1.free;
  571. end
  572. else break;
  573. end;
  574. { remove jumps to a label coming right after them }
  575. if GetNextInstruction(p, hp1) then
  576. begin
  577. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp1) and
  578. {$warning FIXME removing the first instruction fails}
  579. (p<>blockstart) then
  580. begin
  581. hp2:=tai(hp1.next);
  582. asml.remove(p);
  583. p.free;
  584. p:=hp2;
  585. continue;
  586. end
  587. else
  588. begin
  589. if hp1.typ = ait_label then
  590. SkipLabels(hp1,hp1);
  591. if (tai(hp1).typ=ait_instruction) and
  592. (taicpu(hp1).opcode=A_JMP) and
  593. GetNextInstruction(hp1, hp2) and
  594. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp2) then
  595. begin
  596. if taicpu(p).opcode=A_Jcc then
  597. begin
  598. taicpu(p).condition:=inverse_cond(taicpu(p).condition);
  599. tai_label(hp2).l.decrefs;
  600. taicpu(p).oper[0]^.ref^.symbol:=taicpu(hp1).oper[0]^.ref^.symbol;
  601. taicpu(p).oper[0]^.ref^.symbol.increfs;
  602. asml.remove(hp1);
  603. hp1.free;
  604. GetFinalDestination(asml, taicpu(p),0);
  605. end
  606. else
  607. begin
  608. GetFinalDestination(asml, taicpu(p),0);
  609. p:=tai(p.next);
  610. continue;
  611. end;
  612. end
  613. else
  614. GetFinalDestination(asml, taicpu(p),0);
  615. end;
  616. end;
  617. end
  618. else
  619. { All other optimizes }
  620. begin
  621. for l := 0 to taicpu(p).ops-1 Do
  622. if (taicpu(p).oper[l]^.typ = top_ref) then
  623. With taicpu(p).oper[l]^.ref^ Do
  624. begin
  625. if (base = NR_NO) and
  626. (index <> NR_NO) and
  627. (scalefactor in [0,1]) then
  628. begin
  629. base := index;
  630. index := NR_NO
  631. end
  632. end;
  633. case taicpu(p).opcode Of
  634. A_AND:
  635. begin
  636. if (taicpu(p).oper[0]^.typ = top_const) and
  637. (taicpu(p).oper[1]^.typ = top_reg) and
  638. GetNextInstruction(p, hp1) and
  639. (tai(hp1).typ = ait_instruction) and
  640. (taicpu(hp1).opcode = A_AND) and
  641. (taicpu(hp1).oper[0]^.typ = top_const) and
  642. (taicpu(hp1).oper[1]^.typ = top_reg) and
  643. (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) then
  644. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  645. begin
  646. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
  647. asml.remove(hp1);
  648. hp1.free;
  649. end
  650. else
  651. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  652. jump, but only if it's a conditional jump (PFV) }
  653. if (taicpu(p).oper[1]^.typ = top_reg) and
  654. GetNextInstruction(p, hp1) and
  655. (hp1.typ = ait_instruction) and
  656. (taicpu(hp1).is_jmp) and
  657. (taicpu(hp1).opcode<>A_JMP) and
  658. not(getsupreg(taicpu(p).oper[1]^.reg) in UsedRegs) then
  659. taicpu(p).opcode := A_TEST;
  660. end;
  661. A_CMP:
  662. begin
  663. if (taicpu(p).oper[0]^.typ = top_const) and
  664. (taicpu(p).oper[1]^.typ in [top_reg,top_ref]) and
  665. (taicpu(p).oper[0]^.val = 0) and
  666. GetNextInstruction(p, hp1) and
  667. (hp1.typ = ait_instruction) and
  668. (taicpu(hp1).is_jmp) and
  669. (taicpu(hp1).opcode=A_Jcc) and
  670. (taicpu(hp1).condition in [C_LE,C_BE]) and
  671. GetNextInstruction(hp1,hp2) and
  672. (hp2.typ = ait_instruction) and
  673. (taicpu(hp2).opcode = A_DEC) and
  674. OpsEqual(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  675. GetNextInstruction(hp2, hp3) and
  676. (hp3.typ = ait_instruction) and
  677. (taicpu(hp3).is_jmp) and
  678. (taicpu(hp3).opcode = A_JMP) and
  679. GetNextInstruction(hp3, hp4) and
  680. FindLabel(tasmlabel(taicpu(hp1).oper[0]^.ref^.symbol),hp4) then
  681. begin
  682. taicpu(hp2).Opcode := A_SUB;
  683. taicpu(hp2).Loadoper(1,taicpu(hp2).oper[0]^);
  684. taicpu(hp2).LoadConst(0,1);
  685. taicpu(hp2).ops:=2;
  686. taicpu(hp3).Opcode := A_Jcc;
  687. case taicpu(hp1).condition of
  688. C_LE: taicpu(hp3).condition := C_GE;
  689. C_BE: taicpu(hp3).condition := C_AE;
  690. end;
  691. asml.remove(p);
  692. asml.remove(hp1);
  693. p.free;
  694. hp1.free;
  695. p := hp2;
  696. continue;
  697. end
  698. end;
  699. A_FLD:
  700. begin
  701. if (taicpu(p).oper[0]^.typ = top_reg) and
  702. GetNextInstruction(p, hp1) and
  703. (hp1.typ = Ait_Instruction) and
  704. (taicpu(hp1).oper[0]^.typ = top_reg) and
  705. (taicpu(hp1).oper[1]^.typ = top_reg) and
  706. (taicpu(hp1).oper[0]^.reg = NR_ST) and
  707. (taicpu(hp1).oper[1]^.reg = NR_ST1) then
  708. { change to
  709. fld reg fxxx reg,st
  710. fxxxp st, st1 (hp1)
  711. Remark: non commutative operations must be reversed!
  712. }
  713. begin
  714. case taicpu(hp1).opcode Of
  715. A_FMULP,A_FADDP,
  716. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  717. begin
  718. case taicpu(hp1).opcode Of
  719. A_FADDP: taicpu(hp1).opcode := A_FADD;
  720. A_FMULP: taicpu(hp1).opcode := A_FMUL;
  721. A_FSUBP: taicpu(hp1).opcode := A_FSUBR;
  722. A_FSUBRP: taicpu(hp1).opcode := A_FSUB;
  723. A_FDIVP: taicpu(hp1).opcode := A_FDIVR;
  724. A_FDIVRP: taicpu(hp1).opcode := A_FDIV;
  725. end;
  726. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  727. taicpu(hp1).oper[1]^.reg := NR_ST;
  728. asml.remove(p);
  729. p.free;
  730. p := hp1;
  731. continue;
  732. end;
  733. end;
  734. end
  735. else
  736. if (taicpu(p).oper[0]^.typ = top_ref) and
  737. GetNextInstruction(p, hp2) and
  738. (hp2.typ = Ait_Instruction) and
  739. (taicpu(hp2).ops = 2) and
  740. (taicpu(hp2).oper[0]^.typ = top_reg) and
  741. (taicpu(hp2).oper[1]^.typ = top_reg) and
  742. (taicpu(p).opsize in [S_FS, S_FL]) and
  743. (taicpu(hp2).oper[0]^.reg = NR_ST) and
  744. (taicpu(hp2).oper[1]^.reg = NR_ST1) then
  745. if GetLastInstruction(p, hp1) and
  746. (hp1.typ = Ait_Instruction) and
  747. ((taicpu(hp1).opcode = A_FLD) or
  748. (taicpu(hp1).opcode = A_FST)) and
  749. (taicpu(hp1).opsize = taicpu(p).opsize) and
  750. (taicpu(hp1).oper[0]^.typ = top_ref) and
  751. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  752. if ((taicpu(hp2).opcode = A_FMULP) or
  753. (taicpu(hp2).opcode = A_FADDP)) then
  754. { change to
  755. fld/fst mem1 (hp1) fld/fst mem1
  756. fld mem1 (p) fadd/
  757. faddp/ fmul st, st
  758. fmulp st, st1 (hp2) }
  759. begin
  760. asml.remove(p);
  761. p.free;
  762. p := hp1;
  763. if (taicpu(hp2).opcode = A_FADDP) then
  764. taicpu(hp2).opcode := A_FADD
  765. else
  766. taicpu(hp2).opcode := A_FMUL;
  767. taicpu(hp2).oper[1]^.reg := NR_ST;
  768. end
  769. else
  770. { change to
  771. fld/fst mem1 (hp1) fld/fst mem1
  772. fld mem1 (p) fld st}
  773. begin
  774. taicpu(p).changeopsize(S_FL);
  775. taicpu(p).loadreg(0,NR_ST);
  776. end
  777. else
  778. begin
  779. case taicpu(hp2).opcode Of
  780. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  781. { change to
  782. fld/fst mem1 (hp1) fld/fst mem1
  783. fld mem2 (p) fxxx mem2
  784. fxxxp st, st1 (hp2) }
  785. begin
  786. case taicpu(hp2).opcode Of
  787. A_FADDP: taicpu(p).opcode := A_FADD;
  788. A_FMULP: taicpu(p).opcode := A_FMUL;
  789. A_FSUBP: taicpu(p).opcode := A_FSUBR;
  790. A_FSUBRP: taicpu(p).opcode := A_FSUB;
  791. A_FDIVP: taicpu(p).opcode := A_FDIVR;
  792. A_FDIVRP: taicpu(p).opcode := A_FDIV;
  793. end;
  794. asml.remove(hp2);
  795. hp2.free;
  796. end
  797. end
  798. end
  799. end;
  800. A_FSTP,A_FISTP:
  801. if doFpuLoadStoreOpt(asmL,p) then
  802. continue;
  803. A_LEA:
  804. begin
  805. {removes seg register prefixes from LEA operations, as they
  806. don't do anything}
  807. taicpu(p).oper[0]^.ref^.Segment := NR_NO;
  808. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  809. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  810. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX..RS_ESP]) and
  811. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  812. (not(Assigned(taicpu(p).oper[0]^.ref^.Symbol))) then
  813. if (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  814. (taicpu(p).oper[0]^.ref^.offset = 0) then
  815. begin
  816. hp1 := taicpu.op_reg_reg(A_MOV, S_L,taicpu(p).oper[0]^.ref^.base,
  817. taicpu(p).oper[1]^.reg);
  818. InsertLLItem(asml,p.previous,p.next, hp1);
  819. p.free;
  820. p := hp1;
  821. continue;
  822. end
  823. else if (taicpu(p).oper[0]^.ref^.offset = 0) then
  824. begin
  825. hp1 := tai(p.Next);
  826. asml.remove(p);
  827. p.free;
  828. p := hp1;
  829. continue;
  830. end
  831. else
  832. with taicpu(p).oper[0]^.ref^ do
  833. if (base = taicpu(p).oper[1]^.reg) then
  834. begin
  835. l := offset;
  836. if (l=1) then
  837. begin
  838. taicpu(p).opcode := A_INC;
  839. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  840. taicpu(p).ops := 1
  841. end
  842. else if (l=-1) then
  843. begin
  844. taicpu(p).opcode := A_DEC;
  845. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  846. taicpu(p).ops := 1;
  847. end
  848. else
  849. begin
  850. taicpu(p).opcode := A_ADD;
  851. taicpu(p).loadconst(0,l);
  852. end;
  853. end;
  854. end;
  855. A_MOV:
  856. begin
  857. TmpUsedRegs := UsedRegs;
  858. if (taicpu(p).oper[1]^.typ = top_reg) and
  859. (getsupreg(taicpu(p).oper[1]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX, RS_ESI, RS_EDI]) and
  860. GetNextInstruction(p, hp1) and
  861. (tai(hp1).typ = ait_instruction) and
  862. (taicpu(hp1).opcode = A_MOV) and
  863. (taicpu(hp1).oper[0]^.typ = top_reg) and
  864. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  865. begin
  866. {we have "mov x, %treg; mov %treg, y}
  867. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  868. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  869. case taicpu(p).oper[0]^.typ Of
  870. top_reg:
  871. begin
  872. { change "mov %reg, %treg; mov %treg, y"
  873. to "mov %reg, y" }
  874. taicpu(p).LoadOper(1,taicpu(hp1).oper[1]^);
  875. asml.remove(hp1);
  876. hp1.free;
  877. continue;
  878. end;
  879. top_ref:
  880. if (taicpu(hp1).oper[1]^.typ = top_reg) then
  881. begin
  882. { change "mov mem, %treg; mov %treg, %reg"
  883. to "mov mem, %reg" }
  884. taicpu(p).Loadoper(1,taicpu(hp1).oper[1]^);
  885. asml.remove(hp1);
  886. hp1.free;
  887. continue;
  888. end;
  889. end
  890. end
  891. else
  892. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  893. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  894. penalty}
  895. if (taicpu(p).oper[0]^.typ = top_reg) and
  896. (taicpu(p).oper[1]^.typ = top_reg) and
  897. GetNextInstruction(p,hp1) and
  898. (tai(hp1).typ = ait_instruction) and
  899. (taicpu(hp1).ops >= 1) and
  900. (taicpu(hp1).oper[0]^.typ = top_reg) and
  901. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  902. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  903. begin
  904. if ((taicpu(hp1).opcode = A_OR) or
  905. (taicpu(hp1).opcode = A_TEST)) and
  906. (taicpu(hp1).oper[1]^.typ = top_reg) and
  907. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
  908. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  909. begin
  910. TmpUsedRegs := UsedRegs;
  911. { reg1 will be used after the first instruction, }
  912. { so update the allocation info }
  913. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  914. if GetNextInstruction(hp1, hp2) and
  915. (hp2.typ = ait_instruction) and
  916. taicpu(hp2).is_jmp and
  917. not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, hp1, TmpUsedRegs)) then
  918. { change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  919. "test %reg1, %reg1; jxx" }
  920. begin
  921. taicpu(hp1).Loadoper(0,taicpu(p).oper[0]^);
  922. taicpu(hp1).Loadoper(1,taicpu(p).oper[0]^);
  923. asml.remove(p);
  924. p.free;
  925. p := hp1;
  926. continue
  927. end
  928. else
  929. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  930. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  931. begin
  932. taicpu(hp1).Loadoper(0,taicpu(p).oper[0]^);
  933. taicpu(hp1).Loadoper(1,taicpu(p).oper[0]^);
  934. end;
  935. end
  936. { else
  937. if (taicpu(p.next)^.opcode
  938. in [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  939. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  940. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  941. end
  942. else
  943. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  944. x >= RetOffset) as it doesn't do anything (it writes either to a
  945. parameter or to the temporary storage room for the function
  946. result)}
  947. if GetNextInstruction(p, hp1) and
  948. (tai(hp1).typ = ait_instruction) then
  949. if ((taicpu(hp1).opcode = A_LEAVE) or
  950. (taicpu(hp1).opcode = A_RET)) and
  951. (taicpu(p).oper[1]^.typ = top_ref) and
  952. (taicpu(p).oper[1]^.ref^.base = current_procinfo.FramePointer) and
  953. not(assigned(current_procinfo.procdef.funcretsym) and
  954. (taicpu(p).oper[1]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  955. (taicpu(p).oper[1]^.ref^.index = NR_NO) and
  956. (taicpu(p).oper[0]^.typ = top_reg) then
  957. begin
  958. asml.remove(p);
  959. p.free;
  960. p := hp1;
  961. RemoveLastDeallocForFuncRes(asmL,p);
  962. end
  963. else
  964. if (taicpu(p).oper[0]^.typ = top_reg) and
  965. (taicpu(p).oper[1]^.typ = top_ref) and
  966. (taicpu(p).opsize = taicpu(hp1).opsize) and
  967. (taicpu(hp1).opcode = A_CMP) and
  968. (taicpu(hp1).oper[1]^.typ = top_ref) and
  969. RefsEqual(taicpu(p).oper[1]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  970. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  971. begin
  972. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  973. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  974. end;
  975. { Next instruction is also a MOV ? }
  976. if GetNextInstruction(p, hp1) and
  977. (tai(hp1).typ = ait_instruction) and
  978. (taicpu(hp1).opcode = A_MOV) and
  979. (taicpu(hp1).opsize = taicpu(p).opsize) then
  980. begin
  981. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  982. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  983. {mov reg1, mem1 or mov mem1, reg1
  984. mov mem2, reg2 mov reg2, mem2}
  985. begin
  986. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  987. {mov reg1, mem1 or mov mem1, reg1
  988. mov mem2, reg1 mov reg2, mem1}
  989. begin
  990. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  991. { Removes the second statement from
  992. mov reg1, mem1/reg2
  993. mov mem1/reg2, reg1 }
  994. begin
  995. if (taicpu(p).oper[0]^.typ = top_reg) then
  996. AllocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  997. asml.remove(hp1);
  998. hp1.free;
  999. end
  1000. else
  1001. begin
  1002. TmpUsedRegs := UsedRegs;
  1003. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1004. if (taicpu(p).oper[1]^.typ = top_ref) and
  1005. { mov reg1, mem1
  1006. mov mem2, reg1 }
  1007. (taicpu(hp1).oper[0]^.ref^.refaddr = addr_no) and
  1008. GetNextInstruction(hp1, hp2) and
  1009. (hp2.typ = ait_instruction) and
  1010. (taicpu(hp2).opcode = A_CMP) and
  1011. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1012. (taicpu(hp2).oper[0]^.typ = TOp_Ref) and
  1013. (taicpu(hp2).oper[1]^.typ = TOp_Reg) and
  1014. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(p).oper[1]^.ref^) and
  1015. (taicpu(hp2).oper[1]^.reg= taicpu(p).oper[0]^.reg) and
  1016. not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs)) then
  1017. { change to
  1018. mov reg1, mem1 mov reg1, mem1
  1019. mov mem2, reg1 cmp reg1, mem2
  1020. cmp mem1, reg1 }
  1021. begin
  1022. asml.remove(hp2);
  1023. hp2.free;
  1024. taicpu(hp1).opcode := A_CMP;
  1025. taicpu(hp1).loadref(1,taicpu(hp1).oper[0]^.ref^);
  1026. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  1027. end;
  1028. end;
  1029. end
  1030. else
  1031. begin
  1032. tmpUsedRegs := UsedRegs;
  1033. if GetNextInstruction(hp1, hp2) and
  1034. (taicpu(p).oper[0]^.typ = top_ref) and
  1035. (taicpu(p).oper[1]^.typ = top_reg) and
  1036. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1037. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  1038. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1039. (tai(hp2).typ = ait_instruction) and
  1040. (taicpu(hp2).opcode = A_MOV) and
  1041. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1042. (taicpu(hp2).oper[1]^.typ = top_reg) and
  1043. (taicpu(hp2).oper[0]^.typ = top_ref) and
  1044. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1045. if not regInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^) and
  1046. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,tmpUsedRegs)) then
  1047. { mov mem1, %reg1
  1048. mov %reg1, mem2
  1049. mov mem2, reg2
  1050. to:
  1051. mov mem1, reg2
  1052. mov reg2, mem2}
  1053. begin
  1054. AllocRegBetween(asmL,taicpu(hp2).oper[1]^.reg,p,hp2,usedregs);
  1055. taicpu(p).Loadoper(1,taicpu(hp2).oper[1]^);
  1056. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  1057. asml.remove(hp2);
  1058. hp2.free;
  1059. end
  1060. else
  1061. if (taicpu(p).oper[1]^.reg <> taicpu(hp2).oper[1]^.reg) and
  1062. not(RegInRef(getsupreg(taicpu(p).oper[1]^.reg),taicpu(p).oper[0]^.ref^)) and
  1063. not(RegInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^)) then
  1064. { mov mem1, reg1 mov mem1, reg1
  1065. mov reg1, mem2 mov reg1, mem2
  1066. mov mem2, reg2 mov mem2, reg1
  1067. to: to:
  1068. mov mem1, reg1 mov mem1, reg1
  1069. mov mem1, reg2 mov reg1, mem2
  1070. mov reg1, mem2
  1071. or (if mem1 depends on reg1
  1072. and/or if mem2 depends on reg2)
  1073. to:
  1074. mov mem1, reg1
  1075. mov reg1, mem2
  1076. mov reg1, reg2
  1077. }
  1078. begin
  1079. taicpu(hp1).LoadRef(0,taicpu(p).oper[0]^.ref^);
  1080. taicpu(hp1).LoadReg(1,taicpu(hp2).oper[1]^.reg);
  1081. taicpu(hp2).LoadRef(1,taicpu(hp2).oper[0]^.ref^);
  1082. taicpu(hp2).LoadReg(0,taicpu(p).oper[1]^.reg);
  1083. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1084. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  1085. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1086. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.base,p,hp2,usedregs);
  1087. if (taicpu(p).oper[0]^.ref^.index <> NR_NO) and
  1088. (getsupreg(taicpu(p).oper[0]^.ref^.index) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1089. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.index,p,hp2,usedregs);
  1090. end
  1091. else
  1092. if (taicpu(hp1).Oper[0]^.reg <> taicpu(hp2).Oper[1]^.reg) then
  1093. begin
  1094. taicpu(hp2).LoadReg(0,taicpu(hp1).Oper[0]^.reg);
  1095. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1096. end
  1097. else
  1098. begin
  1099. asml.remove(hp2);
  1100. hp2.free;
  1101. end
  1102. end
  1103. end
  1104. else
  1105. (* {movl [mem1],reg1
  1106. movl [mem1],reg2
  1107. to:
  1108. movl [mem1],reg1
  1109. movl reg1,reg2 }
  1110. if (taicpu(p).oper[0]^.typ = top_ref) and
  1111. (taicpu(p).oper[1]^.typ = top_reg) and
  1112. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1113. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1114. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1115. RefsEqual(TReference(taicpu(p).oper[0]^^),taicpu(hp1).oper[0]^^.ref^) and
  1116. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.base) and
  1117. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.index) then
  1118. taicpu(hp1).LoadReg(0,taicpu(p).oper[1]^.reg)
  1119. else*)
  1120. { movl const1,[mem1]
  1121. movl [mem1],reg1
  1122. to:
  1123. movl const1,reg1
  1124. movl reg1,[mem1] }
  1125. if (taicpu(p).oper[0]^.typ = top_const) and
  1126. (taicpu(p).oper[1]^.typ = top_ref) and
  1127. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1128. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1129. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1130. RefsEqual(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.ref^) then
  1131. begin
  1132. allocregbetween(asml,taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1133. taicpu(hp1).LoadReg(0,taicpu(hp1).oper[1]^.reg);
  1134. taicpu(hp1).LoadRef(1,taicpu(p).oper[1]^.ref^);
  1135. taicpu(p).LoadReg(1,taicpu(hp1).oper[0]^.reg);
  1136. end
  1137. end;
  1138. end;
  1139. A_MOVZX:
  1140. begin
  1141. {removes superfluous And's after movzx's}
  1142. if (taicpu(p).oper[1]^.typ = top_reg) and
  1143. GetNextInstruction(p, hp1) and
  1144. (tai(hp1).typ = ait_instruction) and
  1145. (taicpu(hp1).opcode = A_AND) and
  1146. (taicpu(hp1).oper[0]^.typ = top_const) and
  1147. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1148. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1149. case taicpu(p).opsize Of
  1150. S_BL, S_BW:
  1151. if (taicpu(hp1).oper[0]^.val = $ff) then
  1152. begin
  1153. asml.remove(hp1);
  1154. hp1.free;
  1155. end;
  1156. S_WL:
  1157. if (taicpu(hp1).oper[0]^.val = $ffff) then
  1158. begin
  1159. asml.remove(hp1);
  1160. hp1.free;
  1161. end;
  1162. end;
  1163. {changes some movzx constructs to faster synonims (all examples
  1164. are given with eax/ax, but are also valid for other registers)}
  1165. if (taicpu(p).oper[1]^.typ = top_reg) then
  1166. if (taicpu(p).oper[0]^.typ = top_reg) then
  1167. case taicpu(p).opsize of
  1168. S_BW:
  1169. begin
  1170. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1171. not(CS_LittleSize in aktglobalswitches) then
  1172. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1173. begin
  1174. taicpu(p).opcode := A_AND;
  1175. taicpu(p).changeopsize(S_W);
  1176. taicpu(p).LoadConst(0,$ff);
  1177. end
  1178. else if GetNextInstruction(p, hp1) and
  1179. (tai(hp1).typ = ait_instruction) and
  1180. (taicpu(hp1).opcode = A_AND) and
  1181. (taicpu(hp1).oper[0]^.typ = top_const) and
  1182. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1183. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1184. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1185. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1186. begin
  1187. taicpu(p).opcode := A_MOV;
  1188. taicpu(p).changeopsize(S_W);
  1189. setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
  1190. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1191. end;
  1192. end;
  1193. S_BL:
  1194. begin
  1195. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1196. not(CS_LittleSize in aktglobalswitches) then
  1197. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1198. begin
  1199. taicpu(p).opcode := A_AND;
  1200. taicpu(p).changeopsize(S_L);
  1201. taicpu(p).loadconst(0,$ff)
  1202. end
  1203. else if GetNextInstruction(p, hp1) and
  1204. (tai(hp1).typ = ait_instruction) and
  1205. (taicpu(hp1).opcode = A_AND) and
  1206. (taicpu(hp1).oper[0]^.typ = top_const) and
  1207. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1208. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1209. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1210. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1211. begin
  1212. taicpu(p).opcode := A_MOV;
  1213. taicpu(p).changeopsize(S_L);
  1214. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1215. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1216. end
  1217. end;
  1218. S_WL:
  1219. begin
  1220. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1221. not(CS_LittleSize in aktglobalswitches) then
  1222. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1223. begin
  1224. taicpu(p).opcode := A_AND;
  1225. taicpu(p).changeopsize(S_L);
  1226. taicpu(p).LoadConst(0,$ffff);
  1227. end
  1228. else if GetNextInstruction(p, hp1) and
  1229. (tai(hp1).typ = ait_instruction) and
  1230. (taicpu(hp1).opcode = A_AND) and
  1231. (taicpu(hp1).oper[0]^.typ = top_const) and
  1232. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1233. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1234. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1235. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1236. begin
  1237. taicpu(p).opcode := A_MOV;
  1238. taicpu(p).changeopsize(S_L);
  1239. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1240. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1241. end;
  1242. end;
  1243. end
  1244. else if (taicpu(p).oper[0]^.typ = top_ref) then
  1245. begin
  1246. if GetNextInstruction(p, hp1) and
  1247. (tai(hp1).typ = ait_instruction) and
  1248. (taicpu(hp1).opcode = A_AND) and
  1249. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1250. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1251. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1252. begin
  1253. taicpu(p).opcode := A_MOV;
  1254. case taicpu(p).opsize Of
  1255. S_BL:
  1256. begin
  1257. taicpu(p).changeopsize(S_L);
  1258. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1259. end;
  1260. S_WL:
  1261. begin
  1262. taicpu(p).changeopsize(S_L);
  1263. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1264. end;
  1265. S_BW:
  1266. begin
  1267. taicpu(p).changeopsize(S_W);
  1268. taicpu(hp1).LoadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1269. end;
  1270. end;
  1271. end;
  1272. end;
  1273. end;
  1274. (* should not be generated anymore by the current code generator
  1275. A_POP:
  1276. begin
  1277. if target_info.system=system_i386_go32v2 then
  1278. begin
  1279. { Transform a series of pop/pop/pop/push/push/push to }
  1280. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1281. { because I'm not sure whether they can cope with }
  1282. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1283. { such a problem when using esp as frame pointer (JM) }
  1284. if (taicpu(p).oper[0]^.typ = top_reg) then
  1285. begin
  1286. hp1 := p;
  1287. hp2 := p;
  1288. l := 0;
  1289. while getNextInstruction(hp1,hp1) and
  1290. (hp1.typ = ait_instruction) and
  1291. (taicpu(hp1).opcode = A_POP) and
  1292. (taicpu(hp1).oper[0]^.typ = top_reg) do
  1293. begin
  1294. hp2 := hp1;
  1295. inc(l,4);
  1296. end;
  1297. getLastInstruction(p,hp3);
  1298. l1 := 0;
  1299. while (hp2 <> hp3) and
  1300. assigned(hp1) and
  1301. (hp1.typ = ait_instruction) and
  1302. (taicpu(hp1).opcode = A_PUSH) and
  1303. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1304. (taicpu(hp1).oper[0]^.reg.enum = taicpu(hp2).oper[0]^.reg.enum) do
  1305. begin
  1306. { change it to a two op operation }
  1307. taicpu(hp2).oper[1]^.typ:=top_none;
  1308. taicpu(hp2).ops:=2;
  1309. taicpu(hp2).opcode := A_MOV;
  1310. taicpu(hp2).Loadoper(1,taicpu(hp1).oper[0]^);
  1311. reference_reset(tmpref);
  1312. tmpRef.base.enum:=R_INTREGISTER;
  1313. tmpRef.base.number:=NR_STACK_POINTER_REG;
  1314. convert_register_to_enum(tmpref.base);
  1315. tmpRef.offset := l;
  1316. taicpu(hp2).loadRef(0,tmpRef);
  1317. hp4 := hp1;
  1318. getNextInstruction(hp1,hp1);
  1319. asml.remove(hp4);
  1320. hp4.free;
  1321. getLastInstruction(hp2,hp2);
  1322. dec(l,4);
  1323. inc(l1);
  1324. end;
  1325. if l <> -4 then
  1326. begin
  1327. inc(l,4);
  1328. for l1 := l1 downto 1 do
  1329. begin
  1330. getNextInstruction(hp2,hp2);
  1331. dec(taicpu(hp2).oper[0]^.ref^.offset,l);
  1332. end
  1333. end
  1334. end
  1335. end
  1336. else
  1337. begin
  1338. if (taicpu(p).oper[0]^.typ = top_reg) and
  1339. GetNextInstruction(p, hp1) and
  1340. (tai(hp1).typ=ait_instruction) and
  1341. (taicpu(hp1).opcode=A_PUSH) and
  1342. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1343. (taicpu(hp1).oper[0]^.reg.enum=taicpu(p).oper[0]^.reg.enum) then
  1344. begin
  1345. { change it to a two op operation }
  1346. taicpu(p).oper[1]^.typ:=top_none;
  1347. taicpu(p).ops:=2;
  1348. taicpu(p).opcode := A_MOV;
  1349. taicpu(p).Loadoper(1,taicpu(p).oper[0]^);
  1350. reference_reset(tmpref);
  1351. TmpRef.base.enum := R_ESP;
  1352. taicpu(p).LoadRef(0,TmpRef);
  1353. asml.remove(hp1);
  1354. hp1.free;
  1355. end;
  1356. end;
  1357. end;
  1358. *)
  1359. A_PUSH:
  1360. begin
  1361. if (taicpu(p).opsize = S_W) and
  1362. (taicpu(p).oper[0]^.typ = Top_Const) and
  1363. GetNextInstruction(p, hp1) and
  1364. (tai(hp1).typ = ait_instruction) and
  1365. (taicpu(hp1).opcode = A_PUSH) and
  1366. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1367. (taicpu(hp1).opsize = S_W) then
  1368. begin
  1369. taicpu(p).changeopsize(S_L);
  1370. taicpu(p).LoadConst(0,taicpu(p).oper[0]^.val shl 16 + word(taicpu(hp1).oper[0]^.val));
  1371. asml.remove(hp1);
  1372. hp1.free;
  1373. end;
  1374. end;
  1375. A_SHL, A_SAL:
  1376. begin
  1377. if (taicpu(p).oper[0]^.typ = Top_Const) and
  1378. (taicpu(p).oper[1]^.typ = Top_Reg) and
  1379. (taicpu(p).opsize = S_L) and
  1380. (taicpu(p).oper[0]^.val <= 3) then
  1381. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1382. begin
  1383. TmpBool1 := True; {should we check the next instruction?}
  1384. TmpBool2 := False; {have we found an add/sub which could be
  1385. integrated in the lea?}
  1386. reference_reset(tmpref);
  1387. TmpRef.index := taicpu(p).oper[1]^.reg;
  1388. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1389. while TmpBool1 and
  1390. GetNextInstruction(p, hp1) and
  1391. (tai(hp1).typ = ait_instruction) and
  1392. ((((taicpu(hp1).opcode = A_ADD) or
  1393. (taicpu(hp1).opcode = A_SUB)) and
  1394. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1395. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
  1396. (((taicpu(hp1).opcode = A_INC) or
  1397. (taicpu(hp1).opcode = A_DEC)) and
  1398. (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1399. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg))) Do
  1400. begin
  1401. TmpBool1 := False;
  1402. if (taicpu(hp1).oper[0]^.typ = Top_Const) then
  1403. begin
  1404. TmpBool1 := True;
  1405. TmpBool2 := True;
  1406. case taicpu(hp1).opcode of
  1407. A_ADD:
  1408. inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1409. A_SUB:
  1410. dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1411. end;
  1412. asml.remove(hp1);
  1413. hp1.free;
  1414. end
  1415. else
  1416. if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1417. (((taicpu(hp1).opcode = A_ADD) and
  1418. (TmpRef.base = NR_NO)) or
  1419. (taicpu(hp1).opcode = A_INC) or
  1420. (taicpu(hp1).opcode = A_DEC)) then
  1421. begin
  1422. TmpBool1 := True;
  1423. TmpBool2 := True;
  1424. case taicpu(hp1).opcode of
  1425. A_ADD:
  1426. TmpRef.base := taicpu(hp1).oper[0]^.reg;
  1427. A_INC:
  1428. inc(TmpRef.offset);
  1429. A_DEC:
  1430. dec(TmpRef.offset);
  1431. end;
  1432. asml.remove(hp1);
  1433. hp1.free;
  1434. end;
  1435. end;
  1436. if TmpBool2 or
  1437. ((aktoptprocessor < ClassPentium2) and
  1438. (taicpu(p).oper[0]^.val <= 3) and
  1439. not(CS_LittleSize in aktglobalswitches)) then
  1440. begin
  1441. if not(TmpBool2) and
  1442. (taicpu(p).oper[0]^.val = 1) then
  1443. begin
  1444. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1445. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
  1446. end
  1447. else
  1448. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  1449. taicpu(p).oper[1]^.reg);
  1450. InsertLLItem(asml,p.previous, p.next, hp1);
  1451. p.free;
  1452. p := hp1;
  1453. end;
  1454. end
  1455. else
  1456. if (aktoptprocessor < ClassPentium2) and
  1457. (taicpu(p).oper[0]^.typ = top_const) and
  1458. (taicpu(p).oper[1]^.typ = top_reg) then
  1459. if (taicpu(p).oper[0]^.val = 1) then
  1460. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1461. but faster on a 486, and Tairable in both U and V pipes on the Pentium
  1462. (unlike shl, which is only Tairable in the U pipe)}
  1463. begin
  1464. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1465. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  1466. InsertLLItem(asml,p.previous, p.next, hp1);
  1467. p.free;
  1468. p := hp1;
  1469. end
  1470. else if (taicpu(p).opsize = S_L) and
  1471. (taicpu(p).oper[0]^.val<= 3) then
  1472. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1473. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1474. begin
  1475. reference_reset(tmpref);
  1476. TmpRef.index := taicpu(p).oper[1]^.reg;
  1477. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1478. hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
  1479. InsertLLItem(asml,p.previous, p.next, hp1);
  1480. p.free;
  1481. p := hp1;
  1482. end
  1483. end;
  1484. A_SETcc :
  1485. { changes
  1486. setcc (funcres) setcc reg
  1487. movb (funcres), reg to leave/ret
  1488. leave/ret }
  1489. begin
  1490. if (taicpu(p).oper[0]^.typ = top_ref) and
  1491. GetNextInstruction(p, hp1) and
  1492. GetNextInstruction(hp1, hp2) and
  1493. (hp2.typ = ait_instruction) and
  1494. ((taicpu(hp2).opcode = A_LEAVE) or
  1495. (taicpu(hp2).opcode = A_RET)) and
  1496. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  1497. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  1498. not(assigned(current_procinfo.procdef.funcretsym) and
  1499. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  1500. (hp1.typ = ait_instruction) and
  1501. (taicpu(hp1).opcode = A_MOV) and
  1502. (taicpu(hp1).opsize = S_B) and
  1503. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1504. RefsEqual(taicpu(hp1).oper[0]^.ref^, taicpu(p).oper[0]^.ref^) then
  1505. begin
  1506. taicpu(p).LoadReg(0,taicpu(hp1).oper[1]^.reg);
  1507. asml.remove(hp1);
  1508. hp1.free;
  1509. end
  1510. end;
  1511. A_SUB:
  1512. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1513. { * change "sub/add const1, reg" or "dec reg" followed by
  1514. "sub const2, reg" to one "sub ..., reg" }
  1515. begin
  1516. if (taicpu(p).oper[0]^.typ = top_const) and
  1517. (taicpu(p).oper[1]^.typ = top_reg) then
  1518. if (taicpu(p).oper[0]^.val = 2) and
  1519. (taicpu(p).oper[1]^.reg = NR_ESP) and
  1520. { Don't do the sub/push optimization if the sub }
  1521. { comes from setting up the stack frame (JM) }
  1522. (not getLastInstruction(p,hp1) or
  1523. (hp1.typ <> ait_instruction) or
  1524. (taicpu(hp1).opcode <> A_MOV) or
  1525. (taicpu(hp1).oper[0]^.typ <> top_reg) or
  1526. (taicpu(hp1).oper[0]^.reg <> NR_ESP) or
  1527. (taicpu(hp1).oper[1]^.typ <> top_reg) or
  1528. (taicpu(hp1).oper[1]^.reg <> NR_EBP)) then
  1529. begin
  1530. hp1 := tai(p.next);
  1531. while Assigned(hp1) and
  1532. (tai(hp1).typ in [ait_instruction]+SkipInstr) and
  1533. not regReadByInstruction(RS_ESP,hp1) and
  1534. not regModifiedByInstruction(RS_ESP,hp1) do
  1535. hp1 := tai(hp1.next);
  1536. if Assigned(hp1) and
  1537. (tai(hp1).typ = ait_instruction) and
  1538. (taicpu(hp1).opcode = A_PUSH) and
  1539. (taicpu(hp1).opsize = S_W) then
  1540. begin
  1541. taicpu(hp1).changeopsize(S_L);
  1542. if taicpu(hp1).oper[0]^.typ=top_reg then
  1543. setsubreg(taicpu(hp1).oper[0]^.reg,R_SUBWHOLE);
  1544. hp1 := tai(p.next);
  1545. asml.remove(p);
  1546. p.free;
  1547. p := hp1;
  1548. continue
  1549. end;
  1550. if DoSubAddOpt(p) then
  1551. continue;
  1552. end
  1553. else if DoSubAddOpt(p) then
  1554. continue
  1555. end;
  1556. end;
  1557. end; { if is_jmp }
  1558. end;
  1559. end;
  1560. updateUsedRegs(UsedRegs,p);
  1561. p:=tai(p.next);
  1562. end;
  1563. end;
  1564. function isFoldableArithOp(hp1: taicpu; reg: tregister): boolean;
  1565. begin
  1566. isFoldableArithOp := False;
  1567. case hp1.opcode of
  1568. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1569. isFoldableArithOp :=
  1570. ((taicpu(hp1).oper[0]^.typ = top_const) or
  1571. ((taicpu(hp1).oper[0]^.typ = top_reg) and
  1572. (taicpu(hp1).oper[0]^.reg <> reg))) and
  1573. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1574. (taicpu(hp1).oper[1]^.reg = reg);
  1575. A_INC,A_DEC:
  1576. isFoldableArithOp :=
  1577. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1578. (taicpu(hp1).oper[0]^.reg = reg);
  1579. end;
  1580. end;
  1581. procedure PeepHoleOptPass2(asml: taasmoutput; BlockStart, BlockEnd: tai);
  1582. {$ifdef USECMOV}
  1583. function CanBeCMOV(p : tai) : boolean;
  1584. begin
  1585. CanBeCMOV:=assigned(p) and (p.typ=ait_instruction) and
  1586. (taicpu(p).opcode=A_MOV) and
  1587. (taicpu(p).opsize in [S_L,S_W]) and
  1588. ((taicpu(p).oper[0]^.typ = top_reg)
  1589. { we can't use cmov ref,reg because
  1590. ref could be nil and cmov still throws an exception
  1591. if ref=nil but the mov isn't done (FK)
  1592. or ((taicpu(p).oper[0]^.typ = top_ref) and
  1593. (taicpu(p).oper[0]^.ref^.refaddr = addr_no))
  1594. }
  1595. ) and
  1596. (taicpu(p).oper[1]^.typ in [top_reg]);
  1597. end;
  1598. {$endif USECMOV}
  1599. var
  1600. p,hp1,hp2: tai;
  1601. {$ifdef USECMOV}
  1602. l : longint;
  1603. condition : tasmcond;
  1604. hp3: tai;
  1605. {$endif USECMOV}
  1606. UsedRegs, TmpUsedRegs: TRegSet;
  1607. begin
  1608. p := BlockStart;
  1609. UsedRegs := [];
  1610. while (p <> BlockEnd) Do
  1611. begin
  1612. UpdateUsedRegs(UsedRegs, tai(p.next));
  1613. case p.Typ Of
  1614. Ait_Instruction:
  1615. begin
  1616. case taicpu(p).opcode Of
  1617. {$ifdef USECMOV}
  1618. A_Jcc:
  1619. if (aktspecificoptprocessor>=ClassPentium2) then
  1620. begin
  1621. { check for
  1622. jCC xxx
  1623. <several movs>
  1624. xxx:
  1625. }
  1626. l:=0;
  1627. GetNextInstruction(p, hp1);
  1628. while assigned(hp1) and
  1629. CanBeCMOV(hp1) and
  1630. { stop on labels }
  1631. not(hp1.typ=ait_label) do
  1632. begin
  1633. inc(l);
  1634. GetNextInstruction(hp1,hp1);
  1635. end;
  1636. if assigned(hp1) then
  1637. begin
  1638. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1639. begin
  1640. if (l<=4) and (l>0) then
  1641. begin
  1642. condition:=inverse_cond(taicpu(p).condition);
  1643. hp2:=p;
  1644. GetNextInstruction(p,hp1);
  1645. p:=hp1;
  1646. repeat
  1647. taicpu(hp1).opcode:=A_CMOVcc;
  1648. taicpu(hp1).condition:=condition;
  1649. GetNextInstruction(hp1,hp1);
  1650. until not(assigned(hp1)) or
  1651. not(CanBeCMOV(hp1));
  1652. { wait with removing else GetNextInstruction could
  1653. ignore the label if it was the only usage in the
  1654. jump moved away }
  1655. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1656. asml.remove(hp2);
  1657. hp2.free;
  1658. continue;
  1659. end;
  1660. end
  1661. else
  1662. begin
  1663. { check further for
  1664. jCC xxx
  1665. <several movs 1>
  1666. jmp yyy
  1667. xxx:
  1668. <several movs 2>
  1669. yyy:
  1670. }
  1671. { hp2 points to jmp yyy }
  1672. hp2:=hp1;
  1673. { skip hp1 to xxx }
  1674. GetNextInstruction(hp1, hp1);
  1675. if assigned(hp2) and
  1676. assigned(hp1) and
  1677. (l<=3) and
  1678. (hp2.typ=ait_instruction) and
  1679. (taicpu(hp2).is_jmp) and
  1680. (taicpu(hp2).condition=C_None) and
  1681. { real label and jump, no further references to the
  1682. label are allowed }
  1683. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  1684. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1685. begin
  1686. l:=0;
  1687. { skip hp1 to <several moves 2> }
  1688. GetNextInstruction(hp1, hp1);
  1689. while assigned(hp1) and
  1690. CanBeCMOV(hp1) do
  1691. begin
  1692. inc(l);
  1693. GetNextInstruction(hp1, hp1);
  1694. end;
  1695. { hp1 points to yyy: }
  1696. if assigned(hp1) and
  1697. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  1698. begin
  1699. condition:=inverse_cond(taicpu(p).condition);
  1700. GetNextInstruction(p,hp1);
  1701. hp3:=p;
  1702. p:=hp1;
  1703. repeat
  1704. taicpu(hp1).opcode:=A_CMOVcc;
  1705. taicpu(hp1).condition:=condition;
  1706. GetNextInstruction(hp1,hp1);
  1707. until not(assigned(hp1)) or
  1708. not(CanBeCMOV(hp1));
  1709. { hp2 is still at jmp yyy }
  1710. GetNextInstruction(hp2,hp1);
  1711. { hp2 is now at xxx: }
  1712. condition:=inverse_cond(condition);
  1713. GetNextInstruction(hp1,hp1);
  1714. { hp1 is now at <several movs 2> }
  1715. repeat
  1716. taicpu(hp1).opcode:=A_CMOVcc;
  1717. taicpu(hp1).condition:=condition;
  1718. GetNextInstruction(hp1,hp1);
  1719. until not(assigned(hp1)) or
  1720. not(CanBeCMOV(hp1));
  1721. {
  1722. asml.remove(hp1.next)
  1723. hp1.next.free;
  1724. asml.remove(hp1);
  1725. hp1.free;
  1726. }
  1727. { remove jCC }
  1728. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  1729. asml.remove(hp3);
  1730. hp3.free;
  1731. { remove jmp }
  1732. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1733. asml.remove(hp2);
  1734. hp2.free;
  1735. continue;
  1736. end;
  1737. end;
  1738. end;
  1739. end;
  1740. end;
  1741. {$endif USECMOV}
  1742. A_FSTP,A_FISTP:
  1743. if doFpuLoadStoreOpt(asmL,p) then
  1744. continue;
  1745. A_IMUL:
  1746. begin
  1747. if (taicpu(p).ops >= 2) and
  1748. ((taicpu(p).oper[0]^.typ = top_const) or
  1749. ((taicpu(p).oper[0]^.typ = top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full))) and
  1750. (taicpu(p).oper[1]^.typ = top_reg) and
  1751. ((taicpu(p).ops = 2) or
  1752. ((taicpu(p).oper[2]^.typ = top_reg) and
  1753. (taicpu(p).oper[2]^.reg = taicpu(p).oper[1]^.reg))) and
  1754. getLastInstruction(p,hp1) and
  1755. (hp1.typ = ait_instruction) and
  1756. (taicpu(hp1).opcode = A_MOV) and
  1757. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1758. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1759. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1760. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1761. begin
  1762. taicpu(p).ops := 3;
  1763. taicpu(p).loadreg(1,taicpu(hp1).oper[0]^.reg);
  1764. taicpu(p).loadreg(2,taicpu(hp1).oper[1]^.reg);
  1765. asml.remove(hp1);
  1766. hp1.free;
  1767. end;
  1768. end;
  1769. A_MOV:
  1770. begin
  1771. if (taicpu(p).oper[0]^.typ = top_reg) and
  1772. (taicpu(p).oper[1]^.typ = top_reg) and
  1773. GetNextInstruction(p, hp1) and
  1774. (hp1.typ = ait_Instruction) and
  1775. ((taicpu(hp1).opcode = A_MOV) or
  1776. (taicpu(hp1).opcode = A_MOVZX) or
  1777. (taicpu(hp1).opcode = A_MOVSX)) and
  1778. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1779. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1780. ((taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) or
  1781. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg)) and
  1782. (getsupreg(taicpu(hp1).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) then
  1783. {mov reg1, reg2
  1784. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1785. begin
  1786. if (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) then
  1787. taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[0]^.reg;
  1788. if (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) then
  1789. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
  1790. asml.remove(p);
  1791. p.free;
  1792. p := hp1;
  1793. continue;
  1794. end
  1795. else if (taicpu(p).oper[0]^.typ = top_ref) and
  1796. GetNextInstruction(p,hp1) and
  1797. (hp1.typ = ait_instruction) and
  1798. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  1799. GetNextInstruction(hp1,hp2) and
  1800. (hp2.typ = ait_instruction) and
  1801. (taicpu(hp2).opcode = A_MOV) and
  1802. (taicpu(hp2).oper[0]^.typ = top_reg) and
  1803. (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  1804. (taicpu(hp2).oper[1]^.typ = top_ref) then
  1805. begin
  1806. TmpUsedRegs := UsedRegs;
  1807. UpdateUsedRegs(TmpUsedRegs,tai(hp1.next));
  1808. if (RefsEqual(taicpu(hp2).oper[1]^.ref^, taicpu(p).oper[0]^.ref^) and
  1809. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,
  1810. hp2, TmpUsedRegs))) then
  1811. { change mov (ref), reg }
  1812. { add/sub/or/... reg2/$const, reg }
  1813. { mov reg, (ref) }
  1814. { # release reg }
  1815. { to add/sub/or/... reg2/$const, (ref) }
  1816. begin
  1817. case taicpu(hp1).opcode of
  1818. A_INC,A_DEC:
  1819. taicpu(hp1).LoadRef(0,taicpu(p).oper[0]^.ref^)
  1820. else
  1821. taicpu(hp1).LoadRef(1,taicpu(p).oper[0]^.ref^);
  1822. end;
  1823. asml.remove(p);
  1824. asml.remove(hp2);
  1825. p.free;
  1826. hp2.free;
  1827. p := hp1
  1828. end;
  1829. end
  1830. end;
  1831. end;
  1832. end;
  1833. end;
  1834. p := tai(p.next)
  1835. end;
  1836. end;
  1837. procedure PostPeepHoleOpts(asml: taasmoutput; BlockStart, BlockEnd: tai);
  1838. var
  1839. p,hp1,hp2: tai;
  1840. begin
  1841. p := BlockStart;
  1842. while (p <> BlockEnd) Do
  1843. begin
  1844. case p.Typ Of
  1845. Ait_Instruction:
  1846. begin
  1847. case taicpu(p).opcode Of
  1848. A_CALL:
  1849. if (AktOptProcessor < ClassPentium2) and
  1850. GetNextInstruction(p, hp1) and
  1851. (hp1.typ = ait_instruction) and
  1852. (taicpu(hp1).opcode = A_JMP) and
  1853. ((taicpu(hp1).oper[0]^.typ=top_ref) and (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full)) then
  1854. begin
  1855. hp2 := taicpu.Op_sym(A_PUSH,S_L,taicpu(hp1).oper[0]^.ref^.symbol);
  1856. InsertLLItem(asml, p.previous, p, hp2);
  1857. taicpu(p).opcode := A_JMP;
  1858. taicpu(p).is_jmp := true;
  1859. asml.remove(hp1);
  1860. hp1.free;
  1861. end;
  1862. A_CMP:
  1863. begin
  1864. if (taicpu(p).oper[0]^.typ = top_const) and
  1865. (taicpu(p).oper[0]^.val = 0) and
  1866. (taicpu(p).oper[1]^.typ = top_reg) then
  1867. {change "cmp $0, %reg" to "test %reg, %reg"}
  1868. begin
  1869. taicpu(p).opcode := A_TEST;
  1870. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  1871. continue;
  1872. end;
  1873. end;
  1874. (*
  1875. Optimization is not safe; xor clears the carry flag.
  1876. See test/tgadint64 in the test suite.
  1877. A_MOV:
  1878. if (taicpu(p).oper[0]^.typ = Top_Const) and
  1879. (taicpu(p).oper[0]^.val = 0) and
  1880. (taicpu(p).oper[1]^.typ = Top_Reg) then
  1881. { change "mov $0, %reg" into "xor %reg, %reg" }
  1882. begin
  1883. taicpu(p).opcode := A_XOR;
  1884. taicpu(p).LoadReg(0,taicpu(p).oper[1]^.reg);
  1885. end;
  1886. *)
  1887. A_MOVZX:
  1888. { if register vars are on, it's possible there is code like }
  1889. { "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx" }
  1890. { so we can't safely replace the movzx then with xor/mov, }
  1891. { since that would change the flags (JM) }
  1892. if not(cs_regvars in aktglobalswitches) then
  1893. begin
  1894. if (taicpu(p).oper[1]^.typ = top_reg) then
  1895. if (taicpu(p).oper[0]^.typ = top_reg)
  1896. then
  1897. case taicpu(p).opsize of
  1898. S_BL:
  1899. begin
  1900. if IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  1901. not(CS_LittleSize in aktglobalswitches) and
  1902. (aktoptprocessor = ClassPentium) then
  1903. {Change "movzbl %reg1, %reg2" to
  1904. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1905. PentiumMMX}
  1906. begin
  1907. hp1 := taicpu.op_reg_reg(A_XOR, S_L,
  1908. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  1909. InsertLLItem(asml,p.previous, p, hp1);
  1910. taicpu(p).opcode := A_MOV;
  1911. taicpu(p).changeopsize(S_B);
  1912. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  1913. end;
  1914. end;
  1915. end
  1916. else if (taicpu(p).oper[0]^.typ = top_ref) and
  1917. (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  1918. (taicpu(p).oper[0]^.ref^.index <> taicpu(p).oper[1]^.reg) and
  1919. not(CS_LittleSize in aktglobalswitches) and
  1920. IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  1921. (aktoptprocessor = ClassPentium) and
  1922. (taicpu(p).opsize = S_BL) then
  1923. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1924. Pentium and PentiumMMX}
  1925. begin
  1926. hp1 := taicpu.Op_reg_reg(A_XOR, S_L, taicpu(p).oper[1]^.reg,
  1927. taicpu(p).oper[1]^.reg);
  1928. taicpu(p).opcode := A_MOV;
  1929. taicpu(p).changeopsize(S_B);
  1930. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  1931. InsertLLItem(asml,p.previous, p, hp1);
  1932. end;
  1933. end;
  1934. A_TEST, A_OR:
  1935. {removes the line marked with (x) from the sequence
  1936. and/or/xor/add/sub/... $x, %y
  1937. test/or %y, %y (x)
  1938. j(n)z _Label
  1939. as the first instruction already adjusts the ZF}
  1940. begin
  1941. if OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  1942. if GetLastInstruction(p, hp1) and
  1943. (tai(hp1).typ = ait_instruction) then
  1944. case taicpu(hp1).opcode Of
  1945. A_ADD, A_SUB, A_OR, A_XOR, A_AND{, A_SHL, A_SHR}:
  1946. begin
  1947. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  1948. begin
  1949. hp1 := tai(p.next);
  1950. asml.remove(p);
  1951. p.free;
  1952. p := tai(hp1);
  1953. continue
  1954. end;
  1955. end;
  1956. A_DEC, A_INC, A_NEG:
  1957. begin
  1958. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^) then
  1959. begin
  1960. case taicpu(hp1).opcode Of
  1961. A_DEC, A_INC:
  1962. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1963. begin
  1964. case taicpu(hp1).opcode Of
  1965. A_DEC: taicpu(hp1).opcode := A_SUB;
  1966. A_INC: taicpu(hp1).opcode := A_ADD;
  1967. end;
  1968. taicpu(hp1).Loadoper(1,taicpu(hp1).oper[0]^);
  1969. taicpu(hp1).LoadConst(0,1);
  1970. taicpu(hp1).ops:=2;
  1971. end
  1972. end;
  1973. hp1 := tai(p.next);
  1974. asml.remove(p);
  1975. p.free;
  1976. p := tai(hp1);
  1977. continue
  1978. end;
  1979. end
  1980. end
  1981. end;
  1982. end;
  1983. end;
  1984. end;
  1985. p := tai(p.next)
  1986. end;
  1987. end;
  1988. end.