cpuinfo.pas 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144
  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv5te,
  31. cpu_armv5tej,
  32. cpu_armv6,
  33. cpu_armv6k,
  34. cpu_armv6t2,
  35. cpu_armv6z,
  36. cpu_armv7,
  37. cpu_armv7a,
  38. cpu_armv7r,
  39. cpu_armv7m,
  40. cpu_armv7em
  41. );
  42. Const
  43. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  44. cpu_thumb = [];
  45. cpu_thumb2 = [cpu_armv7m];
  46. Type
  47. tfputype =
  48. (fpu_none,
  49. fpu_soft,
  50. fpu_libgcc,
  51. fpu_fpa,
  52. fpu_fpa10,
  53. fpu_fpa11,
  54. fpu_vfpv2,
  55. fpu_vfpv3,
  56. fpu_vfpv3_d16
  57. );
  58. tcontrollertype =
  59. (ct_none,
  60. { Phillips }
  61. ct_lpc2114,
  62. ct_lpc2124,
  63. ct_lpc2194,
  64. ct_lpc1754,
  65. ct_lpc1756,
  66. ct_lpc1758,
  67. ct_lpc1764,
  68. ct_lpc1766,
  69. ct_lpc1768,
  70. { ATMEL }
  71. ct_at91sam7s256,
  72. ct_at91sam7se256,
  73. ct_at91sam7x256,
  74. ct_at91sam7xc256,
  75. { STMicroelectronics }
  76. ct_stm32f103rb,
  77. ct_stm32f103re,
  78. ct_stm32f103c4t,
  79. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  80. ct_lm3s1110,
  81. ct_lm3s1133,
  82. ct_lm3s1138,
  83. ct_lm3s1150,
  84. ct_lm3s1162,
  85. ct_lm3s1165,
  86. ct_lm3s1166,
  87. ct_lm3s2110,
  88. ct_lm3s2139,
  89. ct_lm3s6100,
  90. ct_lm3s6110,
  91. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  92. ct_lm3s1601,
  93. ct_lm3s1608,
  94. ct_lm3s1620,
  95. ct_lm3s1635,
  96. ct_lm3s1636,
  97. ct_lm3s1637,
  98. ct_lm3s1651,
  99. ct_lm3s2601,
  100. ct_lm3s2608,
  101. ct_lm3s2620,
  102. ct_lm3s2637,
  103. ct_lm3s2651,
  104. ct_lm3s6610,
  105. ct_lm3s6611,
  106. ct_lm3s6618,
  107. ct_lm3s6633,
  108. ct_lm3s6637,
  109. ct_lm3s8630,
  110. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  111. ct_lm3s1911,
  112. ct_lm3s1918,
  113. ct_lm3s1937,
  114. ct_lm3s1958,
  115. ct_lm3s1960,
  116. ct_lm3s1968,
  117. ct_lm3s1969,
  118. ct_lm3s2911,
  119. ct_lm3s2918,
  120. ct_lm3s2919,
  121. ct_lm3s2939,
  122. ct_lm3s2948,
  123. ct_lm3s2950,
  124. ct_lm3s2965,
  125. ct_lm3s6911,
  126. ct_lm3s6918,
  127. ct_lm3s6938,
  128. ct_lm3s6950,
  129. ct_lm3s6952,
  130. ct_lm3s6965,
  131. ct_lm3s8930,
  132. ct_lm3s8933,
  133. ct_lm3s8938,
  134. ct_lm3s8962,
  135. ct_lm3s8970,
  136. ct_lm3s8971,
  137. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  138. ct_lm3s5951,
  139. ct_lm3s5956,
  140. ct_lm3s1b21,
  141. ct_lm3s2b93,
  142. ct_lm3s5b91,
  143. ct_lm3s9b81,
  144. ct_lm3s9b90,
  145. ct_lm3s9b92,
  146. ct_lm3s9b95,
  147. ct_lm3s9b96,
  148. { SAMSUNG }
  149. ct_sc32442b,
  150. // generic Thumb2 target
  151. ct_thumb2bare
  152. );
  153. Const
  154. {# Size of native extended floating point type }
  155. extended_size = 12;
  156. {# Size of a multimedia register }
  157. mmreg_size = 16;
  158. { target cpu string (used by compiler options) }
  159. target_cpu_string = 'arm';
  160. { calling conventions supported by the code generator }
  161. supported_calling_conventions : tproccalloptions = [
  162. pocall_internproc,
  163. pocall_safecall,
  164. pocall_stdcall,
  165. { same as stdcall only different name mangling }
  166. pocall_cdecl,
  167. { same as stdcall only different name mangling }
  168. pocall_cppdecl,
  169. { same as stdcall but floating point numbers are handled like equal sized integers }
  170. pocall_softfloat,
  171. { same as stdcall (requires that all const records are passed by
  172. reference, but that's already done for stdcall) }
  173. pocall_mwpascal,
  174. { used for interrupt handling }
  175. pocall_interrupt
  176. ];
  177. cputypestr : array[tcputype] of string[8] = ('',
  178. 'ARMV3',
  179. 'ARMV4',
  180. 'ARMV4T',
  181. 'ARMV5',
  182. 'ARMV5T',
  183. 'ARMV5TE',
  184. 'ARMV5TEJ',
  185. 'ARMV6',
  186. 'ARMV6K',
  187. 'ARMV6T2',
  188. 'ARMV6Z',
  189. 'ARMV7',
  190. 'ARMV7A',
  191. 'ARMV7R',
  192. 'ARMV7M',
  193. 'ARMV7EM'
  194. );
  195. fputypestr : array[tfputype] of string[9] = ('',
  196. 'SOFT',
  197. 'LIBGCC',
  198. 'FPA',
  199. 'FPA10',
  200. 'FPA11',
  201. 'VFPV2',
  202. 'VFPV3',
  203. 'VFPV3_D16'
  204. );
  205. { We know that there are fields after sramsize
  206. but we don't care about this warning }
  207. {$WARN 3177 OFF}
  208. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  209. ((
  210. controllertypestr:'';
  211. controllerunitstr:'';
  212. interruptvectors:0;
  213. flashbase:0;
  214. flashsize:0;
  215. srambase:0;
  216. sramsize:0
  217. ),
  218. (
  219. controllertypestr:'LPC2114';
  220. controllerunitstr:'LPC21x4';
  221. interruptvectors:8;
  222. flashbase:$00000000;
  223. flashsize:$00040000;
  224. srambase:$40000000;
  225. sramsize:$00004000
  226. ),
  227. (
  228. controllertypestr:'LPC2124';
  229. controllerunitstr:'LPC21x4';
  230. interruptvectors:8;
  231. flashbase:$00000000;
  232. flashsize:$00040000;
  233. srambase:$40000000;
  234. sramsize:$00004000
  235. ),
  236. (
  237. controllertypestr:'LPC2194';
  238. controllerunitstr:'LPC21x4';
  239. interruptvectors:8;
  240. flashbase:$00000000;
  241. flashsize:$00040000;
  242. srambase:$40000000;
  243. sramsize:$00004000
  244. ),
  245. (
  246. controllertypestr:'LPC1754';
  247. controllerunitstr:'LPC1754';
  248. interruptvectors:12;
  249. flashbase:$00000000;
  250. flashsize:$00020000;
  251. srambase:$10000000;
  252. sramsize:$00004000
  253. ),
  254. (
  255. controllertypestr:'LPC1756';
  256. controllerunitstr:'LPC1756';
  257. interruptvectors:12;
  258. flashbase:$00000000;
  259. flashsize:$00040000;
  260. srambase:$10000000;
  261. sramsize:$00004000
  262. ),
  263. (
  264. controllertypestr:'LPC1758';
  265. controllerunitstr:'LPC1758';
  266. interruptvectors:12;
  267. flashbase:$00000000;
  268. flashsize:$00080000;
  269. srambase:$10000000;
  270. sramsize:$00008000
  271. ),
  272. (
  273. controllertypestr:'LPC1764';
  274. controllerunitstr:'LPC1764';
  275. interruptvectors:12;
  276. flashbase:$00000000;
  277. flashsize:$00020000;
  278. srambase:$10000000;
  279. sramsize:$00004000
  280. ),
  281. (
  282. controllertypestr:'LPC1766';
  283. controllerunitstr:'LPC1766';
  284. interruptvectors:12;
  285. flashbase:$00000000;
  286. flashsize:$00040000;
  287. srambase:$10000000;
  288. sramsize:$00008000
  289. ),
  290. (
  291. controllertypestr:'LPC1768';
  292. controllerunitstr:'LPC1768';
  293. interruptvectors:12;
  294. flashbase:$00000000;
  295. flashsize:$00080000;
  296. srambase:$10000000;
  297. sramsize:$00008000
  298. ),
  299. (
  300. controllertypestr:'AT91SAM7S256';
  301. controllerunitstr:'AT91SAM7x256';
  302. interruptvectors:8;
  303. flashbase:$00000000;
  304. flashsize:$00040000;
  305. srambase:$00200000;
  306. sramsize:$00010000
  307. ),
  308. (
  309. controllertypestr:'AT91SAM7SE256';
  310. controllerunitstr:'AT91SAM7x256';
  311. interruptvectors:8;
  312. flashbase:$00000000;
  313. flashsize:$00040000;
  314. srambase:$00200000;
  315. sramsize:$00010000
  316. ),
  317. (
  318. controllertypestr:'AT91SAM7X256';
  319. controllerunitstr:'AT91SAM7x256';
  320. interruptvectors:8;
  321. flashbase:$00000000;
  322. flashsize:$00040000;
  323. srambase:$00200000;
  324. sramsize:$00010000
  325. ),
  326. (
  327. controllertypestr:'AT91SAM7XC256';
  328. controllerunitstr:'AT91SAM7x256';
  329. interruptvectors:8;
  330. flashbase:$00000000;
  331. flashsize:$00040000;
  332. srambase:$00200000;
  333. sramsize:$00010000
  334. ),
  335. // ct_stm32f103rb,
  336. (
  337. controllertypestr:'STM32F103RB';
  338. controllerunitstr:'STM32F103';
  339. interruptvectors:12;
  340. flashbase:$08000000;
  341. flashsize:$00020000;
  342. srambase:$20000000;
  343. sramsize:$00005000
  344. ),
  345. // ct_stm32f103re,
  346. (
  347. controllertypestr:'STM32F103RE';
  348. controllerunitstr:'STM32F103';
  349. interruptvectors:12;
  350. flashbase:$08000000;
  351. flashsize:$00080000;
  352. srambase:$20000000;
  353. sramsize:$00010000
  354. ),
  355. // ct_stm32f103re,
  356. (
  357. controllertypestr:'STM32F103C4T';
  358. controllerunitstr:'STM32F103';
  359. interruptvectors:12;
  360. flashbase:$08000000;
  361. flashsize:$00004000;
  362. srambase:$20000000;
  363. sramsize:$00001800
  364. ),
  365. { TI - 64 K Flash, 16 K SRAM Devices }
  366. // ct_lm3s1110,
  367. (
  368. controllertypestr:'LM3S1110';
  369. controllerunitstr:'LM3FURY';
  370. interruptvectors:72;
  371. flashbase:$00000000;
  372. flashsize:$00010000;
  373. srambase:$20000000;
  374. sramsize:$00004000
  375. ),
  376. // ct_lm3s1133,
  377. (
  378. controllertypestr:'LM3S1133';
  379. controllerunitstr:'LM3FURY';
  380. interruptvectors:72;
  381. flashbase:$00000000;
  382. flashsize:$00010000;
  383. srambase:$20000000;
  384. sramsize:$00004000
  385. ),
  386. // ct_lm3s1138,
  387. (
  388. controllertypestr:'LM3S1138';
  389. controllerunitstr:'LM3FURY';
  390. interruptvectors:72;
  391. flashbase:$00000000;
  392. flashsize:$00010000;
  393. srambase:$20000000;
  394. sramsize:$00004000
  395. ),
  396. // ct_lm3s1150,
  397. (
  398. controllertypestr:'LM3S1150';
  399. controllerunitstr:'LM3FURY';
  400. interruptvectors:72;
  401. flashbase:$00000000;
  402. flashsize:$00010000;
  403. srambase:$20000000;
  404. sramsize:$00004000
  405. ),
  406. // ct_lm3s1162,
  407. (
  408. controllertypestr:'LM3S1162';
  409. controllerunitstr:'LM3FURY';
  410. interruptvectors:72;
  411. flashbase:$00000000;
  412. flashsize:$00010000;
  413. srambase:$20000000;
  414. sramsize:$00004000
  415. ),
  416. // ct_lm3s1165,
  417. (
  418. controllertypestr:'LM3S1165';
  419. controllerunitstr:'LM3FURY';
  420. interruptvectors:72;
  421. flashbase:$00000000;
  422. flashsize:$00010000;
  423. srambase:$20000000;
  424. sramsize:$00004000
  425. ),
  426. // ct_lm3s1166,
  427. (
  428. controllertypestr:'LM3S1166';
  429. controllerunitstr:'LM3FURY';
  430. interruptvectors:72;
  431. flashbase:$00000000;
  432. flashsize:$00010000;
  433. srambase:$20000000;
  434. sramsize:$00004000
  435. ),
  436. // ct_lm3s2110,
  437. (
  438. controllertypestr:'LM3S2110';
  439. controllerunitstr:'LM3FURY';
  440. interruptvectors:72;
  441. flashbase:$00000000;
  442. flashsize:$00010000;
  443. srambase:$20000000;
  444. sramsize:$00004000
  445. ),
  446. // ct_lm3s2139,
  447. (
  448. controllertypestr:'LM3S2139';
  449. controllerunitstr:'LM3FURY';
  450. interruptvectors:72;
  451. flashbase:$00000000;
  452. flashsize:$00010000;
  453. srambase:$20000000;
  454. sramsize:$00004000
  455. ),
  456. // ct_lm3s6100,
  457. (
  458. controllertypestr:'LM3S6100';
  459. controllerunitstr:'LM3FURY';
  460. interruptvectors:72;
  461. flashbase:$00000000;
  462. flashsize:$00010000;
  463. srambase:$20000000;
  464. sramsize:$00004000
  465. ),
  466. // ct_lm3s6110,
  467. (
  468. controllertypestr:'LM3S6110';
  469. controllerunitstr:'LM3FURY';
  470. interruptvectors:72;
  471. flashbase:$00000000;
  472. flashsize:$00010000;
  473. srambase:$20000000;
  474. sramsize:$00004000
  475. ),
  476. { TI - 128K Flash, 32K SRAM devices }
  477. // ct_lm3s1601,
  478. (
  479. controllertypestr:'LM3S1601';
  480. controllerunitstr:'LM3FURY';
  481. interruptvectors:72;
  482. flashbase:$00000000;
  483. flashsize:$00020000;
  484. srambase:$20000000;
  485. sramsize:$00008000
  486. ),
  487. // ct_lm3s1608,
  488. (
  489. controllertypestr:'LM3S1608';
  490. controllerunitstr:'LM3FURY';
  491. interruptvectors:72;
  492. flashbase:$00000000;
  493. flashsize:$00020000;
  494. srambase:$20000000;
  495. sramsize:$00008000
  496. ),
  497. // ct_lm3s1620,
  498. (
  499. controllertypestr:'LM3S1620';
  500. controllerunitstr:'LM3FURY';
  501. interruptvectors:72;
  502. flashbase:$00000000;
  503. flashsize:$00020000;
  504. srambase:$20000000;
  505. sramsize:$00008000
  506. ),
  507. // ct_lm3s1635,
  508. (
  509. controllertypestr:'LM3S1635';
  510. controllerunitstr:'LM3FURY';
  511. interruptvectors:72;
  512. flashbase:$00000000;
  513. flashsize:$00020000;
  514. srambase:$20000000;
  515. sramsize:$00008000
  516. ),
  517. // ct_lm3s1636,
  518. (
  519. controllertypestr:'LM3S1636';
  520. controllerunitstr:'LM3FURY';
  521. interruptvectors:72;
  522. flashbase:$00000000;
  523. flashsize:$00020000;
  524. srambase:$20000000;
  525. sramsize:$00008000
  526. ),
  527. // ct_lm3s1637,
  528. (
  529. controllertypestr:'LM3S1637';
  530. controllerunitstr:'LM3FURY';
  531. interruptvectors:72;
  532. flashbase:$00000000;
  533. flashsize:$00020000;
  534. srambase:$20000000;
  535. sramsize:$00008000
  536. ),
  537. // ct_lm3s1651,
  538. (
  539. controllertypestr:'LM3S1651';
  540. controllerunitstr:'LM3FURY';
  541. interruptvectors:72;
  542. flashbase:$00000000;
  543. flashsize:$00020000;
  544. srambase:$20000000;
  545. sramsize:$00008000
  546. ),
  547. // ct_lm3s2601,
  548. (
  549. controllertypestr:'LM3S2601';
  550. controllerunitstr:'LM3FURY';
  551. interruptvectors:72;
  552. flashbase:$00000000;
  553. flashsize:$00020000;
  554. srambase:$20000000;
  555. sramsize:$00008000
  556. ),
  557. // ct_lm3s2608,
  558. (
  559. controllertypestr:'LM3S2608';
  560. controllerunitstr:'LM3FURY';
  561. interruptvectors:72;
  562. flashbase:$00000000;
  563. flashsize:$00020000;
  564. srambase:$20000000;
  565. sramsize:$00008000
  566. ),
  567. // ct_lm3s2620,
  568. (
  569. controllertypestr:'LM3S2620';
  570. controllerunitstr:'LM3FURY';
  571. interruptvectors:72;
  572. flashbase:$00000000;
  573. flashsize:$00020000;
  574. srambase:$20000000;
  575. sramsize:$00008000
  576. ),
  577. // ct_lm3s2637,
  578. (
  579. controllertypestr:'LM3S2637';
  580. controllerunitstr:'LM3FURY';
  581. interruptvectors:72;
  582. flashbase:$00000000;
  583. flashsize:$00020000;
  584. srambase:$20000000;
  585. sramsize:$00008000
  586. ),
  587. // ct_lm3s2651,
  588. (
  589. controllertypestr:'LM3S2651';
  590. controllerunitstr:'LM3FURY';
  591. interruptvectors:72;
  592. flashbase:$00000000;
  593. flashsize:$00020000;
  594. srambase:$20000000;
  595. sramsize:$00008000
  596. ),
  597. // ct_lm3s6610,
  598. (
  599. controllertypestr:'LM3S6610';
  600. controllerunitstr:'LM3FURY';
  601. interruptvectors:72;
  602. flashbase:$00000000;
  603. flashsize:$00020000;
  604. srambase:$20000000;
  605. sramsize:$00008000
  606. ),
  607. // ct_lm3s6611,
  608. (
  609. controllertypestr:'LM3S6611';
  610. controllerunitstr:'LM3FURY';
  611. interruptvectors:72;
  612. flashbase:$00000000;
  613. flashsize:$00020000;
  614. srambase:$20000000;
  615. sramsize:$00008000
  616. ),
  617. // ct_lm3s6618,
  618. (
  619. controllertypestr:'LM3S6618';
  620. controllerunitstr:'LM3FURY';
  621. interruptvectors:72;
  622. flashbase:$00000000;
  623. flashsize:$00020000;
  624. srambase:$20000000;
  625. sramsize:$00008000
  626. ),
  627. // ct_lm3s6633,
  628. (
  629. controllertypestr:'LM3S6633';
  630. controllerunitstr:'LM3FURY';
  631. interruptvectors:72;
  632. flashbase:$00000000;
  633. flashsize:$00020000;
  634. srambase:$20000000;
  635. sramsize:$00008000
  636. ),
  637. // ct_lm3s6637,
  638. (
  639. controllertypestr:'LM3S6637';
  640. controllerunitstr:'LM3FURY';
  641. interruptvectors:72;
  642. flashbase:$00000000;
  643. flashsize:$00020000;
  644. srambase:$20000000;
  645. sramsize:$00008000
  646. ),
  647. // ct_lm3s8630,
  648. (
  649. controllertypestr:'LM3S8630';
  650. controllerunitstr:'LM3FURY';
  651. interruptvectors:72;
  652. flashbase:$00000000;
  653. flashsize:$00020000;
  654. srambase:$20000000;
  655. sramsize:$00008000
  656. ),
  657. { TI - 256K Flash, 64K SRAM devices }
  658. // ct_lm3s1911,
  659. (
  660. controllertypestr:'LM3S1911';
  661. controllerunitstr:'LM3FURY';
  662. interruptvectors:72;
  663. flashbase:$00000000;
  664. flashsize:$00040000;
  665. srambase:$20000000;
  666. sramsize:$00010000
  667. ),
  668. // ct_lm3s1918,
  669. (
  670. controllertypestr:'LM3S1918';
  671. controllerunitstr:'LM3FURY';
  672. interruptvectors:72;
  673. flashbase:$00000000;
  674. flashsize:$00040000;
  675. srambase:$20000000;
  676. sramsize:$00010000
  677. ),
  678. // ct_lm3s1937,
  679. (
  680. controllertypestr:'LM3S1937';
  681. controllerunitstr:'LM3FURY';
  682. interruptvectors:72;
  683. flashbase:$00000000;
  684. flashsize:$00040000;
  685. srambase:$20000000;
  686. sramsize:$00010000
  687. ),
  688. // ct_lm3s1958,
  689. (
  690. controllertypestr:'LM3S1958';
  691. controllerunitstr:'LM3FURY';
  692. interruptvectors:72;
  693. flashbase:$00000000;
  694. flashsize:$00040000;
  695. srambase:$20000000;
  696. sramsize:$00010000
  697. ),
  698. // ct_lm3s1960,
  699. (
  700. controllertypestr:'LM3S1960';
  701. controllerunitstr:'LM3FURY';
  702. interruptvectors:72;
  703. flashbase:$00000000;
  704. flashsize:$00040000;
  705. srambase:$20000000;
  706. sramsize:$00010000
  707. ),
  708. // ct_lm3s1968,
  709. (
  710. controllertypestr:'LM3S1968';
  711. controllerunitstr:'LM3FURY';
  712. interruptvectors:72;
  713. flashbase:$00000000;
  714. flashsize:$00040000;
  715. srambase:$20000000;
  716. sramsize:$00010000
  717. ),
  718. // ct_lm3s1969,
  719. (
  720. controllertypestr:'LM3S1969';
  721. controllerunitstr:'LM3FURY';
  722. interruptvectors:72;
  723. flashbase:$00000000;
  724. flashsize:$00040000;
  725. srambase:$20000000;
  726. sramsize:$00010000
  727. ),
  728. // ct_lm3s2911,
  729. (
  730. controllertypestr:'LM3S2911';
  731. controllerunitstr:'LM3FURY';
  732. interruptvectors:72;
  733. flashbase:$00000000;
  734. flashsize:$00040000;
  735. srambase:$20000000;
  736. sramsize:$00010000
  737. ),
  738. // ct_lm3s2918,
  739. (
  740. controllertypestr:'LM3S2918';
  741. controllerunitstr:'LM3FURY';
  742. interruptvectors:72;
  743. flashbase:$00000000;
  744. flashsize:$00040000;
  745. srambase:$20000000;
  746. sramsize:$00010000
  747. ),
  748. // ct_lm3s2919,
  749. (
  750. controllertypestr:'LM3S2919';
  751. controllerunitstr:'LM3FURY';
  752. interruptvectors:72;
  753. flashbase:$00000000;
  754. flashsize:$00040000;
  755. srambase:$20000000;
  756. sramsize:$00010000
  757. ),
  758. // ct_lm3s2939,
  759. (
  760. controllertypestr:'LM3S2939';
  761. controllerunitstr:'LM3FURY';
  762. interruptvectors:72;
  763. flashbase:$00000000;
  764. flashsize:$00040000;
  765. srambase:$20000000;
  766. sramsize:$00010000
  767. ),
  768. // ct_lm3s2948,
  769. (
  770. controllertypestr:'LM3S2948';
  771. controllerunitstr:'LM3FURY';
  772. interruptvectors:72;
  773. flashbase:$00000000;
  774. flashsize:$00040000;
  775. srambase:$20000000;
  776. sramsize:$00010000
  777. ),
  778. // ct_lm3s2950,
  779. (
  780. controllertypestr:'LM3S2950';
  781. controllerunitstr:'LM3FURY';
  782. interruptvectors:72;
  783. flashbase:$00000000;
  784. flashsize:$00040000;
  785. srambase:$20000000;
  786. sramsize:$00010000
  787. ),
  788. // ct_lm3s2965,
  789. (
  790. controllertypestr:'LM3S2965';
  791. controllerunitstr:'LM3FURY';
  792. interruptvectors:72;
  793. flashbase:$00000000;
  794. flashsize:$00040000;
  795. srambase:$20000000;
  796. sramsize:$00010000
  797. ),
  798. // ct_lm3s6911,
  799. (
  800. controllertypestr:'LM3S6911';
  801. controllerunitstr:'LM3FURY';
  802. interruptvectors:72;
  803. flashbase:$00000000;
  804. flashsize:$00040000;
  805. srambase:$20000000;
  806. sramsize:$00010000
  807. ),
  808. // ct_lm3s6918,
  809. (
  810. controllertypestr:'LM3S6918';
  811. controllerunitstr:'LM3FURY';
  812. interruptvectors:72;
  813. flashbase:$00000000;
  814. flashsize:$00040000;
  815. srambase:$20000000;
  816. sramsize:$00010000
  817. ),
  818. // ct_lm3s6938,
  819. (
  820. controllertypestr:'LM3S6938';
  821. controllerunitstr:'LM3FURY';
  822. interruptvectors:72;
  823. flashbase:$00000000;
  824. flashsize:$00040000;
  825. srambase:$20000000;
  826. sramsize:$00010000
  827. ),
  828. // ct_lm3s6950,
  829. (
  830. controllertypestr:'LM3S6950';
  831. controllerunitstr:'LM3FURY';
  832. interruptvectors:72;
  833. flashbase:$00000000;
  834. flashsize:$00040000;
  835. srambase:$20000000;
  836. sramsize:$00010000
  837. ),
  838. // ct_lm3s6952,
  839. (
  840. controllertypestr:'LM3S6952';
  841. controllerunitstr:'LM3FURY';
  842. interruptvectors:72;
  843. flashbase:$00000000;
  844. flashsize:$00040000;
  845. srambase:$20000000;
  846. sramsize:$00010000
  847. ),
  848. // ct_lm3s6965,
  849. (
  850. controllertypestr:'LM3S6965';
  851. controllerunitstr:'LM3FURY';
  852. interruptvectors:72;
  853. flashbase:$00000000;
  854. flashsize:$00040000;
  855. srambase:$20000000;
  856. sramsize:$00010000
  857. ),
  858. // ct_lm3s8930,
  859. (
  860. controllertypestr:'LM3S8930';
  861. controllerunitstr:'LM3FURY';
  862. interruptvectors:72;
  863. flashbase:$00000000;
  864. flashsize:$00040000;
  865. srambase:$20000000;
  866. sramsize:$00010000
  867. ),
  868. // ct_lm3s8933,
  869. (
  870. controllertypestr:'LM3S8933';
  871. controllerunitstr:'LM3FURY';
  872. interruptvectors:72;
  873. flashbase:$00000000;
  874. flashsize:$00040000;
  875. srambase:$20000000;
  876. sramsize:$00010000
  877. ),
  878. // ct_lm3s8938,
  879. (
  880. controllertypestr:'LM3S8938';
  881. controllerunitstr:'LM3FURY';
  882. interruptvectors:72;
  883. flashbase:$00000000;
  884. flashsize:$00040000;
  885. srambase:$20000000;
  886. sramsize:$00010000
  887. ),
  888. // ct_lm3s8962,
  889. (
  890. controllertypestr:'LM3S8962';
  891. controllerunitstr:'LM3FURY';
  892. interruptvectors:72;
  893. flashbase:$00000000;
  894. flashsize:$00040000;
  895. srambase:$20000000;
  896. sramsize:$00010000
  897. ),
  898. // ct_lm3s8970,
  899. (
  900. controllertypestr:'LM3S8970';
  901. controllerunitstr:'LM3FURY';
  902. interruptvectors:72;
  903. flashbase:$00000000;
  904. flashsize:$00040000;
  905. srambase:$20000000;
  906. sramsize:$00010000
  907. ),
  908. // ct_lm3s8971,
  909. (
  910. controllertypestr:'LM3S8971';
  911. controllerunitstr:'LM3FURY';
  912. interruptvectors:72;
  913. flashbase:$00000000;
  914. flashsize:$00040000;
  915. srambase:$20000000;
  916. sramsize:$00010000
  917. ),
  918. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  919. // ct_lm3s5951,
  920. (
  921. controllertypestr:'LM3S5951';
  922. controllerunitstr:'LM3TEMPEST';
  923. interruptvectors:72;
  924. flashbase:$00000000;
  925. flashsize:$00040000;
  926. srambase:$20000000;
  927. sramsize:$00010000
  928. ),
  929. // ct_lm3s5956,
  930. (
  931. controllertypestr:'LM3S5956';
  932. controllerunitstr:'LM3TEMPEST';
  933. interruptvectors:72;
  934. flashbase:$00000000;
  935. flashsize:$00040000;
  936. srambase:$20000000;
  937. sramsize:$00010000
  938. ),
  939. // ct_lm3s1b21,
  940. (
  941. controllertypestr:'LM3S1B21';
  942. controllerunitstr:'LM3TEMPEST';
  943. interruptvectors:72;
  944. flashbase:$00000000;
  945. flashsize:$00040000;
  946. srambase:$20000000;
  947. sramsize:$00010000
  948. ),
  949. // ct_lm3s2b93,
  950. (
  951. controllertypestr:'LM3S2B93';
  952. controllerunitstr:'LM3TEMPEST';
  953. interruptvectors:72;
  954. flashbase:$00000000;
  955. flashsize:$00040000;
  956. srambase:$20000000;
  957. sramsize:$00010000
  958. ),
  959. // ct_lm3s5b91,
  960. (
  961. controllertypestr:'LM3S5B91';
  962. controllerunitstr:'LM3TEMPEST';
  963. interruptvectors:72;
  964. flashbase:$00000000;
  965. flashsize:$00040000;
  966. srambase:$20000000;
  967. sramsize:$00010000
  968. ),
  969. // ct_lm3s9b81,
  970. (
  971. controllertypestr:'LM3S9B81';
  972. controllerunitstr:'LM3TEMPEST';
  973. interruptvectors:72;
  974. flashbase:$00000000;
  975. flashsize:$00040000;
  976. srambase:$20000000;
  977. sramsize:$00010000
  978. ),
  979. // ct_lm3s9b90,
  980. (
  981. controllertypestr:'LM3S9B90';
  982. controllerunitstr:'LM3TEMPEST';
  983. interruptvectors:72;
  984. flashbase:$00000000;
  985. flashsize:$00040000;
  986. srambase:$20000000;
  987. sramsize:$00010000
  988. ),
  989. // ct_lm3s9b92,
  990. (
  991. controllertypestr:'LM3S9B92';
  992. controllerunitstr:'LM3TEMPEST';
  993. interruptvectors:72;
  994. flashbase:$00000000;
  995. flashsize:$00040000;
  996. srambase:$20000000;
  997. sramsize:$00010000
  998. ),
  999. // ct_lm3s9b95,
  1000. (
  1001. controllertypestr:'LM3S9B95';
  1002. controllerunitstr:'LM3TEMPEST';
  1003. interruptvectors:72;
  1004. flashbase:$00000000;
  1005. flashsize:$00040000;
  1006. srambase:$20000000;
  1007. sramsize:$00010000
  1008. ),
  1009. // ct_lm3s9b96,
  1010. (
  1011. controllertypestr:'LM3S9B96';
  1012. controllerunitstr:'LM3TEMPEST';
  1013. interruptvectors:72;
  1014. flashbase:$00000000;
  1015. flashsize:$00040000;
  1016. srambase:$20000000;
  1017. sramsize:$00010000
  1018. ),
  1019. //ct_SC32442b,
  1020. (
  1021. controllertypestr:'SC32442B';
  1022. controllerunitstr:'sc32442b';
  1023. interruptvectors:7;
  1024. flashbase:$00000000;
  1025. flashsize:$00000000;
  1026. srambase:$00000000;
  1027. sramsize:$08000000
  1028. ),
  1029. // bare bones Thumb2
  1030. (
  1031. controllertypestr:'THUMB2_BARE';
  1032. controllerunitstr:'THUMB2_BARE';
  1033. interruptvectors:128;
  1034. flashbase:$00000000;
  1035. flashsize:$00100000;
  1036. srambase:$20000000;
  1037. sramsize:$00100000
  1038. )
  1039. );
  1040. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16];
  1041. { Supported optimizations, only used for information }
  1042. supported_optimizerswitches = genericlevel1optimizerswitches+
  1043. genericlevel2optimizerswitches+
  1044. genericlevel3optimizerswitches-
  1045. { no need to write info about those }
  1046. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  1047. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  1048. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  1049. level1optimizerswitches = genericlevel1optimizerswitches;
  1050. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  1051. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  1052. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [cs_opt_scheduler{,cs_opt_loopunroll}];
  1053. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  1054. type
  1055. tcpuflags =
  1056. (CPUARM_HAS_BX, { CPU supports the BX instruction }
  1057. CPUARM_HAS_BLX, { CPU supports the BLX instruction }
  1058. CPUARM_HAS_CLZ, { CPU supports the CLZ instruction }
  1059. CPUARM_HAS_EDSP, { CPU supports the PLD,STRD,LDRD,MCRR and MRRC instructions }
  1060. CPUARM_HAS_REV, { CPU supports the REV instruction }
  1061. CPUARM_HAS_LDREX,
  1062. CPUARM_HAS_IDIV
  1063. );
  1064. const
  1065. cpu_capabilities : array[tcputype] of set of tcpuflags =
  1066. ( { cpu_none } [],
  1067. { cpu_armv3 } [],
  1068. { cpu_armv4 } [],
  1069. { cpu_armv4t } [CPUARM_HAS_BX],
  1070. { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ],
  1071. { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ],
  1072. { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1073. { cpu_armv5tej } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1074. { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1075. { cpu_armv6k } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1076. { cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1077. { cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1078. { the identifier armv7 is should not be used, it is considered being equal to armv7a }
  1079. { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1080. { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1081. { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1082. { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
  1083. { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
  1084. );
  1085. Implementation
  1086. end.