aoptcpu.pas 20 KB

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  1. {
  2. Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
  3. Development Team
  4. This unit implements the ARM optimizer object
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. Interface
  21. uses cpubase, aasmtai, aopt, aoptcpub;
  22. Type
  23. TCpuAsmOptimizer = class(TAsmOptimizer)
  24. { uses the same constructor as TAopObj }
  25. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  26. procedure PeepHoleOptPass2;override;
  27. End;
  28. TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
  29. { uses the same constructor as TAopObj }
  30. procedure PeepHoleOptPass2;override;
  31. End;
  32. Implementation
  33. uses
  34. verbose,
  35. cgutils,
  36. aasmbase,aasmcpu;
  37. function CanBeCond(p : tai) : boolean;
  38. begin
  39. result:=
  40. (p.typ=ait_instruction) and
  41. (taicpu(p).condition=C_None) and
  42. ((taicpu(p).opcode<>A_BLX) or
  43. (taicpu(p).oper[0]^.typ=top_reg));
  44. end;
  45. function RefsEqual(const r1, r2: treference): boolean;
  46. begin
  47. refsequal :=
  48. (r1.offset = r2.offset) and
  49. (r1.base = r2.base) and
  50. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  51. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  52. (r1.relsymbol = r2.relsymbol) and
  53. (r1.signindex = r2.signindex) and
  54. (r1.shiftimm = r2.shiftimm) and
  55. (r1.addressmode = r2.addressmode) and
  56. (r1.shiftmode = r2.shiftmode);
  57. end;
  58. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  59. var
  60. next1: tai;
  61. hp1,hp2: tai;
  62. begin
  63. result := false;
  64. case p.typ of
  65. ait_instruction:
  66. begin
  67. (* optimization proved not to be safe, see tw4768.pp
  68. {
  69. change
  70. <op> reg,x,y
  71. cmp reg,#0
  72. into
  73. <op>s reg,x,y
  74. }
  75. { this optimization can applied only to the currently enabled operations because
  76. the other operations do not update all flags and FPC does not track flag usage }
  77. if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
  78. (taicpu(p).oper[0]^.typ = top_reg) and
  79. (taicpu(p).oppostfix = PF_None) and
  80. (taicpu(p).condition = C_None) and
  81. GetNextInstruction(p, hp1) and
  82. (tai(hp1).typ = ait_instruction) and
  83. (taicpu(hp1).opcode = A_CMP) and
  84. (taicpu(hp1).oppostfix = PF_None) and
  85. (taicpu(hp1).condition = C_None) and
  86. (taicpu(hp1).oper[0]^.typ = top_reg) and
  87. (taicpu(hp1).oper[1]^.typ = top_const) and
  88. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  89. (taicpu(hp1).oper[1]^.val = 0) { and
  90. GetNextInstruction(hp1, hp2) and
  91. (tai(hp2).typ = ait_instruction) and
  92. // be careful here, following instructions could use other flags
  93. // however after a jump fpc never depends on the value of flags
  94. (taicpu(hp2).opcode = A_B) and
  95. (taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL])} then
  96. begin
  97. taicpu(p).oppostfix:=PF_S;
  98. asml.remove(hp1);
  99. hp1.free;
  100. end
  101. else
  102. *)
  103. case taicpu(p).opcode of
  104. A_STR:
  105. begin
  106. { change
  107. str reg1,ref
  108. ldr reg2,ref
  109. into
  110. str reg1,ref
  111. mov reg2,reg1
  112. }
  113. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  114. GetNextInstruction(p,hp1) and
  115. (hp1.typ = ait_instruction) and
  116. (taicpu(hp1).opcode = A_LDR) and
  117. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  118. ((taicpu(p).condition = taicpu(hp1).condition) or
  119. (taicpu(p).condition = C_None)) and
  120. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  121. begin
  122. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  123. begin
  124. asml.remove(hp1);
  125. hp1.free;
  126. end
  127. else
  128. begin
  129. taicpu(hp1).opcode:=A_MOV;
  130. taicpu(hp1).oppostfix:=PF_None;
  131. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  132. end;
  133. result := true;
  134. end;
  135. end;
  136. A_LDR:
  137. begin
  138. { change
  139. ldr reg1,ref
  140. ldr reg2,ref
  141. into
  142. ldr reg1,ref
  143. mov reg2,reg1
  144. }
  145. if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
  146. GetNextInstruction(p,hp1) and
  147. (hp1.typ = ait_instruction) and
  148. (taicpu(hp1).opcode = A_LDR) and
  149. RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
  150. ((taicpu(p).condition = taicpu(hp1).condition) or
  151. (taicpu(p).condition = C_None)) and
  152. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
  153. (taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
  154. (taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
  155. begin
  156. if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
  157. begin
  158. asml.remove(hp1);
  159. hp1.free;
  160. end
  161. else
  162. begin
  163. taicpu(hp1).opcode:=A_MOV;
  164. taicpu(hp1).oppostfix:=PF_None;
  165. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  166. end;
  167. result := true;
  168. end;
  169. end;
  170. A_MOV:
  171. begin
  172. { fold
  173. mov reg1,reg0, shift imm1
  174. mov reg1,reg1, shift imm2
  175. to
  176. mov reg1,reg0, shift imm1+imm2
  177. }
  178. if (taicpu(p).ops=3) and
  179. (taicpu(p).oper[0]^.typ = top_reg) and
  180. (taicpu(p).oper[2]^.typ = top_shifterop) and
  181. (taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
  182. getnextinstruction(p,next1) and
  183. (next1.typ = ait_instruction) and
  184. (taicpu(next1).opcode = A_MOV) and
  185. (taicpu(p).condition=taicpu(next1).condition) and
  186. (taicpu(next1).ops=3) and
  187. (taicpu(next1).oper[0]^.typ = top_reg) and
  188. (taicpu(p).oper[0]^.reg=taicpu(next1).oper[0]^.reg) and
  189. (taicpu(next1).oper[1]^.typ = top_reg) and
  190. (taicpu(p).oper[0]^.reg=taicpu(next1).oper[1]^.reg) and
  191. (taicpu(next1).oper[2]^.typ = top_shifterop) and
  192. (taicpu(next1).oper[2]^.shifterop^.rs = NR_NO) and
  193. (taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(next1).oper[2]^.shifterop^.shiftmode) then
  194. begin
  195. inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(next1).oper[2]^.shifterop^.shiftimm);
  196. { avoid overflows }
  197. if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
  198. case taicpu(p).oper[2]^.shifterop^.shiftmode of
  199. SM_ROR:
  200. taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
  201. SM_ASR:
  202. taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
  203. SM_LSR,
  204. SM_LSL:
  205. begin
  206. hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
  207. InsertLLItem(p.previous, p.next, hp1);
  208. p.free;
  209. p:=hp1;
  210. end;
  211. else
  212. internalerror(2008072803);
  213. end;
  214. asml.remove(next1);
  215. next1.free;
  216. result := true;
  217. end;
  218. end;
  219. A_AND:
  220. begin
  221. {
  222. change
  223. and reg2,reg1,const1
  224. and reg2,reg2,const2
  225. to
  226. and reg2,reg1,(const1 and const2)
  227. }
  228. if (taicpu(p).oper[0]^.typ = top_reg) and
  229. (taicpu(p).oper[1]^.typ = top_reg) and
  230. (taicpu(p).oper[2]^.typ = top_const) and
  231. GetNextInstruction(p, hp1) and
  232. (tai(hp1).typ = ait_instruction) and
  233. (taicpu(hp1).opcode = A_AND) and
  234. (taicpu(p).condition=taicpu(hp1).condition) and
  235. (taicpu(p).oppostfix=PF_None) and
  236. (taicpu(hp1).oper[0]^.typ = top_reg) and
  237. (taicpu(hp1).oper[1]^.typ = top_reg) and
  238. (taicpu(hp1).oper[2]^.typ = top_const) and
  239. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  240. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
  241. begin
  242. taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
  243. taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
  244. asml.remove(hp1);
  245. hp1.free;
  246. end;
  247. end;
  248. end;
  249. end;
  250. end;
  251. end;
  252. { instructions modifying the CPSR can be only the last instruction }
  253. function MustBeLast(p : tai) : boolean;
  254. begin
  255. Result:=(p.typ=ait_instruction) and
  256. ((taicpu(p).opcode in [A_BL,A_BLX,A_CMP,A_CMN,A_SWI,A_TEQ,A_TST,A_CMF,A_CMFE {,A_MSR}]) or
  257. ((taicpu(p).ops>=1) and (taicpu(p).oper[0]^.typ=top_reg) and (taicpu(p).oper[0]^.reg=NR_PC)) or
  258. (taicpu(p).oppostfix=PF_S));
  259. end;
  260. procedure TCpuAsmOptimizer.PeepHoleOptPass2;
  261. var
  262. p,hp1,hp2: tai;
  263. l : longint;
  264. condition : tasmcond;
  265. hp3: tai;
  266. WasLast: boolean;
  267. { UsedRegs, TmpUsedRegs: TRegSet; }
  268. begin
  269. p := BlockStart;
  270. { UsedRegs := []; }
  271. while (p <> BlockEnd) Do
  272. begin
  273. { UpdateUsedRegs(UsedRegs, tai(p.next)); }
  274. case p.Typ Of
  275. Ait_Instruction:
  276. begin
  277. case taicpu(p).opcode Of
  278. A_B:
  279. if taicpu(p).condition<>C_None then
  280. begin
  281. { check for
  282. Bxx xxx
  283. <several instructions>
  284. xxx:
  285. }
  286. l:=0;
  287. WasLast:=False;
  288. GetNextInstruction(p, hp1);
  289. while assigned(hp1) and
  290. (l<=4) and
  291. CanBeCond(hp1) and
  292. { stop on labels }
  293. not(hp1.typ=ait_label) do
  294. begin
  295. inc(l);
  296. if MustBeLast(hp1) then
  297. begin
  298. WasLast:=True;
  299. GetNextInstruction(hp1,hp1);
  300. break;
  301. end
  302. else
  303. GetNextInstruction(hp1,hp1);
  304. end;
  305. if assigned(hp1) then
  306. begin
  307. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  308. begin
  309. if (l<=4) and (l>0) then
  310. begin
  311. condition:=inverse_cond(taicpu(p).condition);
  312. hp2:=p;
  313. GetNextInstruction(p,hp1);
  314. p:=hp1;
  315. repeat
  316. if hp1.typ=ait_instruction then
  317. taicpu(hp1).condition:=condition;
  318. if MustBeLast(hp1) then
  319. begin
  320. GetNextInstruction(hp1,hp1);
  321. break;
  322. end
  323. else
  324. GetNextInstruction(hp1,hp1);
  325. until not(assigned(hp1)) or
  326. not(CanBeCond(hp1)) or
  327. (hp1.typ=ait_label);
  328. { wait with removing else GetNextInstruction could
  329. ignore the label if it was the only usage in the
  330. jump moved away }
  331. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  332. asml.remove(hp2);
  333. hp2.free;
  334. continue;
  335. end;
  336. end
  337. else
  338. { do not perform further optimizations if there is inctructon
  339. in block #1 which can not be optimized.
  340. }
  341. if not WasLast then
  342. begin
  343. { check further for
  344. Bcc xxx
  345. <several instructions 1>
  346. B yyy
  347. xxx:
  348. <several instructions 2>
  349. yyy:
  350. }
  351. { hp2 points to jmp yyy }
  352. hp2:=hp1;
  353. { skip hp1 to xxx }
  354. GetNextInstruction(hp1, hp1);
  355. if assigned(hp2) and
  356. assigned(hp1) and
  357. (l<=3) and
  358. (hp2.typ=ait_instruction) and
  359. (taicpu(hp2).is_jmp) and
  360. (taicpu(hp2).condition=C_None) and
  361. { real label and jump, no further references to the
  362. label are allowed }
  363. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  364. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  365. begin
  366. l:=0;
  367. { skip hp1 to <several moves 2> }
  368. GetNextInstruction(hp1, hp1);
  369. while assigned(hp1) and
  370. CanBeCond(hp1) do
  371. begin
  372. inc(l);
  373. GetNextInstruction(hp1, hp1);
  374. end;
  375. { hp1 points to yyy: }
  376. if assigned(hp1) and
  377. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  378. begin
  379. condition:=inverse_cond(taicpu(p).condition);
  380. GetNextInstruction(p,hp1);
  381. hp3:=p;
  382. p:=hp1;
  383. repeat
  384. if hp1.typ=ait_instruction then
  385. taicpu(hp1).condition:=condition;
  386. GetNextInstruction(hp1,hp1);
  387. until not(assigned(hp1)) or
  388. not(CanBeCond(hp1));
  389. { hp2 is still at jmp yyy }
  390. GetNextInstruction(hp2,hp1);
  391. { hp2 is now at xxx: }
  392. condition:=inverse_cond(condition);
  393. GetNextInstruction(hp1,hp1);
  394. { hp1 is now at <several movs 2> }
  395. repeat
  396. taicpu(hp1).condition:=condition;
  397. GetNextInstruction(hp1,hp1);
  398. until not(assigned(hp1)) or
  399. not(CanBeCond(hp1)) or
  400. (hp1.typ=ait_label);
  401. {
  402. asml.remove(hp1.next)
  403. hp1.next.free;
  404. asml.remove(hp1);
  405. hp1.free;
  406. }
  407. { remove Bcc }
  408. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  409. asml.remove(hp3);
  410. hp3.free;
  411. { remove jmp }
  412. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  413. asml.remove(hp2);
  414. hp2.free;
  415. continue;
  416. end;
  417. end;
  418. end;
  419. end;
  420. end;
  421. end;
  422. end;
  423. end;
  424. p := tai(p.next)
  425. end;
  426. end;
  427. procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
  428. begin
  429. { TODO: Add optimizer code }
  430. end;
  431. begin
  432. casmoptimizer:=TCpuAsmOptimizer;
  433. End.