cpuinfo.pas 24 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv5,
  28. cpu_armv6,
  29. cpu_armv7,
  30. cpu_armv7m,
  31. cpu_cortexm3
  32. );
  33. Const
  34. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv5];
  35. cpu_thumb = [];
  36. cpu_thumb2 = [cpu_armv7m,cpu_cortexm3];
  37. Type
  38. tfputype =
  39. (fpu_none,
  40. fpu_soft,
  41. fpu_libgcc,
  42. fpu_fpa,
  43. fpu_fpa10,
  44. fpu_fpa11,
  45. fpu_vfpv2,
  46. fpu_vfpv3
  47. );
  48. tcontrollertype =
  49. (ct_none,
  50. { Phillips }
  51. ct_lpc2114,
  52. ct_lpc2124,
  53. ct_lpc2194,
  54. { ATMEL }
  55. ct_at91sam7s256,
  56. ct_at91sam7se256,
  57. ct_at91sam7x256,
  58. ct_at91sam7xc256,
  59. { STMicroelectronics }
  60. ct_stm32f103rb,
  61. ct_stm32f103re,
  62. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  63. ct_lm3s1110,
  64. ct_lm3s1133,
  65. ct_lm3s1138,
  66. ct_lm3s1150,
  67. ct_lm3s1162,
  68. ct_lm3s1165,
  69. ct_lm3s1166,
  70. ct_lm3s2110,
  71. ct_lm3s2139,
  72. ct_lm3s6100,
  73. ct_lm3s6110,
  74. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  75. ct_lm3s1601,
  76. ct_lm3s1608,
  77. ct_lm3s1620,
  78. ct_lm3s1635,
  79. ct_lm3s1636,
  80. ct_lm3s1637,
  81. ct_lm3s1651,
  82. ct_lm3s2601,
  83. ct_lm3s2608,
  84. ct_lm3s2620,
  85. ct_lm3s2637,
  86. ct_lm3s2651,
  87. ct_lm3s6610,
  88. ct_lm3s6611,
  89. ct_lm3s6618,
  90. ct_lm3s6633,
  91. ct_lm3s6637,
  92. ct_lm3s8630,
  93. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  94. ct_lm3s1911,
  95. ct_lm3s1918,
  96. ct_lm3s1937,
  97. ct_lm3s1958,
  98. ct_lm3s1960,
  99. ct_lm3s1968,
  100. ct_lm3s1969,
  101. ct_lm3s2911,
  102. ct_lm3s2918,
  103. ct_lm3s2919,
  104. ct_lm3s2939,
  105. ct_lm3s2948,
  106. ct_lm3s2950,
  107. ct_lm3s2965,
  108. ct_lm3s6911,
  109. ct_lm3s6918,
  110. ct_lm3s6938,
  111. ct_lm3s6950,
  112. ct_lm3s6952,
  113. ct_lm3s6965,
  114. ct_lm3s8930,
  115. ct_lm3s8933,
  116. ct_lm3s8938,
  117. ct_lm3s8962,
  118. ct_lm3s8970,
  119. ct_lm3s8971,
  120. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  121. ct_lm3s5951,
  122. ct_lm3s5956,
  123. ct_lm3s1b21,
  124. ct_lm3s2b93,
  125. ct_lm3s5b91,
  126. ct_lm3s9b81,
  127. ct_lm3s9b90,
  128. ct_lm3s9b92,
  129. ct_lm3s9b95,
  130. ct_lm3s9b96,
  131. // generic Thumb2 target
  132. ct_thumb2bare
  133. );
  134. {$I controllerunit.inc}
  135. Const
  136. {# Size of native extended floating point type }
  137. extended_size = 12;
  138. {# Size of a multimedia register }
  139. mmreg_size = 16;
  140. { target cpu string (used by compiler options) }
  141. target_cpu_string = 'arm';
  142. { calling conventions supported by the code generator }
  143. supported_calling_conventions : tproccalloptions = [
  144. pocall_internproc,
  145. pocall_safecall,
  146. pocall_stdcall,
  147. { same as stdcall only different name mangling }
  148. pocall_cdecl,
  149. { same as stdcall only different name mangling }
  150. pocall_cppdecl,
  151. { same as stdcall but floating point numbers are handled like equal sized integers }
  152. pocall_softfloat,
  153. { same as stdcall (requires that all const records are passed by
  154. reference, but that's already done for stdcall) }
  155. pocall_mwpascal,
  156. { used for interrupt handling }
  157. pocall_interrupt
  158. ];
  159. cputypestr : array[tcputype] of string[8] = ('',
  160. 'ARMV3',
  161. 'ARMV4',
  162. 'ARMV5',
  163. 'ARMV6',
  164. 'ARMV7',
  165. 'ARMV7M',
  166. 'CORTEXM3'
  167. );
  168. fputypestr : array[tfputype] of string[6] = ('',
  169. 'SOFT',
  170. 'LIBGCC',
  171. 'FPA',
  172. 'FPA10',
  173. 'FPA11',
  174. 'VFPV2',
  175. 'VFPV3'
  176. );
  177. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  178. ((
  179. controllertypestr:'';
  180. controllerunitstr:'';
  181. interruptvectors:0;
  182. flashbase:0;
  183. flashsize:0;
  184. srambase:0;
  185. sramsize:0
  186. ),
  187. (
  188. controllertypestr:'LPC2114';
  189. controllerunitstr:'LPC21x4';
  190. interruptvectors:8;
  191. flashbase:$00000000;
  192. flashsize:$00040000;
  193. srambase:$40000000;
  194. sramsize:$00004000
  195. ),
  196. (
  197. controllertypestr:'LPC2124';
  198. controllerunitstr:'LPC21x4';
  199. interruptvectors:8;
  200. flashbase:$00000000;
  201. flashsize:$00040000;
  202. srambase:$40000000;
  203. sramsize:$00004000
  204. ),
  205. (
  206. controllertypestr:'LPC2194';
  207. controllerunitstr:'LPC21x4';
  208. interruptvectors:8;
  209. flashbase:$00000000;
  210. flashsize:$00040000;
  211. srambase:$40000000;
  212. sramsize:$00004000
  213. ),
  214. (
  215. controllertypestr:'AT91SAM7S256';
  216. controllerunitstr:'AT91SAM7x256';
  217. interruptvectors:8;
  218. flashbase:$00000000;
  219. flashsize:$00040000;
  220. srambase:$00200000;
  221. sramsize:$00010000
  222. ),
  223. (
  224. controllertypestr:'AT91SAM7SE256';
  225. controllerunitstr:'AT91SAM7x256';
  226. interruptvectors:8;
  227. flashbase:$00000000;
  228. flashsize:$00040000;
  229. srambase:$00200000;
  230. sramsize:$00010000
  231. ),
  232. (
  233. controllertypestr:'AT91SAM7X256';
  234. controllerunitstr:'AT91SAM7x256';
  235. interruptvectors:8;
  236. flashbase:$00000000;
  237. flashsize:$00040000;
  238. srambase:$00200000;
  239. sramsize:$00010000
  240. ),
  241. (
  242. controllertypestr:'AT91SAM7XC256';
  243. controllerunitstr:'AT91SAM7x256';
  244. interruptvectors:8;
  245. flashbase:$00000000;
  246. flashsize:$00040000;
  247. srambase:$00200000;
  248. sramsize:$00010000
  249. ),
  250. // ct_stm32f103rb,
  251. (
  252. controllertypestr:'STM32F103RB';
  253. controllerunitstr:'STM32F103';
  254. interruptvectors:12;
  255. flashbase:$08000000;
  256. flashsize:$00020000;
  257. srambase:$20000000;
  258. sramsize:$00005000
  259. ),
  260. // ct_stm32f103re,
  261. (
  262. controllertypestr:'STM32F103RE';
  263. controllerunitstr:'STM32F103';
  264. interruptvectors:12;
  265. flashbase:$08000000;
  266. flashsize:$00080000;
  267. srambase:$20000000;
  268. sramsize:$00010000
  269. ),
  270. { TI - 64 K Flash, 16 K SRAM Devices }
  271. // ct_lm3s1110,
  272. (
  273. controllertypestr:'LM3S1110';
  274. controllerunitstr:'LM3FURY';
  275. interruptvectors:72;
  276. flashbase:$00000000;
  277. flashsize:$00010000;
  278. srambase:$20000000;
  279. sramsize:$00004000
  280. ),
  281. // ct_lm3s1133,
  282. (
  283. controllertypestr:'LM3S1133';
  284. controllerunitstr:'LM3FURY';
  285. interruptvectors:72;
  286. flashbase:$00000000;
  287. flashsize:$00010000;
  288. srambase:$20000000;
  289. sramsize:$00004000
  290. ),
  291. // ct_lm3s1138,
  292. (
  293. controllertypestr:'LM3S1138';
  294. controllerunitstr:'LM3FURY';
  295. interruptvectors:72;
  296. flashbase:$00000000;
  297. flashsize:$00010000;
  298. srambase:$20000000;
  299. sramsize:$00004000
  300. ),
  301. // ct_lm3s1150,
  302. (
  303. controllertypestr:'LM3S1150';
  304. controllerunitstr:'LM3FURY';
  305. interruptvectors:72;
  306. flashbase:$00000000;
  307. flashsize:$00010000;
  308. srambase:$20000000;
  309. sramsize:$00004000
  310. ),
  311. // ct_lm3s1162,
  312. (
  313. controllertypestr:'LM3S1162';
  314. controllerunitstr:'LM3FURY';
  315. interruptvectors:72;
  316. flashbase:$00000000;
  317. flashsize:$00010000;
  318. srambase:$20000000;
  319. sramsize:$00004000
  320. ),
  321. // ct_lm3s1165,
  322. (
  323. controllertypestr:'LM3S1165';
  324. controllerunitstr:'LM3FURY';
  325. interruptvectors:72;
  326. flashbase:$00000000;
  327. flashsize:$00010000;
  328. srambase:$20000000;
  329. sramsize:$00004000
  330. ),
  331. // ct_lm3s1166,
  332. (
  333. controllertypestr:'LM3S1166';
  334. controllerunitstr:'LM3FURY';
  335. interruptvectors:72;
  336. flashbase:$00000000;
  337. flashsize:$00010000;
  338. srambase:$20000000;
  339. sramsize:$00004000
  340. ),
  341. // ct_lm3s2110,
  342. (
  343. controllertypestr:'LM3S2110';
  344. controllerunitstr:'LM3FURY';
  345. interruptvectors:72;
  346. flashbase:$00000000;
  347. flashsize:$00010000;
  348. srambase:$20000000;
  349. sramsize:$00004000
  350. ),
  351. // ct_lm3s2139,
  352. (
  353. controllertypestr:'LM3S2139';
  354. controllerunitstr:'LM3FURY';
  355. interruptvectors:72;
  356. flashbase:$00000000;
  357. flashsize:$00010000;
  358. srambase:$20000000;
  359. sramsize:$00004000
  360. ),
  361. // ct_lm3s6100,
  362. (
  363. controllertypestr:'LM3S6100';
  364. controllerunitstr:'LM3FURY';
  365. interruptvectors:72;
  366. flashbase:$00000000;
  367. flashsize:$00010000;
  368. srambase:$20000000;
  369. sramsize:$00004000
  370. ),
  371. // ct_lm3s6110,
  372. (
  373. controllertypestr:'LM3S6110';
  374. controllerunitstr:'LM3FURY';
  375. interruptvectors:72;
  376. flashbase:$00000000;
  377. flashsize:$00010000;
  378. srambase:$20000000;
  379. sramsize:$00004000
  380. ),
  381. { TI - 128K Flash, 32K SRAM devices }
  382. // ct_lm3s1601,
  383. (
  384. controllertypestr:'LM3S1601';
  385. controllerunitstr:'LM3FURY';
  386. interruptvectors:72;
  387. flashbase:$00000000;
  388. flashsize:$00020000;
  389. srambase:$20000000;
  390. sramsize:$00008000
  391. ),
  392. // ct_lm3s1608,
  393. (
  394. controllertypestr:'LM3S1608';
  395. controllerunitstr:'LM3FURY';
  396. interruptvectors:72;
  397. flashbase:$00000000;
  398. flashsize:$00020000;
  399. srambase:$20000000;
  400. sramsize:$00008000
  401. ),
  402. // ct_lm3s1620,
  403. (
  404. controllertypestr:'LM3S1620';
  405. controllerunitstr:'LM3FURY';
  406. interruptvectors:72;
  407. flashbase:$00000000;
  408. flashsize:$00020000;
  409. srambase:$20000000;
  410. sramsize:$00008000
  411. ),
  412. // ct_lm3s1635,
  413. (
  414. controllertypestr:'LM3S1635';
  415. controllerunitstr:'LM3FURY';
  416. interruptvectors:72;
  417. flashbase:$00000000;
  418. flashsize:$00020000;
  419. srambase:$20000000;
  420. sramsize:$00008000
  421. ),
  422. // ct_lm3s1636,
  423. (
  424. controllertypestr:'LM3S1636';
  425. controllerunitstr:'LM3FURY';
  426. interruptvectors:72;
  427. flashbase:$00000000;
  428. flashsize:$00020000;
  429. srambase:$20000000;
  430. sramsize:$00008000
  431. ),
  432. // ct_lm3s1637,
  433. (
  434. controllertypestr:'LM3S1637';
  435. controllerunitstr:'LM3FURY';
  436. interruptvectors:72;
  437. flashbase:$00000000;
  438. flashsize:$00020000;
  439. srambase:$20000000;
  440. sramsize:$00008000
  441. ),
  442. // ct_lm3s1651,
  443. (
  444. controllertypestr:'LM3S1651';
  445. controllerunitstr:'LM3FURY';
  446. interruptvectors:72;
  447. flashbase:$00000000;
  448. flashsize:$00020000;
  449. srambase:$20000000;
  450. sramsize:$00008000
  451. ),
  452. // ct_lm3s2601,
  453. (
  454. controllertypestr:'LM3S2601';
  455. controllerunitstr:'LM3FURY';
  456. interruptvectors:72;
  457. flashbase:$00000000;
  458. flashsize:$00020000;
  459. srambase:$20000000;
  460. sramsize:$00008000
  461. ),
  462. // ct_lm3s2608,
  463. (
  464. controllertypestr:'LM3S2608';
  465. controllerunitstr:'LM3FURY';
  466. interruptvectors:72;
  467. flashbase:$00000000;
  468. flashsize:$00020000;
  469. srambase:$20000000;
  470. sramsize:$00008000
  471. ),
  472. // ct_lm3s2620,
  473. (
  474. controllertypestr:'LM3S2620';
  475. controllerunitstr:'LM3FURY';
  476. interruptvectors:72;
  477. flashbase:$00000000;
  478. flashsize:$00020000;
  479. srambase:$20000000;
  480. sramsize:$00008000
  481. ),
  482. // ct_lm3s2637,
  483. (
  484. controllertypestr:'LM3S2637';
  485. controllerunitstr:'LM3FURY';
  486. interruptvectors:72;
  487. flashbase:$00000000;
  488. flashsize:$00020000;
  489. srambase:$20000000;
  490. sramsize:$00008000
  491. ),
  492. // ct_lm3s2651,
  493. (
  494. controllertypestr:'LM3S2651';
  495. controllerunitstr:'LM3FURY';
  496. interruptvectors:72;
  497. flashbase:$00000000;
  498. flashsize:$00020000;
  499. srambase:$20000000;
  500. sramsize:$00008000
  501. ),
  502. // ct_lm3s6610,
  503. (
  504. controllertypestr:'LM3S6610';
  505. controllerunitstr:'LM3FURY';
  506. interruptvectors:72;
  507. flashbase:$00000000;
  508. flashsize:$00020000;
  509. srambase:$20000000;
  510. sramsize:$00008000
  511. ),
  512. // ct_lm3s6611,
  513. (
  514. controllertypestr:'LM3S6611';
  515. controllerunitstr:'LM3FURY';
  516. interruptvectors:72;
  517. flashbase:$00000000;
  518. flashsize:$00020000;
  519. srambase:$20000000;
  520. sramsize:$00008000
  521. ),
  522. // ct_lm3s6618,
  523. (
  524. controllertypestr:'LM3S6618';
  525. controllerunitstr:'LM3FURY';
  526. interruptvectors:72;
  527. flashbase:$00000000;
  528. flashsize:$00020000;
  529. srambase:$20000000;
  530. sramsize:$00008000
  531. ),
  532. // ct_lm3s6633,
  533. (
  534. controllertypestr:'LM3S6633';
  535. controllerunitstr:'LM3FURY';
  536. interruptvectors:72;
  537. flashbase:$00000000;
  538. flashsize:$00020000;
  539. srambase:$20000000;
  540. sramsize:$00008000
  541. ),
  542. // ct_lm3s6637,
  543. (
  544. controllertypestr:'LM3S6637';
  545. controllerunitstr:'LM3FURY';
  546. interruptvectors:72;
  547. flashbase:$00000000;
  548. flashsize:$00020000;
  549. srambase:$20000000;
  550. sramsize:$00008000
  551. ),
  552. // ct_lm3s8630,
  553. (
  554. controllertypestr:'LM3S8630';
  555. controllerunitstr:'LM3FURY';
  556. interruptvectors:72;
  557. flashbase:$00000000;
  558. flashsize:$00020000;
  559. srambase:$20000000;
  560. sramsize:$00008000
  561. ),
  562. { TI - 256K Flash, 64K SRAM devices }
  563. // ct_lm3s1911,
  564. (
  565. controllertypestr:'LM3S1911';
  566. controllerunitstr:'LM3FURY';
  567. interruptvectors:72;
  568. flashbase:$00000000;
  569. flashsize:$00040000;
  570. srambase:$20000000;
  571. sramsize:$00010000
  572. ),
  573. // ct_lm3s1918,
  574. (
  575. controllertypestr:'LM3S1918';
  576. controllerunitstr:'LM3FURY';
  577. interruptvectors:72;
  578. flashbase:$00000000;
  579. flashsize:$00040000;
  580. srambase:$20000000;
  581. sramsize:$00010000
  582. ),
  583. // ct_lm3s1937,
  584. (
  585. controllertypestr:'LM3S1937';
  586. controllerunitstr:'LM3FURY';
  587. interruptvectors:72;
  588. flashbase:$00000000;
  589. flashsize:$00040000;
  590. srambase:$20000000;
  591. sramsize:$00010000
  592. ),
  593. // ct_lm3s1958,
  594. (
  595. controllertypestr:'LM3S1958';
  596. controllerunitstr:'LM3FURY';
  597. interruptvectors:72;
  598. flashbase:$00000000;
  599. flashsize:$00040000;
  600. srambase:$20000000;
  601. sramsize:$00010000
  602. ),
  603. // ct_lm3s1960,
  604. (
  605. controllertypestr:'LM3S1960';
  606. controllerunitstr:'LM3FURY';
  607. interruptvectors:72;
  608. flashbase:$00000000;
  609. flashsize:$00040000;
  610. srambase:$20000000;
  611. sramsize:$00010000
  612. ),
  613. // ct_lm3s1968,
  614. (
  615. controllertypestr:'LM3S1968';
  616. controllerunitstr:'LM3FURY';
  617. interruptvectors:72;
  618. flashbase:$00000000;
  619. flashsize:$00040000;
  620. srambase:$20000000;
  621. sramsize:$00010000
  622. ),
  623. // ct_lm3s1969,
  624. (
  625. controllertypestr:'LM3S1969';
  626. controllerunitstr:'LM3FURY';
  627. interruptvectors:72;
  628. flashbase:$00000000;
  629. flashsize:$00040000;
  630. srambase:$20000000;
  631. sramsize:$00010000
  632. ),
  633. // ct_lm3s2911,
  634. (
  635. controllertypestr:'LM3S2911';
  636. controllerunitstr:'LM3FURY';
  637. interruptvectors:72;
  638. flashbase:$00000000;
  639. flashsize:$00040000;
  640. srambase:$20000000;
  641. sramsize:$00010000
  642. ),
  643. // ct_lm3s2918,
  644. (
  645. controllertypestr:'LM3S2918';
  646. controllerunitstr:'LM3FURY';
  647. interruptvectors:72;
  648. flashbase:$00000000;
  649. flashsize:$00040000;
  650. srambase:$20000000;
  651. sramsize:$00010000
  652. ),
  653. // ct_lm3s2919,
  654. (
  655. controllertypestr:'LM3S2919';
  656. controllerunitstr:'LM3FURY';
  657. interruptvectors:72;
  658. flashbase:$00000000;
  659. flashsize:$00040000;
  660. srambase:$20000000;
  661. sramsize:$00010000
  662. ),
  663. // ct_lm3s2939,
  664. (
  665. controllertypestr:'LM3S2939';
  666. controllerunitstr:'LM3FURY';
  667. interruptvectors:72;
  668. flashbase:$00000000;
  669. flashsize:$00040000;
  670. srambase:$20000000;
  671. sramsize:$00010000
  672. ),
  673. // ct_lm3s2948,
  674. (
  675. controllertypestr:'LM3S2948';
  676. controllerunitstr:'LM3FURY';
  677. interruptvectors:72;
  678. flashbase:$00000000;
  679. flashsize:$00040000;
  680. srambase:$20000000;
  681. sramsize:$00010000
  682. ),
  683. // ct_lm3s2950,
  684. (
  685. controllertypestr:'LM3S2950';
  686. controllerunitstr:'LM3FURY';
  687. interruptvectors:72;
  688. flashbase:$00000000;
  689. flashsize:$00040000;
  690. srambase:$20000000;
  691. sramsize:$00010000
  692. ),
  693. // ct_lm3s2965,
  694. (
  695. controllertypestr:'LM3S2965';
  696. controllerunitstr:'LM3FURY';
  697. interruptvectors:72;
  698. flashbase:$00000000;
  699. flashsize:$00040000;
  700. srambase:$20000000;
  701. sramsize:$00010000
  702. ),
  703. // ct_lm3s6911,
  704. (
  705. controllertypestr:'LM3S6911';
  706. controllerunitstr:'LM3FURY';
  707. interruptvectors:72;
  708. flashbase:$00000000;
  709. flashsize:$00040000;
  710. srambase:$20000000;
  711. sramsize:$00010000
  712. ),
  713. // ct_lm3s6918,
  714. (
  715. controllertypestr:'LM3S6918';
  716. controllerunitstr:'LM3FURY';
  717. interruptvectors:72;
  718. flashbase:$00000000;
  719. flashsize:$00040000;
  720. srambase:$20000000;
  721. sramsize:$00010000
  722. ),
  723. // ct_lm3s6938,
  724. (
  725. controllertypestr:'LM3S6938';
  726. controllerunitstr:'LM3FURY';
  727. interruptvectors:72;
  728. flashbase:$00000000;
  729. flashsize:$00040000;
  730. srambase:$20000000;
  731. sramsize:$00010000
  732. ),
  733. // ct_lm3s6950,
  734. (
  735. controllertypestr:'LM3S6950';
  736. controllerunitstr:'LM3FURY';
  737. interruptvectors:72;
  738. flashbase:$00000000;
  739. flashsize:$00040000;
  740. srambase:$20000000;
  741. sramsize:$00010000
  742. ),
  743. // ct_lm3s6952,
  744. (
  745. controllertypestr:'LM3S6952';
  746. controllerunitstr:'LM3FURY';
  747. interruptvectors:72;
  748. flashbase:$00000000;
  749. flashsize:$00040000;
  750. srambase:$20000000;
  751. sramsize:$00010000
  752. ),
  753. // ct_lm3s6965,
  754. (
  755. controllertypestr:'LM3S6965';
  756. controllerunitstr:'LM3FURY';
  757. interruptvectors:72;
  758. flashbase:$00000000;
  759. flashsize:$00040000;
  760. srambase:$20000000;
  761. sramsize:$00010000
  762. ),
  763. // ct_lm3s8930,
  764. (
  765. controllertypestr:'LM3S8930';
  766. controllerunitstr:'LM3FURY';
  767. interruptvectors:72;
  768. flashbase:$00000000;
  769. flashsize:$00040000;
  770. srambase:$20000000;
  771. sramsize:$00010000
  772. ),
  773. // ct_lm3s8933,
  774. (
  775. controllertypestr:'LM3S8933';
  776. controllerunitstr:'LM3FURY';
  777. interruptvectors:72;
  778. flashbase:$00000000;
  779. flashsize:$00040000;
  780. srambase:$20000000;
  781. sramsize:$00010000
  782. ),
  783. // ct_lm3s8938,
  784. (
  785. controllertypestr:'LM3S8938';
  786. controllerunitstr:'LM3FURY';
  787. interruptvectors:72;
  788. flashbase:$00000000;
  789. flashsize:$00040000;
  790. srambase:$20000000;
  791. sramsize:$00010000
  792. ),
  793. // ct_lm3s8962,
  794. (
  795. controllertypestr:'LM3S8962';
  796. controllerunitstr:'LM3FURY';
  797. interruptvectors:72;
  798. flashbase:$00000000;
  799. flashsize:$00040000;
  800. srambase:$20000000;
  801. sramsize:$00010000
  802. ),
  803. // ct_lm3s8970,
  804. (
  805. controllertypestr:'LM3S8970';
  806. controllerunitstr:'LM3FURY';
  807. interruptvectors:72;
  808. flashbase:$00000000;
  809. flashsize:$00040000;
  810. srambase:$20000000;
  811. sramsize:$00010000
  812. ),
  813. // ct_lm3s8971,
  814. (
  815. controllertypestr:'LM3S8971';
  816. controllerunitstr:'LM3FURY';
  817. interruptvectors:72;
  818. flashbase:$00000000;
  819. flashsize:$00040000;
  820. srambase:$20000000;
  821. sramsize:$00010000
  822. ),
  823. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  824. // ct_lm3s5951,
  825. (
  826. controllertypestr:'LM3S5951';
  827. controllerunitstr:'LM3TEMPEST';
  828. interruptvectors:72;
  829. flashbase:$00000000;
  830. flashsize:$00040000;
  831. srambase:$20000000;
  832. sramsize:$00010000
  833. ),
  834. // ct_lm3s5956,
  835. (
  836. controllertypestr:'LM3S5956';
  837. controllerunitstr:'LM3TEMPEST';
  838. interruptvectors:72;
  839. flashbase:$00000000;
  840. flashsize:$00040000;
  841. srambase:$20000000;
  842. sramsize:$00010000
  843. ),
  844. // ct_lm3s1b21,
  845. (
  846. controllertypestr:'LM3S1B21';
  847. controllerunitstr:'LM3TEMPEST';
  848. interruptvectors:72;
  849. flashbase:$00000000;
  850. flashsize:$00040000;
  851. srambase:$20000000;
  852. sramsize:$00010000
  853. ),
  854. // ct_lm3s2b93,
  855. (
  856. controllertypestr:'LM3S2B93';
  857. controllerunitstr:'LM3TEMPEST';
  858. interruptvectors:72;
  859. flashbase:$00000000;
  860. flashsize:$00040000;
  861. srambase:$20000000;
  862. sramsize:$00010000
  863. ),
  864. // ct_lm3s5b91,
  865. (
  866. controllertypestr:'LM3S5B91';
  867. controllerunitstr:'LM3TEMPEST';
  868. interruptvectors:72;
  869. flashbase:$00000000;
  870. flashsize:$00040000;
  871. srambase:$20000000;
  872. sramsize:$00010000
  873. ),
  874. // ct_lm3s9b81,
  875. (
  876. controllertypestr:'LM3S9B81';
  877. controllerunitstr:'LM3TEMPEST';
  878. interruptvectors:72;
  879. flashbase:$00000000;
  880. flashsize:$00040000;
  881. srambase:$20000000;
  882. sramsize:$00010000
  883. ),
  884. // ct_lm3s9b90,
  885. (
  886. controllertypestr:'LM3S9B90';
  887. controllerunitstr:'LM3TEMPEST';
  888. interruptvectors:72;
  889. flashbase:$00000000;
  890. flashsize:$00040000;
  891. srambase:$20000000;
  892. sramsize:$00010000
  893. ),
  894. // ct_lm3s9b92,
  895. (
  896. controllertypestr:'LM3S9B92';
  897. controllerunitstr:'LM3TEMPEST';
  898. interruptvectors:72;
  899. flashbase:$00000000;
  900. flashsize:$00040000;
  901. srambase:$20000000;
  902. sramsize:$00010000
  903. ),
  904. // ct_lm3s9b95,
  905. (
  906. controllertypestr:'LM3S9B95';
  907. controllerunitstr:'LM3TEMPEST';
  908. interruptvectors:72;
  909. flashbase:$00000000;
  910. flashsize:$00040000;
  911. srambase:$20000000;
  912. sramsize:$00010000
  913. ),
  914. // ct_lm3s9b96,
  915. (
  916. controllertypestr:'LM3S9B96';
  917. controllerunitstr:'LM3TEMPEST';
  918. interruptvectors:72;
  919. flashbase:$00000000;
  920. flashsize:$00040000;
  921. srambase:$20000000;
  922. sramsize:$00010000
  923. ),
  924. // bare bones Thumb2
  925. (
  926. controllertypestr:'THUMB2_BARE';
  927. controllerunitstr:'THUMB2_BARE';
  928. interruptvectors:128;
  929. flashbase:$00000000;
  930. flashsize:$00100000;
  931. srambase:$20000000;
  932. sramsize:$00100000
  933. )
  934. );
  935. vfp_scalar = [fpu_vfpv2,fpu_vfpv3];
  936. { Supported optimizations, only used for information }
  937. supported_optimizerswitches = genericlevel1optimizerswitches+
  938. genericlevel2optimizerswitches+
  939. genericlevel3optimizerswitches-
  940. { no need to write info about those }
  941. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  942. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  943. cs_opt_stackframe,cs_opt_nodecse];
  944. level1optimizerswitches = genericlevel1optimizerswitches;
  945. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  946. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  947. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  948. Implementation
  949. end.