cgcpu.pas 90 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2002 by Florian Klaempfl
  4. This unit implements the code generator for the PowerPC
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgobj,
  24. aasmbase,aasmcpu,aasmtai,
  25. cpubase,cpuinfo,cgutils,cg64f32,rgcpu,
  26. parabase;
  27. type
  28. tcgppc = class(tcg)
  29. procedure init_register_allocators;override;
  30. procedure done_register_allocators;override;
  31. { passing parameters, per default the parameter is pushed }
  32. { nr gives the number of the parameter (enumerated from }
  33. { left to right), this allows to move the parameter to }
  34. { register, if the cpu supports register calling }
  35. { conventions }
  36. procedure a_param_const(list : taasmoutput;size : tcgsize;a : aint;const paraloc : tcgpara);override;
  37. procedure a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const paraloc : tcgpara);override;
  38. procedure a_paramaddr_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);override;
  39. procedure a_call_name(list : taasmoutput;const s : string);override;
  40. procedure a_call_reg(list : taasmoutput;reg: tregister); override;
  41. procedure a_op_const_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister); override;
  42. procedure a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  43. procedure a_op_const_reg_reg(list: taasmoutput; op: TOpCg;
  44. size: tcgsize; a: aint; src, dst: tregister); override;
  45. procedure a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
  46. size: tcgsize; src1, src2, dst: tregister); override;
  47. { move instructions }
  48. procedure a_load_const_reg(list : taasmoutput; size: tcgsize; a : aint;reg : tregister);override;
  49. procedure a_load_reg_ref(list : taasmoutput; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  50. procedure a_load_ref_reg(list : taasmoutput; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  51. procedure a_load_reg_reg(list : taasmoutput; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  52. { fpu move instructions }
  53. procedure a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister); override;
  54. procedure a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister); override;
  55. procedure a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference); override;
  56. { comparison operations }
  57. procedure a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  58. l : tasmlabel);override;
  59. procedure a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  60. procedure a_jmp_name(list : taasmoutput;const s : string); override;
  61. procedure a_jmp_always(list : taasmoutput;l: tasmlabel); override;
  62. procedure a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel); override;
  63. procedure g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  64. procedure g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);override;
  65. procedure g_proc_exit(list : taasmoutput;parasize : longint;nostackframe:boolean); override;
  66. procedure g_save_standard_registers(list:Taasmoutput); override;
  67. procedure g_restore_standard_registers(list:Taasmoutput); override;
  68. procedure a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);override;
  69. procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aint);override;
  70. procedure g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef); override;
  71. { find out whether a is of the form 11..00..11b or 00..11...00. If }
  72. { that's the case, we can use rlwinm to do an AND operation }
  73. function get_rlwi_const(a: aint; var l1, l2: longint): boolean;
  74. procedure a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
  75. procedure g_intf_wrapper(list: TAAsmoutput; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  76. private
  77. (* NOT IN USE: *)
  78. procedure g_stackframe_entry_mac(list : taasmoutput;localsize : longint);
  79. (* NOT IN USE: *)
  80. procedure g_return_from_proc_mac(list : taasmoutput;parasize : aint);
  81. { Make sure ref is a valid reference for the PowerPC and sets the }
  82. { base to the value of the index if (base = R_NO). }
  83. { Returns true if the reference contained a base, index and an }
  84. { offset or symbol, in which case the base will have been changed }
  85. { to a tempreg (which has to be freed by the caller) containing }
  86. { the sum of part of the original reference }
  87. function fixref(list: taasmoutput; var ref: treference): boolean;
  88. { returns whether a reference can be used immediately in a powerpc }
  89. { instruction }
  90. function issimpleref(const ref: treference): boolean;
  91. { contains the common code of a_load_reg_ref and a_load_ref_reg }
  92. procedure a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
  93. ref: treference);
  94. { creates the correct branch instruction for a given combination }
  95. { of asmcondflags and destination addressing mode }
  96. procedure a_jmp(list: taasmoutput; op: tasmop;
  97. c: tasmcondflag; crval: longint; l: tasmlabel);
  98. function save_regs(list : taasmoutput):longint;
  99. procedure restore_regs(list : taasmoutput);
  100. function get_darwin_call_stub(const s: string): tasmsymbol;
  101. end;
  102. tcg64fppc = class(tcg64f32)
  103. procedure a_op64_reg_reg(list : taasmoutput;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  104. procedure a_op64_const_reg(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  105. procedure a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
  106. procedure a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  107. end;
  108. const
  109. TOpCG2AsmOpConstLo: Array[topcg] of TAsmOp = (A_NONE,A_ADDI,A_ANDI_,A_DIVWU,
  110. A_DIVW,A_MULLW, A_MULLW, A_NONE,A_NONE,A_ORI,
  111. A_SRAWI,A_SLWI,A_SRWI,A_SUBI,A_XORI);
  112. TOpCG2AsmOpConstHi: Array[topcg] of TAsmOp = (A_NONE,A_ADDIS,A_ANDIS_,
  113. A_DIVWU,A_DIVW, A_MULLW,A_MULLW,A_NONE,A_NONE,
  114. A_ORIS,A_NONE, A_NONE,A_NONE,A_SUBIS,A_XORIS);
  115. TOpCmp2AsmCond: Array[topcmp] of TAsmCondFlag = (C_NONE,C_EQ,C_GT,
  116. C_LT,C_GE,C_LE,C_NE,C_LE,C_LT,C_GE,C_GT);
  117. implementation
  118. uses
  119. globals,verbose,systems,cutils,
  120. symconst,symsym,fmodule,
  121. rgobj,tgobj,cpupi,procinfo,paramgr;
  122. procedure tcgppc.init_register_allocators;
  123. begin
  124. inherited init_register_allocators;
  125. if target_info.system=system_powerpc_darwin then
  126. begin
  127. if pi_needs_got in current_procinfo.flags then
  128. begin
  129. current_procinfo.got:=NR_R31;
  130. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  131. [RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  132. RS_R9,RS_R10,RS_R11,RS_R12,RS_R30,RS_R29,
  133. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  134. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  135. RS_R14,RS_R13],first_int_imreg,[]);
  136. end
  137. else
  138. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  139. [RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  140. RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
  141. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  142. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  143. RS_R14,RS_R13],first_int_imreg,[]);
  144. end
  145. else
  146. rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
  147. [RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  148. RS_R9,RS_R10,RS_R11,RS_R12,RS_R31,RS_R30,RS_R29,
  149. RS_R28,RS_R27,RS_R26,RS_R25,RS_R24,RS_R23,RS_R22,
  150. RS_R21,RS_R20,RS_R19,RS_R18,RS_R17,RS_R16,RS_R15,
  151. RS_R14,RS_R13],first_int_imreg,[]);
  152. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  153. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,
  154. RS_F10,RS_F11,RS_F12,RS_F13,RS_F31,RS_F30,RS_F29,RS_F28,RS_F27,
  155. RS_F26,RS_F25,RS_F24,RS_F23,RS_F22,RS_F21,RS_F20,RS_F19,RS_F18,
  156. RS_F17,RS_F16,RS_F15,RS_F14],first_fpu_imreg,[]);
  157. {$warning FIX ME}
  158. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
  159. [RS_M0,RS_M1,RS_M2],first_mm_imreg,[]);
  160. end;
  161. procedure tcgppc.done_register_allocators;
  162. begin
  163. rg[R_INTREGISTER].free;
  164. rg[R_FPUREGISTER].free;
  165. rg[R_MMREGISTER].free;
  166. inherited done_register_allocators;
  167. end;
  168. procedure tcgppc.a_param_const(list : taasmoutput;size : tcgsize;a : aint;const paraloc : tcgpara);
  169. var
  170. ref: treference;
  171. begin
  172. paraloc.check_simple_location;
  173. case paraloc.location^.loc of
  174. LOC_REGISTER,LOC_CREGISTER:
  175. a_load_const_reg(list,size,a,paraloc.location^.register);
  176. LOC_REFERENCE:
  177. begin
  178. reference_reset(ref);
  179. ref.base:=paraloc.location^.reference.index;
  180. ref.offset:=paraloc.location^.reference.offset;
  181. a_load_const_ref(list,size,a,ref);
  182. end;
  183. else
  184. internalerror(2002081101);
  185. end;
  186. end;
  187. procedure tcgppc.a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const paraloc : tcgpara);
  188. var
  189. tmpref, ref: treference;
  190. location: pcgparalocation;
  191. sizeleft: aint;
  192. begin
  193. location := paraloc.location;
  194. tmpref := r;
  195. sizeleft := paraloc.intsize;
  196. while assigned(location) do
  197. begin
  198. case location^.loc of
  199. LOC_REGISTER,LOC_CREGISTER:
  200. begin
  201. {$ifndef cpu64bit}
  202. if (sizeleft <> 3) then
  203. begin
  204. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  205. { the following is only for AIX abi systems, but the }
  206. { conditions should never be true for SYSV (if they }
  207. { are, there is a bug in cpupara) }
  208. { update: this doesn't work yet (we have to shift }
  209. { right again in ncgutil when storing the parameters, }
  210. { and additionally Apple's documentation seems to be }
  211. { wrong, in that these values are always kept in the }
  212. { lower bytes of the registers }
  213. {
  214. if (paraloc.composite) and
  215. (sizeleft <= 2) and
  216. ((paraloc.intsize > 4) or
  217. (target_info.system <> system_powerpc_darwin)) then
  218. begin
  219. case sizeleft of
  220. 1:
  221. a_op_const_reg(list,OP_SHL,OS_INT,24,location^.register);
  222. 2:
  223. a_op_const_reg(list,OP_SHL,OS_INT,16,location^.register);
  224. else
  225. internalerror(2005010910);
  226. end;
  227. end;
  228. }
  229. end
  230. else
  231. begin
  232. a_load_ref_reg(list,OS_16,OS_16,tmpref,location^.register);
  233. a_reg_alloc(list,NR_R0);
  234. inc(tmpref.offset,2);
  235. a_load_ref_reg(list,OS_8,OS_8,tmpref,newreg(R_INTREGISTER,RS_R0,R_SUBNONE));
  236. a_op_const_reg(list,OP_SHL,OS_INT,16,location^.register);
  237. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,location^.register,newreg(R_INTREGISTER,RS_R0,R_SUBNONE),8,16,31-8));
  238. a_reg_dealloc(list,NR_R0);
  239. dec(tmpref.offset,2);
  240. end;
  241. {$else not cpu64bit}
  242. {$error add 64 bit support for non power of 2 loads in a_param_ref}
  243. {$endif not cpu64bit}
  244. end;
  245. LOC_REFERENCE:
  246. begin
  247. reference_reset_base(ref,location^.reference.index,location^.reference.offset);
  248. g_concatcopy(list,tmpref,ref,sizeleft);
  249. if assigned(location^.next) then
  250. internalerror(2005010710);
  251. end;
  252. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  253. case location^.size of
  254. OS_F32, OS_F64:
  255. a_loadfpu_ref_reg(list,location^.size,tmpref,location^.register);
  256. else
  257. internalerror(2002072801);
  258. end;
  259. LOC_VOID:
  260. begin
  261. // nothing to do
  262. end;
  263. else
  264. internalerror(2002081103);
  265. end;
  266. inc(tmpref.offset,tcgsize2size[location^.size]);
  267. dec(sizeleft,tcgsize2size[location^.size]);
  268. location := location^.next;
  269. end;
  270. end;
  271. procedure tcgppc.a_paramaddr_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);
  272. var
  273. ref: treference;
  274. tmpreg: tregister;
  275. begin
  276. paraloc.check_simple_location;
  277. case paraloc.location^.loc of
  278. LOC_REGISTER,LOC_CREGISTER:
  279. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  280. LOC_REFERENCE:
  281. begin
  282. reference_reset(ref);
  283. ref.base := paraloc.location^.reference.index;
  284. ref.offset := paraloc.location^.reference.offset;
  285. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  286. a_loadaddr_ref_reg(list,r,tmpreg);
  287. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  288. end;
  289. else
  290. internalerror(2002080701);
  291. end;
  292. end;
  293. function tcgppc.get_darwin_call_stub(const s: string): tasmsymbol;
  294. var
  295. stubname: string;
  296. href: treference;
  297. l1: tasmsymbol;
  298. begin
  299. { function declared in the current unit? }
  300. result := objectlibrary.getasmsymbol(s);
  301. if not(assigned(result)) then
  302. begin
  303. stubname := 'L'+s+'$stub';
  304. result := objectlibrary.getasmsymbol(stubname);
  305. end;
  306. if assigned(result) then
  307. exit;
  308. if not(assigned(importssection)) then
  309. importssection:=TAAsmoutput.create;
  310. importsSection.concat(Tai_section.Create(sec_data,'',0));
  311. importsSection.concat(Tai_direct.create(strpnew('.section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16')));
  312. importsSection.concat(Tai_align.Create(4));
  313. result := objectlibrary.newasmsymbol(stubname,AB_EXTERNAL,AT_FUNCTION);
  314. importsSection.concat(Tai_symbol.Create(result,0));
  315. importsSection.concat(Tai_direct.create(strpnew((#9+'.indirect_symbol ')+s)));
  316. l1 := objectlibrary.newasmsymbol('L'+s+'$lazy_ptr',AB_EXTERNAL,AT_FUNCTION);
  317. reference_reset_symbol(href,l1,0);
  318. {$ifdef powerpc}
  319. href.refaddr := addr_hi;
  320. importsSection.concat(taicpu.op_reg_ref(A_LIS,NR_R11,href));
  321. href.refaddr := addr_lo;
  322. href.base := NR_R11;
  323. importsSection.concat(taicpu.op_reg_ref(A_LWZU,NR_R12,href));
  324. importsSection.concat(taicpu.op_reg(A_MTCTR,NR_R12));
  325. importsSection.concat(taicpu.op_none(A_BCTR));
  326. {$else powerpc}
  327. internalerror(2004010502);
  328. {$endif powerpc}
  329. importsSection.concat(Tai_section.Create(sec_data,'',0));
  330. importsSection.concat(Tai_direct.create(strpnew('.lazy_symbol_pointer')));
  331. importsSection.concat(Tai_symbol.Create(l1,0));
  332. importsSection.concat(Tai_direct.create(strpnew((#9+'.indirect_symbol ')+s)));
  333. importsSection.concat(tai_const.createname(strpnew('dyld_stub_binding_helper'),AT_FUNCTION,0));
  334. end;
  335. { calling a procedure by name }
  336. procedure tcgppc.a_call_name(list : taasmoutput;const s : string);
  337. begin
  338. { MacOS: The linker on MacOS (PPCLink) inserts a call to glue code,
  339. if it is a cross-TOC call. If so, it also replaces the NOP
  340. with some restore code.}
  341. if (target_info.system <> system_powerpc_darwin) then
  342. begin
  343. list.concat(taicpu.op_sym(A_BL,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION)));
  344. if target_info.system=system_powerpc_macos then
  345. list.concat(taicpu.op_none(A_NOP));
  346. end
  347. else
  348. begin
  349. list.concat(taicpu.op_sym(A_BL,get_darwin_call_stub(s)));
  350. end;
  351. {
  352. the compiler does not properly set this flag anymore in pass 1, and
  353. for now we only need it after pass 2 (I hope) (JM)
  354. if not(pi_do_call in current_procinfo.flags) then
  355. internalerror(2003060703);
  356. }
  357. include(current_procinfo.flags,pi_do_call);
  358. end;
  359. { calling a procedure by address }
  360. procedure tcgppc.a_call_reg(list : taasmoutput;reg: tregister);
  361. var
  362. tmpreg : tregister;
  363. tmpref : treference;
  364. begin
  365. if target_info.system=system_powerpc_macos then
  366. begin
  367. {Generate instruction to load the procedure address from
  368. the transition vector.}
  369. //TODO: Support cross-TOC calls.
  370. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  371. reference_reset(tmpref);
  372. tmpref.offset := 0;
  373. //tmpref.symaddr := refs_full;
  374. tmpref.base:= reg;
  375. list.concat(taicpu.op_reg_ref(A_LWZ,tmpreg,tmpref));
  376. list.concat(taicpu.op_reg(A_MTCTR,tmpreg));
  377. end
  378. else
  379. list.concat(taicpu.op_reg(A_MTCTR,reg));
  380. list.concat(taicpu.op_none(A_BCTRL));
  381. //if target_info.system=system_powerpc_macos then
  382. // //NOP is not needed here.
  383. // list.concat(taicpu.op_none(A_NOP));
  384. include(current_procinfo.flags,pi_do_call);
  385. {
  386. if not(pi_do_call in current_procinfo.flags) then
  387. internalerror(2003060704);
  388. }
  389. //list.concat(tai_comment.create(strpnew('***** a_call_reg')));
  390. end;
  391. {********************** load instructions ********************}
  392. procedure tcgppc.a_load_const_reg(list : taasmoutput; size: TCGSize; a : aint; reg : TRegister);
  393. begin
  394. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  395. internalerror(2002090902);
  396. if (a >= low(smallint)) and
  397. (a <= high(smallint)) then
  398. list.concat(taicpu.op_reg_const(A_LI,reg,smallint(a)))
  399. else if ((a and $ffff) <> 0) then
  400. begin
  401. list.concat(taicpu.op_reg_const(A_LI,reg,smallint(a and $ffff)));
  402. if ((a shr 16) <> 0) or
  403. (smallint(a and $ffff) < 0) then
  404. list.concat(taicpu.op_reg_reg_const(A_ADDIS,reg,reg,
  405. smallint((a shr 16)+ord(smallint(a and $ffff) < 0))))
  406. end
  407. else
  408. list.concat(taicpu.op_reg_const(A_LIS,reg,smallint(a shr 16)));
  409. end;
  410. procedure tcgppc.a_load_reg_ref(list : taasmoutput; fromsize, tosize: TCGSize; reg : tregister;const ref : treference);
  411. const
  412. StoreInstr: Array[OS_8..OS_32,boolean, boolean] of TAsmOp =
  413. { indexed? updating?}
  414. (((A_STB,A_STBU),(A_STBX,A_STBUX)),
  415. ((A_STH,A_STHU),(A_STHX,A_STHUX)),
  416. ((A_STW,A_STWU),(A_STWX,A_STWUX)));
  417. var
  418. op: TAsmOp;
  419. ref2: TReference;
  420. begin
  421. ref2 := ref;
  422. fixref(list,ref2);
  423. if tosize in [OS_S8..OS_S16] then
  424. { storing is the same for signed and unsigned values }
  425. tosize := tcgsize(ord(tosize)-(ord(OS_S8)-ord(OS_8)));
  426. { 64 bit stuff should be handled separately }
  427. if tosize in [OS_64,OS_S64] then
  428. internalerror(200109236);
  429. op := storeinstr[tcgsize2unsigned[tosize],ref2.index<>NR_NO,false];
  430. a_load_store(list,op,reg,ref2);
  431. End;
  432. procedure tcgppc.a_load_ref_reg(list : taasmoutput; fromsize,tosize : tcgsize;const ref: treference;reg : tregister);
  433. const
  434. LoadInstr: Array[OS_8..OS_S32,boolean, boolean] of TAsmOp =
  435. { indexed? updating?}
  436. (((A_LBZ,A_LBZU),(A_LBZX,A_LBZUX)),
  437. ((A_LHZ,A_LHZU),(A_LHZX,A_LHZUX)),
  438. ((A_LWZ,A_LWZU),(A_LWZX,A_LWZUX)),
  439. { 64bit stuff should be handled separately }
  440. ((A_NONE,A_NONE),(A_NONE,A_NONE)),
  441. { 128bit stuff too }
  442. ((A_NONE,A_NONE),(A_NONE,A_NONE)),
  443. { there's no load-byte-with-sign-extend :( }
  444. ((A_LBZ,A_LBZU),(A_LBZX,A_LBZUX)),
  445. ((A_LHA,A_LHAU),(A_LHAX,A_LHAUX)),
  446. ((A_LWZ,A_LWZU),(A_LWZX,A_LWZUX)));
  447. var
  448. op: tasmop;
  449. ref2: treference;
  450. begin
  451. { TODO: optimize/take into consideration fromsize/tosize. Will }
  452. { probably only matter for OS_S8 loads though }
  453. if not(fromsize in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  454. internalerror(2002090902);
  455. ref2 := ref;
  456. fixref(list,ref2);
  457. { the caller is expected to have adjusted the reference already }
  458. { in this case }
  459. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  460. fromsize := tosize;
  461. op := loadinstr[fromsize,ref2.index<>NR_NO,false];
  462. a_load_store(list,op,reg,ref2);
  463. { sign extend shortint if necessary, since there is no }
  464. { load instruction that does that automatically (JM) }
  465. if fromsize = OS_S8 then
  466. list.concat(taicpu.op_reg_reg(A_EXTSB,reg,reg));
  467. end;
  468. procedure tcgppc.a_load_reg_reg(list : taasmoutput;fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  469. var
  470. instr: taicpu;
  471. begin
  472. case tosize of
  473. OS_8:
  474. instr := taicpu.op_reg_reg_const_const_const(A_RLWINM,
  475. reg2,reg1,0,31-8+1,31);
  476. OS_S8:
  477. instr := taicpu.op_reg_reg(A_EXTSB,reg2,reg1);
  478. OS_16:
  479. instr := taicpu.op_reg_reg_const_const_const(A_RLWINM,
  480. reg2,reg1,0,31-16+1,31);
  481. OS_S16:
  482. instr := taicpu.op_reg_reg(A_EXTSH,reg2,reg1);
  483. OS_32,OS_S32:
  484. instr := taicpu.op_reg_reg(A_MR,reg2,reg1);
  485. else internalerror(2002090901);
  486. end;
  487. list.concat(instr);
  488. rg[R_INTREGISTER].add_move_instruction(instr);
  489. end;
  490. procedure tcgppc.a_loadfpu_reg_reg(list: taasmoutput; size: tcgsize; reg1, reg2: tregister);
  491. var
  492. instr: taicpu;
  493. begin
  494. instr := taicpu.op_reg_reg(A_FMR,reg2,reg1);
  495. list.concat(instr);
  496. rg[R_FPUREGISTER].add_move_instruction(instr);
  497. end;
  498. procedure tcgppc.a_loadfpu_ref_reg(list: taasmoutput; size: tcgsize; const ref: treference; reg: tregister);
  499. const
  500. FpuLoadInstr: Array[OS_F32..OS_F64,boolean, boolean] of TAsmOp =
  501. { indexed? updating?}
  502. (((A_LFS,A_LFSU),(A_LFSX,A_LFSUX)),
  503. ((A_LFD,A_LFDU),(A_LFDX,A_LFDUX)));
  504. var
  505. op: tasmop;
  506. ref2: treference;
  507. begin
  508. { several functions call this procedure with OS_32 or OS_64 }
  509. { so this makes life easier (FK) }
  510. case size of
  511. OS_32,OS_F32:
  512. size:=OS_F32;
  513. OS_64,OS_F64,OS_C64:
  514. size:=OS_F64;
  515. else
  516. internalerror(200201121);
  517. end;
  518. ref2 := ref;
  519. fixref(list,ref2);
  520. op := fpuloadinstr[size,ref2.index <> NR_NO,false];
  521. a_load_store(list,op,reg,ref2);
  522. end;
  523. procedure tcgppc.a_loadfpu_reg_ref(list: taasmoutput; size: tcgsize; reg: tregister; const ref: treference);
  524. const
  525. FpuStoreInstr: Array[OS_F32..OS_F64,boolean, boolean] of TAsmOp =
  526. { indexed? updating?}
  527. (((A_STFS,A_STFSU),(A_STFSX,A_STFSUX)),
  528. ((A_STFD,A_STFDU),(A_STFDX,A_STFDUX)));
  529. var
  530. op: tasmop;
  531. ref2: treference;
  532. begin
  533. if not(size in [OS_F32,OS_F64]) then
  534. internalerror(200201122);
  535. ref2 := ref;
  536. fixref(list,ref2);
  537. op := fpustoreinstr[size,ref2.index <> NR_NO,false];
  538. a_load_store(list,op,reg,ref2);
  539. end;
  540. procedure tcgppc.a_op_const_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister);
  541. begin
  542. a_op_const_reg_reg(list,op,size,a,reg,reg);
  543. end;
  544. procedure tcgppc.a_op_reg_reg(list : taasmoutput; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  545. begin
  546. a_op_reg_reg_reg(list,op,size,src,dst,dst);
  547. end;
  548. procedure tcgppc.a_op_const_reg_reg(list: taasmoutput; op: TOpCg;
  549. size: tcgsize; a: aint; src, dst: tregister);
  550. var
  551. l1,l2: longint;
  552. oplo, ophi: tasmop;
  553. scratchreg: tregister;
  554. useReg, gotrlwi: boolean;
  555. procedure do_lo_hi;
  556. begin
  557. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,word(a)));
  558. list.concat(taicpu.op_reg_reg_const(ophi,dst,dst,word(a shr 16)));
  559. end;
  560. begin
  561. if op = OP_SUB then
  562. begin
  563. a_op_const_reg_reg(list,OP_ADD,size,-a,src,dst);
  564. exit;
  565. end;
  566. ophi := TOpCG2AsmOpConstHi[op];
  567. oplo := TOpCG2AsmOpConstLo[op];
  568. gotrlwi := get_rlwi_const(a,l1,l2);
  569. if (op in [OP_AND,OP_OR,OP_XOR]) then
  570. begin
  571. if (a = 0) then
  572. begin
  573. if op = OP_AND then
  574. list.concat(taicpu.op_reg_const(A_LI,dst,0))
  575. else
  576. a_load_reg_reg(list,size,size,src,dst);
  577. exit;
  578. end
  579. else if (a = -1) then
  580. begin
  581. case op of
  582. OP_OR:
  583. list.concat(taicpu.op_reg_const(A_LI,dst,-1));
  584. OP_XOR:
  585. list.concat(taicpu.op_reg_reg(A_NOT,dst,src));
  586. OP_AND:
  587. a_load_reg_reg(list,size,size,src,dst);
  588. end;
  589. exit;
  590. end
  591. else if (aword(a) <= high(word)) and
  592. ((op <> OP_AND) or
  593. not gotrlwi) then
  594. begin
  595. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,word(a)));
  596. exit;
  597. end;
  598. { all basic constant instructions also have a shifted form that }
  599. { works only on the highest 16bits, so if lo(a) is 0, we can }
  600. { use that one }
  601. if (word(a) = 0) and
  602. (not(op = OP_AND) or
  603. not gotrlwi) then
  604. begin
  605. list.concat(taicpu.op_reg_reg_const(ophi,dst,src,word(a shr 16)));
  606. exit;
  607. end;
  608. end
  609. else if (op = OP_ADD) then
  610. if a = 0 then
  611. begin
  612. a_load_reg_reg(list,size,size,src,dst);
  613. exit
  614. end
  615. else if (a >= low(smallint)) and
  616. (a <= high(smallint)) then
  617. begin
  618. list.concat(taicpu.op_reg_reg_const(A_ADDI,dst,src,smallint(a)));
  619. exit;
  620. end;
  621. { otherwise, the instructions we can generate depend on the }
  622. { operation }
  623. useReg := false;
  624. case op of
  625. OP_DIV,OP_IDIV:
  626. if (a = 0) then
  627. internalerror(200208103)
  628. else if (a = 1) then
  629. begin
  630. a_load_reg_reg(list,OS_INT,OS_INT,src,dst);
  631. exit
  632. end
  633. else if ispowerof2(a,l1) then
  634. begin
  635. case op of
  636. OP_DIV:
  637. list.concat(taicpu.op_reg_reg_const(A_SRWI,dst,src,l1));
  638. OP_IDIV:
  639. begin
  640. list.concat(taicpu.op_reg_reg_const(A_SRAWI,dst,src,l1));
  641. list.concat(taicpu.op_reg_reg(A_ADDZE,dst,dst));
  642. end;
  643. end;
  644. exit;
  645. end
  646. else
  647. usereg := true;
  648. OP_IMUL, OP_MUL:
  649. if (a = 0) then
  650. begin
  651. list.concat(taicpu.op_reg_const(A_LI,dst,0));
  652. exit
  653. end
  654. else if (a = 1) then
  655. begin
  656. a_load_reg_reg(list,OS_INT,OS_INT,src,dst);
  657. exit
  658. end
  659. else if ispowerof2(a,l1) then
  660. list.concat(taicpu.op_reg_reg_const(A_SLWI,dst,src,l1))
  661. else if (longint(a) >= low(smallint)) and
  662. (longint(a) <= high(smallint)) then
  663. list.concat(taicpu.op_reg_reg_const(A_MULLI,dst,src,smallint(a)))
  664. else
  665. usereg := true;
  666. OP_ADD:
  667. begin
  668. list.concat(taicpu.op_reg_reg_const(oplo,dst,src,smallint(a)));
  669. list.concat(taicpu.op_reg_reg_const(ophi,dst,dst,
  670. smallint((a shr 16) + ord(smallint(a) < 0))));
  671. end;
  672. OP_OR:
  673. { try to use rlwimi }
  674. if gotrlwi and
  675. (src = dst) then
  676. begin
  677. scratchreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  678. list.concat(taicpu.op_reg_const(A_LI,scratchreg,-1));
  679. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,dst,
  680. scratchreg,0,l1,l2));
  681. end
  682. else
  683. do_lo_hi;
  684. OP_AND:
  685. { try to use rlwinm }
  686. if gotrlwi then
  687. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,dst,
  688. src,0,l1,l2))
  689. else
  690. useReg := true;
  691. OP_XOR:
  692. do_lo_hi;
  693. OP_SHL,OP_SHR,OP_SAR:
  694. begin
  695. if (a and 31) <> 0 Then
  696. list.concat(taicpu.op_reg_reg_const(
  697. TOpCG2AsmOpConstLo[Op],dst,src,a and 31))
  698. else
  699. a_load_reg_reg(list,size,size,src,dst);
  700. if (a shr 5) <> 0 then
  701. internalError(68991);
  702. end
  703. else
  704. internalerror(200109091);
  705. end;
  706. { if all else failed, load the constant in a register and then }
  707. { perform the operation }
  708. if useReg then
  709. begin
  710. scratchreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  711. a_load_const_reg(list,OS_32,a,scratchreg);
  712. a_op_reg_reg_reg(list,op,OS_32,scratchreg,src,dst);
  713. end;
  714. end;
  715. procedure tcgppc.a_op_reg_reg_reg(list: taasmoutput; op: TOpCg;
  716. size: tcgsize; src1, src2, dst: tregister);
  717. const
  718. op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
  719. (A_NONE,A_ADD,A_AND,A_DIVWU,A_DIVW,A_MULLW,A_MULLW,A_NEG,A_NOT,A_OR,
  720. A_SRAW,A_SLW,A_SRW,A_SUB,A_XOR);
  721. begin
  722. case op of
  723. OP_NEG,OP_NOT:
  724. begin
  725. list.concat(taicpu.op_reg_reg(op_reg_reg_opcg2asmop[op],dst,src1));
  726. if (op = OP_NOT) and
  727. not(size in [OS_32,OS_S32]) then
  728. { zero/sign extend result again }
  729. a_load_reg_reg(list,OS_32,size,dst,dst);
  730. end;
  731. else
  732. list.concat(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1));
  733. end;
  734. end;
  735. {*************** compare instructructions ****************}
  736. procedure tcgppc.a_cmp_const_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  737. l : tasmlabel);
  738. var
  739. scratch_register: TRegister;
  740. signed: boolean;
  741. begin
  742. signed := cmp_op in [OC_GT,OC_LT,OC_GTE,OC_LTE];
  743. { in the following case, we generate more efficient code when }
  744. { signed is true }
  745. if (cmp_op in [OC_EQ,OC_NE]) and
  746. (aword(a) > $ffff) then
  747. signed := true;
  748. if signed then
  749. if (a >= low(smallint)) and (a <= high(smallint)) Then
  750. list.concat(taicpu.op_reg_reg_const(A_CMPWI,NR_CR0,reg,a))
  751. else
  752. begin
  753. scratch_register := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  754. a_load_const_reg(list,OS_32,a,scratch_register);
  755. list.concat(taicpu.op_reg_reg_reg(A_CMPW,NR_CR0,reg,scratch_register));
  756. end
  757. else
  758. if (aword(a) <= $ffff) then
  759. list.concat(taicpu.op_reg_reg_const(A_CMPLWI,NR_CR0,reg,aword(a)))
  760. else
  761. begin
  762. scratch_register := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  763. a_load_const_reg(list,OS_32,a,scratch_register);
  764. list.concat(taicpu.op_reg_reg_reg(A_CMPLW,NR_CR0,reg,scratch_register));
  765. end;
  766. a_jmp(list,A_BC,TOpCmp2AsmCond[cmp_op],0,l);
  767. end;
  768. procedure tcgppc.a_cmp_reg_reg_label(list : taasmoutput;size : tcgsize;cmp_op : topcmp;
  769. reg1,reg2 : tregister;l : tasmlabel);
  770. var
  771. op: tasmop;
  772. begin
  773. if cmp_op in [OC_GT,OC_LT,OC_GTE,OC_LTE] then
  774. op := A_CMPW
  775. else
  776. op := A_CMPLW;
  777. list.concat(taicpu.op_reg_reg_reg(op,NR_CR0,reg2,reg1));
  778. a_jmp(list,A_BC,TOpCmp2AsmCond[cmp_op],0,l);
  779. end;
  780. procedure tcgppc.a_jmp_cond(list : taasmoutput;cond : TOpCmp;l: tasmlabel);
  781. begin
  782. a_jmp(list,A_BC,TOpCmp2AsmCond[cond],0,l);
  783. end;
  784. procedure tcgppc.a_jmp_name(list : taasmoutput;const s : string);
  785. var
  786. p : taicpu;
  787. begin
  788. if (target_info.system = system_powerpc_darwin) then
  789. p := taicpu.op_sym(A_B,get_darwin_call_stub(s))
  790. else
  791. p := taicpu.op_sym(A_B,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION));
  792. p.is_jmp := true;
  793. list.concat(p)
  794. end;
  795. procedure tcgppc.a_jmp_always(list : taasmoutput;l: tasmlabel);
  796. begin
  797. a_jmp(list,A_B,C_None,0,l);
  798. end;
  799. procedure tcgppc.a_jmp_flags(list : taasmoutput;const f : TResFlags;l: tasmlabel);
  800. var
  801. c: tasmcond;
  802. begin
  803. c := flags_to_cond(f);
  804. a_jmp(list,A_BC,c.cond,c.cr-RS_CR0,l);
  805. end;
  806. procedure tcgppc.g_flags2reg(list: taasmoutput; size: TCgSize; const f: TResFlags; reg: TRegister);
  807. var
  808. testbit: byte;
  809. bitvalue: boolean;
  810. begin
  811. { get the bit to extract from the conditional register + its }
  812. { requested value (0 or 1) }
  813. testbit := ((f.cr-RS_CR0) * 4);
  814. case f.flag of
  815. F_EQ,F_NE:
  816. begin
  817. inc(testbit,2);
  818. bitvalue := f.flag = F_EQ;
  819. end;
  820. F_LT,F_GE:
  821. begin
  822. bitvalue := f.flag = F_LT;
  823. end;
  824. F_GT,F_LE:
  825. begin
  826. inc(testbit);
  827. bitvalue := f.flag = F_GT;
  828. end;
  829. else
  830. internalerror(200112261);
  831. end;
  832. { load the conditional register in the destination reg }
  833. list.concat(taicpu.op_reg(A_MFCR,reg));
  834. { we will move the bit that has to be tested to bit 0 by rotating }
  835. { left }
  836. testbit := (testbit + 1) and 31;
  837. { extract bit }
  838. list.concat(taicpu.op_reg_reg_const_const_const(
  839. A_RLWINM,reg,reg,testbit,31,31));
  840. { if we need the inverse, xor with 1 }
  841. if not bitvalue then
  842. list.concat(taicpu.op_reg_reg_const(A_XORI,reg,reg,1));
  843. end;
  844. (*
  845. procedure tcgppc.g_cond2reg(list: taasmoutput; const f: TAsmCond; reg: TRegister);
  846. var
  847. testbit: byte;
  848. bitvalue: boolean;
  849. begin
  850. { get the bit to extract from the conditional register + its }
  851. { requested value (0 or 1) }
  852. case f.simple of
  853. false:
  854. begin
  855. { we don't generate this in the compiler }
  856. internalerror(200109062);
  857. end;
  858. true:
  859. case f.cond of
  860. C_None:
  861. internalerror(200109063);
  862. C_LT..C_NU:
  863. begin
  864. testbit := (ord(f.cr) - ord(R_CR0))*4;
  865. inc(testbit,AsmCondFlag2BI[f.cond]);
  866. bitvalue := AsmCondFlagTF[f.cond];
  867. end;
  868. C_T,C_F,C_DNZT,C_DNZF,C_DZT,C_DZF:
  869. begin
  870. testbit := f.crbit
  871. bitvalue := AsmCondFlagTF[f.cond];
  872. end;
  873. else
  874. internalerror(200109064);
  875. end;
  876. end;
  877. { load the conditional register in the destination reg }
  878. list.concat(taicpu.op_reg_reg(A_MFCR,reg));
  879. { we will move the bit that has to be tested to bit 31 -> rotate }
  880. { left by bitpos+1 (remember, this is big-endian!) }
  881. if bitpos <> 31 then
  882. inc(bitpos)
  883. else
  884. bitpos := 0;
  885. { extract bit }
  886. list.concat(taicpu.op_reg_reg_const_const_const(
  887. A_RLWINM,reg,reg,bitpos,31,31));
  888. { if we need the inverse, xor with 1 }
  889. if not bitvalue then
  890. list.concat(taicpu.op_reg_reg_const(A_XORI,reg,reg,1));
  891. end;
  892. *)
  893. { *********** entry/exit code and address loading ************ }
  894. procedure tcgppc.g_save_standard_registers(list:Taasmoutput);
  895. begin
  896. { this work is done in g_proc_entry }
  897. end;
  898. procedure tcgppc.g_restore_standard_registers(list:Taasmoutput);
  899. begin
  900. { this work is done in g_proc_exit }
  901. end;
  902. procedure tcgppc.g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);
  903. { generated the entry code of a procedure/function. Note: localsize is the }
  904. { sum of the size necessary for local variables and the maximum possible }
  905. { combined size of ALL the parameters of a procedure called by the current }
  906. { one. }
  907. { This procedure may be called before, as well as after g_return_from_proc }
  908. { is called. NOTE registers are not to be allocated through the register }
  909. { allocator here, because the register colouring has already occured !! }
  910. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  911. href : treference;
  912. usesfpr,usesgpr,gotgot : boolean;
  913. regcounter2, firstfpureg: Tsuperregister;
  914. cond : tasmcond;
  915. instr : taicpu;
  916. begin
  917. { CR and LR only have to be saved in case they are modified by the current }
  918. { procedure, but currently this isn't checked, so save them always }
  919. { following is the entry code as described in "Altivec Programming }
  920. { Interface Manual", bar the saving of AltiVec registers }
  921. a_reg_alloc(list,NR_STACK_POINTER_REG);
  922. a_reg_alloc(list,NR_R0);
  923. usesfpr:=false;
  924. if not (po_assembler in current_procinfo.procdef.procoptions) then
  925. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  926. case target_info.abi of
  927. abi_powerpc_aix:
  928. firstfpureg := RS_F14;
  929. abi_powerpc_sysv:
  930. firstfpureg := RS_F14;
  931. else
  932. internalerror(2003122903);
  933. end;
  934. for regcounter:=firstfpureg to RS_F31 do
  935. begin
  936. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  937. begin
  938. usesfpr:= true;
  939. firstregfpu:=regcounter;
  940. break;
  941. end;
  942. end;
  943. usesgpr:=false;
  944. if not (po_assembler in current_procinfo.procdef.procoptions) then
  945. for regcounter2:=RS_R13 to RS_R31 do
  946. begin
  947. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  948. begin
  949. usesgpr:=true;
  950. firstreggpr:=regcounter2;
  951. break;
  952. end;
  953. end;
  954. { save link register? }
  955. if not (po_assembler in current_procinfo.procdef.procoptions) then
  956. if (pi_do_call in current_procinfo.flags) then
  957. begin
  958. { save return address... }
  959. list.concat(taicpu.op_reg(A_MFLR,NR_R0));
  960. { ... in caller's frame }
  961. case target_info.abi of
  962. abi_powerpc_aix:
  963. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_AIX);
  964. abi_powerpc_sysv:
  965. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_SYSV);
  966. end;
  967. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  968. a_reg_dealloc(list,NR_R0);
  969. end;
  970. { save the CR if necessary in callers frame. }
  971. if not (po_assembler in current_procinfo.procdef.procoptions) then
  972. if target_info.abi = abi_powerpc_aix then
  973. if false then { Not needed at the moment. }
  974. begin
  975. a_reg_alloc(list,NR_R0);
  976. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_CR));
  977. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  978. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  979. a_reg_dealloc(list,NR_R0);
  980. end;
  981. { !!! always allocate space for all registers for now !!! }
  982. if not (po_assembler in current_procinfo.procdef.procoptions) then
  983. { if usesfpr or usesgpr then }
  984. begin
  985. a_reg_alloc(list,NR_R12);
  986. { save end of fpr save area }
  987. list.concat(taicpu.op_reg_reg(A_MR,NR_R12,NR_STACK_POINTER_REG));
  988. end;
  989. if (not nostackframe) and
  990. (localsize <> 0) then
  991. begin
  992. if (localsize <= high(smallint)) then
  993. begin
  994. reference_reset_base(href,NR_STACK_POINTER_REG,-localsize);
  995. a_load_store(list,A_STWU,NR_STACK_POINTER_REG,href);
  996. end
  997. else
  998. begin
  999. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1000. { can't use getregisterint here, the register colouring }
  1001. { is already done when we get here }
  1002. href.index := NR_R11;
  1003. a_reg_alloc(list,href.index);
  1004. a_load_const_reg(list,OS_S32,-localsize,href.index);
  1005. a_load_store(list,A_STWUX,NR_STACK_POINTER_REG,href);
  1006. a_reg_dealloc(list,href.index);
  1007. end;
  1008. end;
  1009. { no GOT pointer loaded yet }
  1010. gotgot:=false;
  1011. if usesfpr then
  1012. begin
  1013. { save floating-point registers
  1014. if (cs_create_pic in aktmoduleswitches) and not(usesgpr) then
  1015. begin
  1016. a_call_name(objectlibrary.newasmsymbol('_savefpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14)+'_g',AB_EXTERNAL,AT_FUNCTION));
  1017. gotgot:=true;
  1018. end
  1019. else
  1020. a_call_name(objectlibrary.newasmsymbol('_savefpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14),AB_EXTERNAL,AT_FUNCTION));
  1021. }
  1022. reference_reset_base(href,NR_R12,-8);
  1023. for regcounter:=firstregfpu to RS_F31 do
  1024. begin
  1025. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1026. begin
  1027. a_loadfpu_reg_ref(list,OS_F64,newreg(R_FPUREGISTER,regcounter,R_SUBNONE),href);
  1028. dec(href.offset,8);
  1029. end;
  1030. end;
  1031. { compute end of gpr save area }
  1032. a_op_const_reg(list,OP_ADD,OS_ADDR,href.offset+8,NR_R12);
  1033. end;
  1034. { save gprs and fetch GOT pointer }
  1035. if usesgpr then
  1036. begin
  1037. {
  1038. if cs_create_pic in aktmoduleswitches then
  1039. begin
  1040. a_call_name(objectlibrary.newasmsymbol('_savegpr_'+tostr(ord(firstreggpr)-ord(R_14)+14)+'_g',AB_EXTERNAL,AT_FUNCTION));
  1041. gotgot:=true;
  1042. end
  1043. else
  1044. a_call_name(objectlibrary.newasmsymbol('_savegpr_'+tostr(ord(firstreggpr)-ord(R_14)+14),AB_EXTERNAL,AT_FUNCTION))
  1045. }
  1046. reference_reset_base(href,NR_R12,-4);
  1047. for regcounter2:=RS_R13 to RS_R31 do
  1048. begin
  1049. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1050. begin
  1051. usesgpr:=true;
  1052. a_load_reg_ref(list,OS_INT,OS_INT,newreg(R_INTREGISTER,regcounter2,R_SUBNONE),href);
  1053. dec(href.offset,4);
  1054. end;
  1055. end;
  1056. {
  1057. r.enum:=R_INTREGISTER;
  1058. r.:=;
  1059. reference_reset_base(href,NR_R12,-((NR_R31-firstreggpr) shr 8+1)*4);
  1060. list.concat(taicpu.op_reg_ref(A_STMW,firstreggpr,href));
  1061. }
  1062. end;
  1063. { see "!!! always allocate space for all registers for now !!!" above }
  1064. { done in ncgutil because it may only be released after the parameters }
  1065. { have been moved to their final resting place }
  1066. { if usesfpr or usesgpr then }
  1067. { a_reg_dealloc(list,NR_R12); }
  1068. { if we didn't get the GOT pointer till now, we've to calculate it now }
  1069. if not(gotgot) and (pi_needs_got in current_procinfo.flags) then
  1070. case target_info.system of
  1071. system_powerpc_darwin:
  1072. begin
  1073. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_LR));
  1074. fillchar(cond,sizeof(cond),0);
  1075. cond.simple:=false;
  1076. cond.bo:=20;
  1077. cond.bi:=31;
  1078. instr:=taicpu.op_sym(A_BCL,current_procinfo.gotlabel);
  1079. instr.setcondition(cond);
  1080. list.concat(instr);
  1081. a_label(list,current_procinfo.gotlabel);
  1082. list.concat(taicpu.op_reg_reg(A_MFSPR,current_procinfo.got,NR_LR));
  1083. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_LR,NR_R0));
  1084. end;
  1085. else
  1086. begin
  1087. a_reg_alloc(list,NR_R31);
  1088. { place GOT ptr in r31 }
  1089. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R31,NR_LR));
  1090. end;
  1091. end;
  1092. { save the CR if necessary ( !!! always done currently ) }
  1093. { still need to find out where this has to be done for SystemV
  1094. a_reg_alloc(list,R_0);
  1095. list.concat(taicpu.op_reg_reg(A_MFSPR,R_0,R_CR);
  1096. list.concat(taicpu.op_reg_ref(A_STW,scratch_register,
  1097. new_reference(STACK_POINTER_REG,LA_CR)));
  1098. a_reg_dealloc(list,R_0); }
  1099. { now comes the AltiVec context save, not yet implemented !!! }
  1100. end;
  1101. procedure tcgppc.g_proc_exit(list : taasmoutput;parasize : longint;nostackframe:boolean);
  1102. { This procedure may be called before, as well as after g_stackframe_entry }
  1103. { is called. NOTE registers are not to be allocated through the register }
  1104. { allocator here, because the register colouring has already occured !! }
  1105. var
  1106. regcounter,firstregfpu,firstreggpr: TsuperRegister;
  1107. href : treference;
  1108. usesfpr,usesgpr,genret : boolean;
  1109. regcounter2, firstfpureg:Tsuperregister;
  1110. localsize: aint;
  1111. begin
  1112. { AltiVec context restore, not yet implemented !!! }
  1113. usesfpr:=false;
  1114. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1115. begin
  1116. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1117. case target_info.abi of
  1118. abi_powerpc_aix:
  1119. firstfpureg := RS_F14;
  1120. abi_powerpc_sysv:
  1121. firstfpureg := RS_F14;
  1122. else
  1123. internalerror(2003122903);
  1124. end;
  1125. for regcounter:=firstfpureg to RS_F31 do
  1126. begin
  1127. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1128. begin
  1129. usesfpr:=true;
  1130. firstregfpu:=regcounter;
  1131. break;
  1132. end;
  1133. end;
  1134. end;
  1135. usesgpr:=false;
  1136. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1137. for regcounter2:=RS_R13 to RS_R31 do
  1138. begin
  1139. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1140. begin
  1141. usesgpr:=true;
  1142. firstreggpr:=regcounter2;
  1143. break;
  1144. end;
  1145. end;
  1146. localsize:= tppcprocinfo(current_procinfo).calc_stackframe_size;
  1147. { no return (blr) generated yet }
  1148. genret:=true;
  1149. if usesgpr or usesfpr then
  1150. begin
  1151. { address of gpr save area to r11 }
  1152. { (register allocator is no longer valid at this time and an add of 0 }
  1153. { is translated into a move, which is then registered with the register }
  1154. { allocator, causing a crash }
  1155. if (localsize <> 0) then
  1156. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,localsize,NR_STACK_POINTER_REG,NR_R12)
  1157. else
  1158. list.concat(taicpu.op_reg_reg(A_MR,NR_R12,NR_STACK_POINTER_REG));
  1159. if usesfpr then
  1160. begin
  1161. reference_reset_base(href,NR_R12,-8);
  1162. for regcounter := firstregfpu to RS_F31 do
  1163. begin
  1164. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1165. begin
  1166. a_loadfpu_ref_reg(list,OS_F64,href,newreg(R_FPUREGISTER,regcounter,R_SUBNONE));
  1167. dec(href.offset,8);
  1168. end;
  1169. end;
  1170. inc(href.offset,4);
  1171. end
  1172. else
  1173. reference_reset_base(href,NR_R12,-4);
  1174. for regcounter2:=RS_R13 to RS_R31 do
  1175. begin
  1176. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1177. begin
  1178. usesgpr:=true;
  1179. a_load_ref_reg(list,OS_INT,OS_INT,href,newreg(R_INTREGISTER,regcounter2,R_SUBNONE));
  1180. dec(href.offset,4);
  1181. end;
  1182. end;
  1183. (*
  1184. reference_reset_base(href,r2,-((NR_R31-ord(firstreggpr)) shr 8+1)*4);
  1185. list.concat(taicpu.op_reg_ref(A_LMW,firstreggpr,href));
  1186. *)
  1187. end;
  1188. (*
  1189. { restore fprs and return }
  1190. if usesfpr then
  1191. begin
  1192. { address of fpr save area to r11 }
  1193. r:=NR_R12;
  1194. list.concat(taicpu.op_reg_reg_const(A_ADDI,r,r,(ord(R_F31)-ord(firstregfpu.enum)+1)*8));
  1195. {
  1196. if (pi_do_call in current_procinfo.flags) then
  1197. a_call_name(objectlibrary.newasmsymbol('_restfpr_'+tostr(ord(firstregfpu)-ord(R_F14)+14)+
  1198. '_x',AB_EXTERNAL,AT_FUNCTION))
  1199. else
  1200. { leaf node => lr haven't to be restored }
  1201. a_call_name('_restfpr_'+tostr(ord(firstregfpu.enum)-ord(R_F14)+14)+
  1202. '_l');
  1203. genret:=false;
  1204. }
  1205. end;
  1206. *)
  1207. { if we didn't generate the return code, we've to do it now }
  1208. if genret then
  1209. begin
  1210. { adjust r1 }
  1211. { (register allocator is no longer valid at this time and an add of 0 }
  1212. { is translated into a move, which is then registered with the register }
  1213. { allocator, causing a crash }
  1214. if (not nostackframe) and
  1215. (localsize <> 0) then
  1216. a_op_const_reg(list,OP_ADD,OS_ADDR,localsize,NR_R1);
  1217. { load link register? }
  1218. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1219. begin
  1220. if (pi_do_call in current_procinfo.flags) then
  1221. begin
  1222. case target_info.abi of
  1223. abi_powerpc_aix:
  1224. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_AIX);
  1225. abi_powerpc_sysv:
  1226. reference_reset_base(href,NR_STACK_POINTER_REG,LA_LR_SYSV);
  1227. end;
  1228. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1229. list.concat(taicpu.op_reg(A_MTLR,NR_R0));
  1230. end;
  1231. { restore the CR if necessary from callers frame}
  1232. if target_info.abi = abi_powerpc_aix then
  1233. if false then { Not needed at the moment. }
  1234. begin
  1235. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1236. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1237. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_CR));
  1238. a_reg_dealloc(list,NR_R0);
  1239. end;
  1240. end;
  1241. list.concat(taicpu.op_none(A_BLR));
  1242. end;
  1243. end;
  1244. function tcgppc.save_regs(list : taasmoutput):longint;
  1245. {Generates code which saves used non-volatile registers in
  1246. the save area right below the address the stackpointer point to.
  1247. Returns the actual used save area size.}
  1248. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  1249. usesfpr,usesgpr: boolean;
  1250. href : treference;
  1251. offset: aint;
  1252. regcounter2, firstfpureg: Tsuperregister;
  1253. begin
  1254. usesfpr:=false;
  1255. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1256. begin
  1257. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1258. case target_info.abi of
  1259. abi_powerpc_aix:
  1260. firstfpureg := RS_F14;
  1261. abi_powerpc_sysv:
  1262. firstfpureg := RS_F9;
  1263. else
  1264. internalerror(2003122903);
  1265. end;
  1266. for regcounter:=firstfpureg to RS_F31 do
  1267. begin
  1268. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1269. begin
  1270. usesfpr:=true;
  1271. firstregfpu:=regcounter;
  1272. break;
  1273. end;
  1274. end;
  1275. end;
  1276. usesgpr:=false;
  1277. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1278. for regcounter2:=RS_R13 to RS_R31 do
  1279. begin
  1280. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1281. begin
  1282. usesgpr:=true;
  1283. firstreggpr:=regcounter2;
  1284. break;
  1285. end;
  1286. end;
  1287. offset:= 0;
  1288. { save floating-point registers }
  1289. if usesfpr then
  1290. for regcounter := firstregfpu to RS_F31 do
  1291. begin
  1292. offset:= offset - 8;
  1293. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1294. list.concat(taicpu.op_reg_ref(A_STFD, tregister(regcounter), href));
  1295. end;
  1296. (* Optimiztion in the future: a_call_name(list,'_savefXX'); *)
  1297. { save gprs in gpr save area }
  1298. if usesgpr then
  1299. if firstreggpr < RS_R30 then
  1300. begin
  1301. offset:= offset - 4 * (RS_R31 - firstreggpr + 1);
  1302. reference_reset_base(href,NR_STACK_POINTER_REG,offset);
  1303. list.concat(taicpu.op_reg_ref(A_STMW,tregister(firstreggpr),href));
  1304. {STMW stores multiple registers}
  1305. end
  1306. else
  1307. begin
  1308. for regcounter := firstreggpr to RS_R31 do
  1309. begin
  1310. offset:= offset - 4;
  1311. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1312. list.concat(taicpu.op_reg_ref(A_STW, newreg(R_INTREGISTER,regcounter,R_SUBWHOLE), href));
  1313. end;
  1314. end;
  1315. { now comes the AltiVec context save, not yet implemented !!! }
  1316. save_regs:= -offset;
  1317. end;
  1318. procedure tcgppc.restore_regs(list : taasmoutput);
  1319. {Generates code which restores used non-volatile registers from
  1320. the save area right below the address the stackpointer point to.}
  1321. var regcounter,firstregfpu,firstreggpr: TSuperRegister;
  1322. usesfpr,usesgpr: boolean;
  1323. href : treference;
  1324. offset: integer;
  1325. regcounter2, firstfpureg: Tsuperregister;
  1326. begin
  1327. usesfpr:=false;
  1328. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1329. begin
  1330. { FIXME: has to be R_F14 instad of R_F8 for SYSV-64bit }
  1331. case target_info.abi of
  1332. abi_powerpc_aix:
  1333. firstfpureg := RS_F14;
  1334. abi_powerpc_sysv:
  1335. firstfpureg := RS_F9;
  1336. else
  1337. internalerror(2003122903);
  1338. end;
  1339. for regcounter:=firstfpureg to RS_F31 do
  1340. begin
  1341. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1342. begin
  1343. usesfpr:=true;
  1344. firstregfpu:=regcounter;
  1345. break;
  1346. end;
  1347. end;
  1348. end;
  1349. usesgpr:=false;
  1350. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1351. for regcounter2:=RS_R13 to RS_R31 do
  1352. begin
  1353. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1354. begin
  1355. usesgpr:=true;
  1356. firstreggpr:=regcounter2;
  1357. break;
  1358. end;
  1359. end;
  1360. offset:= 0;
  1361. { restore fp registers }
  1362. if usesfpr then
  1363. for regcounter := firstregfpu to RS_F31 do
  1364. begin
  1365. offset:= offset - 8;
  1366. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1367. list.concat(taicpu.op_reg_ref(A_LFD, newreg(R_FPUREGISTER,regcounter,R_SUBWHOLE), href));
  1368. end;
  1369. (* Optimiztion in the future: a_call_name(list,'_restfXX'); *)
  1370. { restore gprs }
  1371. if usesgpr then
  1372. if firstreggpr < RS_R30 then
  1373. begin
  1374. offset:= offset - 4 * (RS_R31 - firstreggpr + 1);
  1375. reference_reset_base(href,NR_STACK_POINTER_REG,offset); //-220
  1376. list.concat(taicpu.op_reg_ref(A_LMW,tregister(firstreggpr),href));
  1377. {LMW loads multiple registers}
  1378. end
  1379. else
  1380. begin
  1381. for regcounter := firstreggpr to RS_R31 do
  1382. begin
  1383. offset:= offset - 4;
  1384. reference_reset_base(href, NR_STACK_POINTER_REG, offset);
  1385. list.concat(taicpu.op_reg_ref(A_LWZ, newreg(R_INTREGISTER,regcounter,R_SUBWHOLE), href));
  1386. end;
  1387. end;
  1388. { now comes the AltiVec context restore, not yet implemented !!! }
  1389. end;
  1390. procedure tcgppc.g_stackframe_entry_mac(list : taasmoutput;localsize : longint);
  1391. (* NOT IN USE *)
  1392. { generated the entry code of a procedure/function. Note: localsize is the }
  1393. { sum of the size necessary for local variables and the maximum possible }
  1394. { combined size of ALL the parameters of a procedure called by the current }
  1395. { one }
  1396. const
  1397. macosLinkageAreaSize = 24;
  1398. var
  1399. href : treference;
  1400. registerSaveAreaSize : longint;
  1401. begin
  1402. if (localsize mod 8) <> 0 then
  1403. internalerror(58991);
  1404. { CR and LR only have to be saved in case they are modified by the current }
  1405. { procedure, but currently this isn't checked, so save them always }
  1406. { following is the entry code as described in "Altivec Programming }
  1407. { Interface Manual", bar the saving of AltiVec registers }
  1408. a_reg_alloc(list,NR_STACK_POINTER_REG);
  1409. a_reg_alloc(list,NR_R0);
  1410. { save return address in callers frame}
  1411. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_LR));
  1412. { ... in caller's frame }
  1413. reference_reset_base(href,NR_STACK_POINTER_REG,8);
  1414. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  1415. a_reg_dealloc(list,NR_R0);
  1416. { save non-volatile registers in callers frame}
  1417. registerSaveAreaSize:= save_regs(list);
  1418. { save the CR if necessary in callers frame ( !!! always done currently ) }
  1419. a_reg_alloc(list,NR_R0);
  1420. list.concat(taicpu.op_reg_reg(A_MFSPR,NR_R0,NR_CR));
  1421. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1422. list.concat(taicpu.op_reg_ref(A_STW,NR_R0,href));
  1423. a_reg_dealloc(list,NR_R0);
  1424. (*
  1425. { save pointer to incoming arguments }
  1426. list.concat(taicpu.op_reg_reg_const(A_ORI,R_31,STACK_POINTER_REG,0));
  1427. *)
  1428. (*
  1429. a_reg_alloc(list,R_12);
  1430. { 0 or 8 based on SP alignment }
  1431. list.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,
  1432. R_12,STACK_POINTER_REG,0,28,28));
  1433. { add in stack length }
  1434. list.concat(taicpu.op_reg_reg_const(A_SUBFIC,R_12,R_12,
  1435. -localsize));
  1436. { establish new alignment }
  1437. list.concat(taicpu.op_reg_reg_reg(A_STWUX,STACK_POINTER_REG,STACK_POINTER_REG,R_12));
  1438. a_reg_dealloc(list,R_12);
  1439. *)
  1440. { allocate stack frame }
  1441. localsize:= align(localsize + macosLinkageAreaSize + registerSaveAreaSize, 16);
  1442. inc(localsize,tg.lasttemp);
  1443. localsize:=align(localsize,16);
  1444. //tppcprocinfo(current_procinfo).localsize:=localsize;
  1445. if (localsize <> 0) then
  1446. begin
  1447. if (localsize <= high(smallint)) then
  1448. begin
  1449. reference_reset_base(href,NR_STACK_POINTER_REG,-localsize);
  1450. a_load_store(list,A_STWU,NR_STACK_POINTER_REG,href);
  1451. end
  1452. else
  1453. begin
  1454. reference_reset_base(href,NR_STACK_POINTER_REG,0);
  1455. href.index := NR_R11;
  1456. a_reg_alloc(list,href.index);
  1457. a_load_const_reg(list,OS_S32,-localsize,href.index);
  1458. a_load_store(list,A_STWUX,NR_STACK_POINTER_REG,href);
  1459. a_reg_dealloc(list,href.index);
  1460. end;
  1461. end;
  1462. end;
  1463. procedure tcgppc.g_return_from_proc_mac(list : taasmoutput;parasize : aint);
  1464. (* NOT IN USE *)
  1465. var
  1466. href : treference;
  1467. begin
  1468. a_reg_alloc(list,NR_R0);
  1469. { restore stack pointer }
  1470. reference_reset_base(href,NR_STACK_POINTER_REG,LA_SP);
  1471. list.concat(taicpu.op_reg_ref(A_LWZ,NR_STACK_POINTER_REG,href));
  1472. (*
  1473. list.concat(taicpu.op_reg_reg_const(A_ORI,NR_STACK_POINTER_REG,R_31,0));
  1474. *)
  1475. { restore the CR if necessary from callers frame
  1476. ( !!! always done currently ) }
  1477. reference_reset_base(href,NR_STACK_POINTER_REG,LA_CR_AIX);
  1478. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1479. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_CR));
  1480. a_reg_dealloc(list,NR_R0);
  1481. (*
  1482. { restore return address from callers frame }
  1483. reference_reset_base(href,STACK_POINTER_REG,8);
  1484. list.concat(taicpu.op_reg_ref(A_LWZ,R_0,href));
  1485. *)
  1486. { restore non-volatile registers from callers frame }
  1487. restore_regs(list);
  1488. (*
  1489. { return to caller }
  1490. list.concat(taicpu.op_reg_reg(A_MTSPR,R_0,R_LR));
  1491. list.concat(taicpu.op_none(A_BLR));
  1492. *)
  1493. { restore return address from callers frame }
  1494. reference_reset_base(href,NR_STACK_POINTER_REG,8);
  1495. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R0,href));
  1496. { return to caller }
  1497. list.concat(taicpu.op_reg_reg(A_MTSPR,NR_R0,NR_LR));
  1498. list.concat(taicpu.op_none(A_BLR));
  1499. end;
  1500. procedure tcgppc.a_loadaddr_ref_reg(list : taasmoutput;const ref : treference;r : tregister);
  1501. var
  1502. ref2, tmpref: treference;
  1503. begin
  1504. ref2 := ref;
  1505. fixref(list,ref2);
  1506. if assigned(ref2.symbol) then
  1507. begin
  1508. if target_info.system = system_powerpc_macos then
  1509. begin
  1510. if macos_direct_globals then
  1511. begin
  1512. reference_reset(tmpref);
  1513. tmpref.offset := ref2.offset;
  1514. tmpref.symbol := ref2.symbol;
  1515. tmpref.base := NR_NO;
  1516. list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,NR_RTOC,tmpref));
  1517. end
  1518. else
  1519. begin
  1520. reference_reset(tmpref);
  1521. tmpref.symbol := ref2.symbol;
  1522. tmpref.offset := 0;
  1523. tmpref.base := NR_RTOC;
  1524. list.concat(taicpu.op_reg_ref(A_LWZ,r,tmpref));
  1525. if ref2.offset <> 0 then
  1526. begin
  1527. reference_reset(tmpref);
  1528. tmpref.offset := ref2.offset;
  1529. tmpref.base:= r;
  1530. list.concat(taicpu.op_reg_ref(A_LA,r,tmpref));
  1531. end;
  1532. end;
  1533. if ref2.base <> NR_NO then
  1534. list.concat(taicpu.op_reg_reg_reg(A_ADD,r,r,ref2.base));
  1535. //list.concat(tai_comment.create(strpnew('*** a_loadaddr_ref_reg')));
  1536. end
  1537. else
  1538. begin
  1539. { add the symbol's value to the base of the reference, and if the }
  1540. { reference doesn't have a base, create one }
  1541. reference_reset(tmpref);
  1542. tmpref.offset := ref2.offset;
  1543. tmpref.symbol := ref2.symbol;
  1544. tmpref.relsymbol := ref2.relsymbol;
  1545. tmpref.refaddr := addr_hi;
  1546. if ref2.base<> NR_NO then
  1547. begin
  1548. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,r,
  1549. ref2.base,tmpref));
  1550. end
  1551. else
  1552. list.concat(taicpu.op_reg_ref(A_LIS,r,tmpref));
  1553. tmpref.base := NR_NO;
  1554. tmpref.refaddr := addr_lo;
  1555. { can be folded with one of the next instructions by the }
  1556. { optimizer probably }
  1557. list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,r,tmpref));
  1558. end
  1559. end
  1560. else if ref2.offset <> 0 Then
  1561. if ref2.base <> NR_NO then
  1562. a_op_const_reg_reg(list,OP_ADD,OS_32,ref2.offset,ref2.base,r)
  1563. { FixRef makes sure that "(ref.index <> R_NO) and (ref.offset <> 0)" never}
  1564. { occurs, so now only ref.offset has to be loaded }
  1565. else
  1566. a_load_const_reg(list,OS_32,ref2.offset,r)
  1567. else if ref.index <> NR_NO Then
  1568. list.concat(taicpu.op_reg_reg_reg(A_ADD,r,ref2.base,ref2.index))
  1569. else if (ref2.base <> NR_NO) and
  1570. (r <> ref2.base) then
  1571. a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref2.base,r)
  1572. else
  1573. list.concat(taicpu.op_reg_const(A_LI,r,0));
  1574. end;
  1575. { ************* concatcopy ************ }
  1576. {$ifndef ppc603}
  1577. const
  1578. maxmoveunit = 8;
  1579. {$else ppc603}
  1580. const
  1581. maxmoveunit = 4;
  1582. {$endif ppc603}
  1583. procedure tcgppc.g_concatcopy(list : taasmoutput;const source,dest : treference;len : aint);
  1584. var
  1585. countreg: TRegister;
  1586. src, dst: TReference;
  1587. lab: tasmlabel;
  1588. count, count2: aint;
  1589. size: tcgsize;
  1590. begin
  1591. {$ifdef extdebug}
  1592. if len > high(longint) then
  1593. internalerror(2002072704);
  1594. {$endif extdebug}
  1595. { make sure short loads are handled as optimally as possible }
  1596. if (len <= maxmoveunit) and
  1597. (byte(len) in [1,2,4,8]) then
  1598. begin
  1599. if len < 8 then
  1600. begin
  1601. size := int_cgsize(len);
  1602. a_load_ref_ref(list,size,size,source,dest);
  1603. end
  1604. else
  1605. begin
  1606. a_reg_alloc(list,NR_F0);
  1607. a_loadfpu_ref_reg(list,OS_F64,source,NR_F0);
  1608. a_loadfpu_reg_ref(list,OS_F64,NR_F0,dest);
  1609. a_reg_dealloc(list,NR_F0);
  1610. end;
  1611. exit;
  1612. end;
  1613. count := len div maxmoveunit;
  1614. reference_reset(src);
  1615. reference_reset(dst);
  1616. { load the address of source into src.base }
  1617. if (count > 4) or
  1618. not issimpleref(source) or
  1619. ((source.index <> NR_NO) and
  1620. ((source.offset + longint(len)) > high(smallint))) then
  1621. begin
  1622. src.base := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1623. a_loadaddr_ref_reg(list,source,src.base);
  1624. end
  1625. else
  1626. begin
  1627. src := source;
  1628. end;
  1629. { load the address of dest into dst.base }
  1630. if (count > 4) or
  1631. not issimpleref(dest) or
  1632. ((dest.index <> NR_NO) and
  1633. ((dest.offset + longint(len)) > high(smallint))) then
  1634. begin
  1635. dst.base := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1636. a_loadaddr_ref_reg(list,dest,dst.base);
  1637. end
  1638. else
  1639. begin
  1640. dst := dest;
  1641. end;
  1642. {$ifndef ppc603}
  1643. if count > 4 then
  1644. { generate a loop }
  1645. begin
  1646. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1647. { have to be set to 8. I put an Inc there so debugging may be }
  1648. { easier (should offset be different from zero here, it will be }
  1649. { easy to notice in the generated assembler }
  1650. inc(dst.offset,8);
  1651. inc(src.offset,8);
  1652. list.concat(taicpu.op_reg_reg_const(A_SUBI,src.base,src.base,8));
  1653. list.concat(taicpu.op_reg_reg_const(A_SUBI,dst.base,dst.base,8));
  1654. countreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1655. a_load_const_reg(list,OS_32,count,countreg);
  1656. { explicitely allocate R_0 since it can be used safely here }
  1657. { (for holding date that's being copied) }
  1658. a_reg_alloc(list,NR_F0);
  1659. objectlibrary.getlabel(lab);
  1660. a_label(list, lab);
  1661. list.concat(taicpu.op_reg_reg_const(A_SUBIC_,countreg,countreg,1));
  1662. list.concat(taicpu.op_reg_ref(A_LFDU,NR_F0,src));
  1663. list.concat(taicpu.op_reg_ref(A_STFDU,NR_F0,dst));
  1664. a_jmp(list,A_BC,C_NE,0,lab);
  1665. a_reg_dealloc(list,NR_F0);
  1666. len := len mod 8;
  1667. end;
  1668. count := len div 8;
  1669. if count > 0 then
  1670. { unrolled loop }
  1671. begin
  1672. a_reg_alloc(list,NR_F0);
  1673. for count2 := 1 to count do
  1674. begin
  1675. a_loadfpu_ref_reg(list,OS_F64,src,NR_F0);
  1676. a_loadfpu_reg_ref(list,OS_F64,NR_F0,dst);
  1677. inc(src.offset,8);
  1678. inc(dst.offset,8);
  1679. end;
  1680. a_reg_dealloc(list,NR_F0);
  1681. len := len mod 8;
  1682. end;
  1683. if (len and 4) <> 0 then
  1684. begin
  1685. a_reg_alloc(list,NR_R0);
  1686. a_load_ref_reg(list,OS_32,OS_32,src,NR_R0);
  1687. a_load_reg_ref(list,OS_32,OS_32,NR_R0,dst);
  1688. inc(src.offset,4);
  1689. inc(dst.offset,4);
  1690. a_reg_dealloc(list,NR_R0);
  1691. end;
  1692. {$else not ppc603}
  1693. if count > 4 then
  1694. { generate a loop }
  1695. begin
  1696. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1697. { have to be set to 4. I put an Inc there so debugging may be }
  1698. { easier (should offset be different from zero here, it will be }
  1699. { easy to notice in the generated assembler }
  1700. inc(dst.offset,4);
  1701. inc(src.offset,4);
  1702. list.concat(taicpu.op_reg_reg_const(A_SUBI,src.base,src.base,4));
  1703. list.concat(taicpu.op_reg_reg_const(A_SUBI,dst.base,dst.base,4));
  1704. countreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1705. a_load_const_reg(list,OS_32,count,countreg);
  1706. { explicitely allocate R_0 since it can be used safely here }
  1707. { (for holding date that's being copied) }
  1708. a_reg_alloc(list,NR_R0);
  1709. objectlibrary.getlabel(lab);
  1710. a_label(list, lab);
  1711. list.concat(taicpu.op_reg_reg_const(A_SUBIC_,countreg,countreg,1));
  1712. list.concat(taicpu.op_reg_ref(A_LWZU,NR_R0,src));
  1713. list.concat(taicpu.op_reg_ref(A_STWU,NR_R0,dst));
  1714. a_jmp(list,A_BC,C_NE,0,lab);
  1715. a_reg_dealloc(list,NR_R0);
  1716. len := len mod 4;
  1717. end;
  1718. count := len div 4;
  1719. if count > 0 then
  1720. { unrolled loop }
  1721. begin
  1722. a_reg_alloc(list,NR_R0);
  1723. for count2 := 1 to count do
  1724. begin
  1725. a_load_ref_reg(list,OS_32,OS_32,src,NR_R0);
  1726. a_load_reg_ref(list,OS_32,OS_32,NR_R0,dst);
  1727. inc(src.offset,4);
  1728. inc(dst.offset,4);
  1729. end;
  1730. a_reg_dealloc(list,NR_R0);
  1731. len := len mod 4;
  1732. end;
  1733. {$endif not ppc603}
  1734. { copy the leftovers }
  1735. if (len and 2) <> 0 then
  1736. begin
  1737. a_reg_alloc(list,NR_R0);
  1738. a_load_ref_reg(list,OS_16,OS_16,src,NR_R0);
  1739. a_load_reg_ref(list,OS_16,OS_16,NR_R0,dst);
  1740. inc(src.offset,2);
  1741. inc(dst.offset,2);
  1742. a_reg_dealloc(list,NR_R0);
  1743. end;
  1744. if (len and 1) <> 0 then
  1745. begin
  1746. a_reg_alloc(list,NR_R0);
  1747. a_load_ref_reg(list,OS_8,OS_8,src,NR_R0);
  1748. a_load_reg_ref(list,OS_8,OS_8,NR_R0,dst);
  1749. a_reg_dealloc(list,NR_R0);
  1750. end;
  1751. end;
  1752. procedure tcgppc.g_overflowcheck(list: taasmoutput; const l: tlocation; def: tdef);
  1753. var
  1754. hl : tasmlabel;
  1755. begin
  1756. if not(cs_check_overflow in aktlocalswitches) then
  1757. exit;
  1758. objectlibrary.getlabel(hl);
  1759. if not ((def.deftype=pointerdef) or
  1760. ((def.deftype=orddef) and
  1761. (torddef(def).typ in [u64bit,u16bit,u32bit,u8bit,uchar,
  1762. bool8bit,bool16bit,bool32bit]))) then
  1763. begin
  1764. list.concat(taicpu.op_reg(A_MCRXR,NR_CR7));
  1765. a_jmp(list,A_BC,C_NO,7,hl)
  1766. end
  1767. else
  1768. a_jmp_cond(list,OC_AE,hl);
  1769. a_call_name(list,'FPC_OVERFLOW');
  1770. a_label(list,hl);
  1771. end;
  1772. procedure tcgppc.g_intf_wrapper(list: TAAsmoutput; procdef: tprocdef; const labelname: string; ioffset: longint);
  1773. procedure loadvmttor11;
  1774. var
  1775. href : treference;
  1776. begin
  1777. reference_reset_base(href,NR_R3,0);
  1778. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R11);
  1779. end;
  1780. procedure op_onr11methodaddr;
  1781. var
  1782. href : treference;
  1783. begin
  1784. if (procdef.extnumber=$ffff) then
  1785. Internalerror(200006139);
  1786. { call/jmp vmtoffs(%eax) ; method offs }
  1787. reference_reset_base(href,NR_R11,procdef._class.vmtmethodoffset(procdef.extnumber));
  1788. if not((longint(href.offset) >= low(smallint)) and
  1789. (longint(href.offset) <= high(smallint))) then
  1790. begin
  1791. list.concat(taicpu.op_reg_reg_const(A_ADDIS,NR_R11,NR_R11,
  1792. smallint((href.offset shr 16)+ord(smallint(href.offset and $ffff) < 0))));
  1793. href.offset := smallint(href.offset and $ffff);
  1794. end;
  1795. list.concat(taicpu.op_reg_ref(A_LWZ,NR_R11,href));
  1796. list.concat(taicpu.op_reg(A_MTCTR,NR_R11));
  1797. list.concat(taicpu.op_none(A_BCTR));
  1798. end;
  1799. var
  1800. make_global : boolean;
  1801. begin
  1802. if procdef.proctypeoption<>potype_none then
  1803. Internalerror(200006137);
  1804. if not assigned(procdef._class) or
  1805. (procdef.procoptions*[po_classmethod, po_staticmethod,
  1806. po_methodpointer, po_interrupt, po_iocheck]<>[]) then
  1807. Internalerror(200006138);
  1808. if procdef.owner.symtabletype<>objectsymtable then
  1809. Internalerror(200109191);
  1810. make_global:=false;
  1811. if (not current_module.is_unit) or
  1812. (cs_create_smart in aktmoduleswitches) or
  1813. (procdef.owner.defowner.owner.symtabletype=globalsymtable) then
  1814. make_global:=true;
  1815. if make_global then
  1816. List.concat(Tai_symbol.Createname_global(labelname,AT_FUNCTION,0))
  1817. else
  1818. List.concat(Tai_symbol.Createname(labelname,AT_FUNCTION,0));
  1819. { set param1 interface to self }
  1820. g_adjust_self_value(list,procdef,ioffset);
  1821. { case 4 }
  1822. if po_virtualmethod in procdef.procoptions then
  1823. begin
  1824. loadvmttor11;
  1825. op_onr11methodaddr;
  1826. end
  1827. { case 0 }
  1828. else
  1829. list.concat(taicpu.op_sym(A_B,objectlibrary.newasmsymbol(procdef.mangledname,AB_EXTERNAL,AT_FUNCTION)));
  1830. List.concat(Tai_symbol_end.Createname(labelname));
  1831. end;
  1832. {***************** This is private property, keep out! :) *****************}
  1833. function tcgppc.issimpleref(const ref: treference): boolean;
  1834. begin
  1835. if (ref.base = NR_NO) and
  1836. (ref.index <> NR_NO) then
  1837. internalerror(200208101);
  1838. result :=
  1839. not(assigned(ref.symbol)) and
  1840. (((ref.index = NR_NO) and
  1841. (ref.offset >= low(smallint)) and
  1842. (ref.offset <= high(smallint))) or
  1843. ((ref.index <> NR_NO) and
  1844. (ref.offset = 0)));
  1845. end;
  1846. function tcgppc.fixref(list: taasmoutput; var ref: treference): boolean;
  1847. var
  1848. tmpreg: tregister;
  1849. begin
  1850. result := false;
  1851. if (ref.base = NR_NO) then
  1852. begin
  1853. ref.base := ref.index;
  1854. ref.base := NR_NO;
  1855. end;
  1856. if (ref.base <> NR_NO) then
  1857. begin
  1858. if (ref.index <> NR_NO) and
  1859. ((ref.offset <> 0) or assigned(ref.symbol)) then
  1860. begin
  1861. result := true;
  1862. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1863. list.concat(taicpu.op_reg_reg_reg(
  1864. A_ADD,tmpreg,ref.base,ref.index));
  1865. ref.index := NR_NO;
  1866. ref.base := tmpreg;
  1867. end
  1868. end
  1869. else
  1870. if ref.index <> NR_NO then
  1871. internalerror(200208102);
  1872. end;
  1873. { find out whether a is of the form 11..00..11b or 00..11...00. If }
  1874. { that's the case, we can use rlwinm to do an AND operation }
  1875. function tcgppc.get_rlwi_const(a: aint; var l1, l2: longint): boolean;
  1876. var
  1877. temp : longint;
  1878. testbit : aint;
  1879. compare: boolean;
  1880. begin
  1881. get_rlwi_const := false;
  1882. if (a = 0) or (a = -1) then
  1883. exit;
  1884. { start with the lowest bit }
  1885. testbit := 1;
  1886. { check its value }
  1887. compare := boolean(a and testbit);
  1888. { find out how long the run of bits with this value is }
  1889. { (it's impossible that all bits are 1 or 0, because in that case }
  1890. { this function wouldn't have been called) }
  1891. l1 := 31;
  1892. while (((a and testbit) <> 0) = compare) do
  1893. begin
  1894. testbit := testbit shl 1;
  1895. dec(l1);
  1896. end;
  1897. { check the length of the run of bits that comes next }
  1898. compare := not compare;
  1899. l2 := l1;
  1900. while (((a and testbit) <> 0) = compare) and
  1901. (l2 >= 0) do
  1902. begin
  1903. testbit := testbit shl 1;
  1904. dec(l2);
  1905. end;
  1906. { and finally the check whether the rest of the bits all have the }
  1907. { same value }
  1908. compare := not compare;
  1909. temp := l2;
  1910. if temp >= 0 then
  1911. if (a shr (31-temp)) <> ((-ord(compare)) shr (31-temp)) then
  1912. exit;
  1913. { we have done "not(not(compare))", so compare is back to its }
  1914. { initial value. If the lowest bit was 0, a is of the form }
  1915. { 00..11..00 and we need "rlwinm reg,reg,0,l2+1,l1", (+1 }
  1916. { because l2 now contains the position of the last zero of the }
  1917. { first run instead of that of the first 1) so switch l1 and l2 }
  1918. { in that case (we will generate "rlwinm reg,reg,0,l1,l2") }
  1919. if not compare then
  1920. begin
  1921. temp := l1;
  1922. l1 := l2+1;
  1923. l2 := temp;
  1924. end
  1925. else
  1926. { otherwise, l1 currently contains the position of the last }
  1927. { zero instead of that of the first 1 of the second run -> +1 }
  1928. inc(l1);
  1929. { the following is the same as "if l1 = -1 then l1 := 31;" }
  1930. l1 := l1 and 31;
  1931. l2 := l2 and 31;
  1932. get_rlwi_const := true;
  1933. end;
  1934. procedure tcgppc.a_load_store(list:taasmoutput;op: tasmop;reg:tregister;
  1935. ref: treference);
  1936. var
  1937. tmpreg: tregister;
  1938. tmpref: treference;
  1939. largeOffset: Boolean;
  1940. begin
  1941. tmpreg := NR_NO;
  1942. if target_info.system = system_powerpc_macos then
  1943. begin
  1944. largeOffset:= (cardinal(ref.offset-low(smallint)) >
  1945. high(smallint)-low(smallint));
  1946. if assigned(ref.symbol) then
  1947. begin {Load symbol's value}
  1948. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1949. reference_reset(tmpref);
  1950. tmpref.symbol := ref.symbol;
  1951. tmpref.base := NR_RTOC;
  1952. if macos_direct_globals then
  1953. list.concat(taicpu.op_reg_ref(A_LA,tmpreg,tmpref))
  1954. else
  1955. list.concat(taicpu.op_reg_ref(A_LWZ,tmpreg,tmpref));
  1956. end;
  1957. if largeOffset then
  1958. begin {Add hi part of offset}
  1959. reference_reset(tmpref);
  1960. if Smallint(Lo(ref.offset)) < 0 then
  1961. tmpref.offset := Hi(ref.offset) + 1 {Compensate when lo part is negative}
  1962. else
  1963. tmpref.offset := Hi(ref.offset);
  1964. if (tmpreg <> NR_NO) then
  1965. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,tmpreg, tmpreg,tmpref))
  1966. else
  1967. begin
  1968. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1969. list.concat(taicpu.op_reg_ref(A_LIS,tmpreg,tmpref));
  1970. end;
  1971. end;
  1972. if (tmpreg <> NR_NO) then
  1973. begin
  1974. {Add content of base register}
  1975. if ref.base <> NR_NO then
  1976. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,
  1977. ref.base,tmpreg));
  1978. {Make ref ready to be used by op}
  1979. ref.symbol:= nil;
  1980. ref.base:= tmpreg;
  1981. if largeOffset then
  1982. ref.offset := Smallint(Lo(ref.offset));
  1983. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1984. //list.concat(tai_comment.create(strpnew('*** a_load_store indirect global')));
  1985. end
  1986. else
  1987. list.concat(taicpu.op_reg_ref(op,reg,ref));
  1988. end
  1989. else {if target_info.system <> system_powerpc_macos}
  1990. begin
  1991. if assigned(ref.symbol) or
  1992. (cardinal(ref.offset-low(smallint)) >
  1993. high(smallint)-low(smallint)) then
  1994. begin
  1995. tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  1996. reference_reset(tmpref);
  1997. tmpref.symbol := ref.symbol;
  1998. tmpref.relsymbol := ref.relsymbol;
  1999. tmpref.offset := ref.offset;
  2000. tmpref.refaddr := addr_hi;
  2001. if ref.base <> NR_NO then
  2002. list.concat(taicpu.op_reg_reg_ref(A_ADDIS,tmpreg,
  2003. ref.base,tmpref))
  2004. else
  2005. list.concat(taicpu.op_reg_ref(A_LIS,tmpreg,tmpref));
  2006. ref.base := tmpreg;
  2007. ref.refaddr := addr_lo;
  2008. list.concat(taicpu.op_reg_ref(op,reg,ref));
  2009. end
  2010. else
  2011. list.concat(taicpu.op_reg_ref(op,reg,ref));
  2012. end;
  2013. end;
  2014. procedure tcgppc.a_jmp(list: taasmoutput; op: tasmop; c: tasmcondflag;
  2015. crval: longint; l: tasmlabel);
  2016. var
  2017. p: taicpu;
  2018. begin
  2019. p := taicpu.op_sym(op,objectlibrary.newasmsymbol(l.name,AB_EXTERNAL,AT_FUNCTION));
  2020. if op <> A_B then
  2021. create_cond_norm(c,crval,p.condition);
  2022. p.is_jmp := true;
  2023. list.concat(p)
  2024. end;
  2025. procedure tcg64fppc.a_op64_reg_reg(list : taasmoutput;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  2026. begin
  2027. a_op64_reg_reg_reg(list,op,size,regsrc,regdst,regdst);
  2028. end;
  2029. procedure tcg64fppc.a_op64_const_reg(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  2030. begin
  2031. a_op64_const_reg_reg(list,op,size,value,reg,reg);
  2032. end;
  2033. procedure tcg64fppc.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
  2034. begin
  2035. case op of
  2036. OP_AND,OP_OR,OP_XOR:
  2037. begin
  2038. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
  2039. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
  2040. end;
  2041. OP_ADD:
  2042. begin
  2043. list.concat(taicpu.op_reg_reg_reg(A_ADDC,regdst.reglo,regsrc1.reglo,regsrc2.reglo));
  2044. list.concat(taicpu.op_reg_reg_reg(A_ADDE,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  2045. end;
  2046. OP_SUB:
  2047. begin
  2048. list.concat(taicpu.op_reg_reg_reg(A_SUBC,regdst.reglo,regsrc2.reglo,regsrc1.reglo));
  2049. list.concat(taicpu.op_reg_reg_reg(A_SUBFE,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  2050. end;
  2051. else
  2052. internalerror(2002072801);
  2053. end;
  2054. end;
  2055. procedure tcg64fppc.a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);
  2056. const
  2057. ops: array[boolean,1..3] of tasmop = ((A_ADDIC,A_ADDC,A_ADDZE),
  2058. (A_SUBIC,A_SUBC,A_ADDME));
  2059. var
  2060. tmpreg: tregister;
  2061. tmpreg64: tregister64;
  2062. issub: boolean;
  2063. begin
  2064. case op of
  2065. OP_AND,OP_OR,OP_XOR:
  2066. begin
  2067. cg.a_op_const_reg_reg(list,op,OS_32,aint(value),regsrc.reglo,regdst.reglo);
  2068. cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
  2069. regdst.reghi);
  2070. end;
  2071. OP_ADD, OP_SUB:
  2072. begin
  2073. if (value < 0) then
  2074. begin
  2075. if op = OP_ADD then
  2076. op := OP_SUB
  2077. else
  2078. op := OP_ADD;
  2079. value := -value;
  2080. end;
  2081. if (longint(value) <> 0) then
  2082. begin
  2083. issub := op = OP_SUB;
  2084. if (value > 0) and
  2085. (value-ord(issub) <= 32767) then
  2086. begin
  2087. list.concat(taicpu.op_reg_reg_const(ops[issub,1],
  2088. regdst.reglo,regsrc.reglo,longint(value)));
  2089. list.concat(taicpu.op_reg_reg(ops[issub,3],
  2090. regdst.reghi,regsrc.reghi));
  2091. end
  2092. else if ((value shr 32) = 0) then
  2093. begin
  2094. tmpreg := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2095. cg.a_load_const_reg(list,OS_32,cardinal(value),tmpreg);
  2096. list.concat(taicpu.op_reg_reg_reg(ops[issub,2],
  2097. regdst.reglo,regsrc.reglo,tmpreg));
  2098. list.concat(taicpu.op_reg_reg(ops[issub,3],
  2099. regdst.reghi,regsrc.reghi));
  2100. end
  2101. else
  2102. begin
  2103. tmpreg64.reglo := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2104. tmpreg64.reghi := tcgppc(cg).rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
  2105. a_load64_const_reg(list,value,tmpreg64);
  2106. a_op64_reg_reg_reg(list,op,size,tmpreg64,regsrc,regdst);
  2107. end
  2108. end
  2109. else
  2110. begin
  2111. cg.a_load_reg_reg(list,OS_INT,OS_INT,regsrc.reglo,regdst.reglo);
  2112. cg.a_op_const_reg_reg(list,op,OS_32,aint(value shr 32),regsrc.reghi,
  2113. regdst.reghi);
  2114. end;
  2115. end;
  2116. else
  2117. internalerror(2002072802);
  2118. end;
  2119. end;
  2120. begin
  2121. cg := tcgppc.create;
  2122. cg64 :=tcg64fppc.create;
  2123. end.
  2124. {
  2125. $Log$
  2126. Revision 1.196 2005-03-25 21:55:43 jonas
  2127. * removed some unused variables
  2128. Revision 1.195 2005/02/14 17:13:10 peter
  2129. * truncate log
  2130. Revision 1.194 2005/02/13 18:55:19 florian
  2131. + overflow checking for the arm
  2132. Revision 1.193 2005/01/24 22:08:32 peter
  2133. * interface wrapper generation moved to cgobj
  2134. * generate interface wrappers after the module is parsed
  2135. Revision 1.192 2005/01/13 22:02:40 jonas
  2136. * r2 can be used by the register allocator under Darwin
  2137. * merged the initialisations of the fpu register allocator for AIX and
  2138. SYSV
  2139. Revision 1.191 2005/01/10 21:50:05 jonas
  2140. + support for passing records in registers under darwin
  2141. * tcgpara now also has an intsize field, which contains the size in
  2142. bytes of the whole parameter
  2143. Revision 1.190 2005/01/05 19:01:53 karoly
  2144. * sysv abi also uses F0-F13 as volatile registers
  2145. }